hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
/* Drive strength */
- io_write_and_or(sd, 0x14, 0xc0, pdata->drive_strength.data<<4 |
- pdata->drive_strength.clock<<2 |
- pdata->drive_strength.sync);
+ io_write_and_or(sd, 0x14, 0xc0,
+ pdata->dr_str_data << 4 |
+ pdata->dr_str_clk << 2 |
+ pdata->dr_str_sync);
/* HDMI free run */
cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
ADV7842_SELECT_SDP_YC,
};
+enum adv7842_drive_strength {
+ ADV7842_DR_STR_LOW = 0,
+ ADV7842_DR_STR_MEDIUM_LOW = 1,
+ ADV7842_DR_STR_MEDIUM_HIGH = 2,
+ ADV7842_DR_STR_HIGH = 3,
+};
+
struct adv7842_sdp_csc_coeff {
bool manual;
uint16_t scaling;
unsigned output_bus_lsb_to_msb:1;
/* IO register 0x14 */
- struct {
- unsigned data:2;
- unsigned clock:2;
- unsigned sync:2;
- } drive_strength;
+ enum adv7842_drive_strength dr_str_data;
+ enum adv7842_drive_strength dr_str_clk;
+ enum adv7842_drive_strength dr_str_sync;
/*
* IO register 0x19: Adjustment to the LLC DLL phase in