goto err_of;
}
- clk_prepare_enable(clk);
- clk_prepare_enable(icnclk);
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to prepare clock\n");
+ goto err_of;
+ }
+
+ ret = clk_prepare_enable(icnclk);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to prepare icn clock\n");
+ goto err_icnclk;
+ }
/* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
err_out:
clk_disable_unprepare(icnclk);
+err_icnclk:
clk_disable_unprepare(clk);
err_of:
sdhci_pltfm_free(pdev);
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct st_mmc_platform_data *pdata = sdhci_pltfm_priv(pltfm_host);
struct device_node *np = dev->of_node;
+ int ret;
+
+ ret = clk_prepare_enable(pltfm_host->clk);
+ if (ret)
+ return ret;
- clk_prepare_enable(pltfm_host->clk);
- clk_prepare_enable(pdata->icnclk);
+ ret = clk_prepare_enable(pdata->icnclk);
+ if (ret) {
+ clk_disable_unprepare(pltfm_host->clk);
+ return ret;
+ }
if (pdata->rstc)
reset_control_deassert(pdata->rstc);