dt-bindings: clk: sun5i: add DRAM gates compatible

The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).

Use a simple gates driver to support the one found in the A13 / R8 SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 9de34a83202308dfabdb16644fdc4c38fae6661f..1bf588e11d46fa585b876aad8a59e7c0260013bc 100644 (file)
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -64,6 +64,7 @@ Required properties:
        "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
        "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
        "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
+       "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
        "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
        "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
        "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80