ARM: rockchip: fix the SMP code style

Use the below scripts to check:
scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 4187ac2b01b32a826d8bace9e91874ac15c5646f..7ebd1c1a98c6d5f56481c88f029adcbe57487779 100644 (file)
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -100,7 +100,7 @@ static int pmu_set_power_domain(int pd, bool on)
                ret = pmu_power_domain_is_on(pd);
                if (ret < 0) {
                        pr_err("%s: could not read power domain state\n",
-                                __func__);
+                              __func__);
                        return ret;
                }
        }
@@ -129,7 +129,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
        if (cpu >= ncores) {
                pr_err("%s: cpu %d outside maximum number of cpus %d\n",
-                                                       __func__, cpu, ncores);
+                      __func__, cpu, ncores);
                return -ENXIO;
        }
 
@@ -139,7 +139,8 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
                return ret;
 
        if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
-               /* We communicate with the bootrom to active the cpus other
+               /*
+                * We communicate with the bootrom to active the cpus other
                 * than cpu0, after a blob of initialize code, they will
                 * stay at wfe state, once they are actived, they will check
                 * the mailbox:
@@ -148,11 +149,11 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
                 * The cpu0 need to wait the other cpus other than cpu0 entering
                 * the wfe state.The wait time is affected by many aspects.
                 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
-                * */
+                */
                mdelay(1); /* ensure the cpus other than cpu0 to startup */
 
                writel(virt_to_phys(rockchip_secondary_startup),
-                       sram_base_addr + 8);
+                      sram_base_addr + 8);
                writel(0xDEADBEAF, sram_base_addr + 4);
                dsb_sev();
        }
@@ -335,7 +336,7 @@ static int rockchip_cpu_kill(unsigned int cpu)
 static void rockchip_cpu_die(unsigned int cpu)
 {
        v7_exit_coherency_flush(louis);
-       while(1)
+       while (1)
                cpu_do_idle();
 }
 #endif
@@ -348,4 +349,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
        .cpu_die                = rockchip_cpu_die,
 #endif
 };
+
 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);