drm/i915/cnl: Add slice and subslice information to debugfs.
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 9 Aug 2017 20:07:02 +0000 (13:07 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 10 Aug 2017 20:59:29 +0000 (13:59 -0700)
A missing part to EU slice power gating is the
debugfs interface. This patch actually should have been
squashed to the initial EU slice power gating one.

v2: Initial patch was merged without this part.

Fixes: c7ae7e9ab207 ("drm/i915/cnl: Configure EU slice power gating.")
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170809200702.11236-1-rodrigo.vivi@intel.com
drivers/gpu/drm/i915/i915_debugfs.c

index 6480897bcaf438881b707a788b61956468785970..329fb3649dc30f7b056ab0b762f26df21018866d 100644 (file)
@@ -4560,7 +4560,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 
                sseu->slice_mask |= BIT(s);
 
-               if (IS_GEN9_BC(dev_priv))
+               if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
                        sseu->subslice_mask =
                                INTEL_INFO(dev_priv)->sseu.subslice_mask;