amd-xgbe: Simplify the burst length settings

Currently the driver hardcodes the PBLx8 setting.  Remove the need for
specifying the PBLx8 setting and automatically calculate based on the
specified PBL value. Since the PBLx8 setting applies to both Tx and Rx
use the same PBL value for both of them.

Also, the driver currently uses a bit field to set the AXI master burst
len setting. Change to the full bit field range and set the burst length
based on the specified value.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
index dc098832e0fee43fc4ba8a459074ca55569ecbad..6b5c72d276559dc2cffd6512303dfe81b2d01834 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
@@ -137,12 +137,19 @@
 #define DMA_MR_SWR_WIDTH               1
 #define DMA_SBMR_EAME_INDEX            11
 #define DMA_SBMR_EAME_WIDTH            1
-#define DMA_SBMR_BLEN_256_INDEX                7
-#define DMA_SBMR_BLEN_256_WIDTH                1
+#define DMA_SBMR_BLEN_INDEX            1
+#define DMA_SBMR_BLEN_WIDTH            7
 #define DMA_SBMR_UNDEF_INDEX           0
 #define DMA_SBMR_UNDEF_WIDTH           1
 
 /* DMA register values */
+#define DMA_SBMR_BLEN_256              256
+#define DMA_SBMR_BLEN_128              128
+#define DMA_SBMR_BLEN_64               64
+#define DMA_SBMR_BLEN_32               32
+#define DMA_SBMR_BLEN_16               16
+#define DMA_SBMR_BLEN_8                        8
+#define DMA_SBMR_BLEN_4                        4
 #define DMA_DSR_RPS_WIDTH              4
 #define DMA_DSR_TPS_WIDTH              4
 #define DMA_DSR_Q_WIDTH                        (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index 98da24964f1f7e3234f68faa718e3ab69bd13904..a51ece52905f7c0f4c744e453342e0916898db82 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -174,52 +174,30 @@ static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
        return ret;
 }
 
-static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
+static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata)
 {
+       unsigned int pblx8, pbl;
        unsigned int i;
 
-       for (i = 0; i < pdata->channel_count; i++)
-               XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,
-                                      pdata->pblx8);
-
-       return 0;
-}
-
-static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
-{
-       return XGMAC_DMA_IOREAD_BITS(pdata->channel[0], DMA_CH_TCR, PBL);
-}
-
-static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
-{
-       unsigned int i;
-
-       for (i = 0; i < pdata->channel_count; i++) {
-               if (!pdata->channel[i]->tx_ring)
-                       break;
+       pblx8 = DMA_PBL_X8_DISABLE;
+       pbl = pdata->pbl;
 
-               XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, PBL,
-                                      pdata->tx_pbl);
+       if (pdata->pbl > 32) {
+               pblx8 = DMA_PBL_X8_ENABLE;
+               pbl >>= 3;
        }
 
-       return 0;
-}
-
-static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
-{
-       return XGMAC_DMA_IOREAD_BITS(pdata->channel[0], DMA_CH_RCR, PBL);
-}
-
-static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
-{
-       unsigned int i;
-
        for (i = 0; i < pdata->channel_count; i++) {
-               if (!pdata->channel[i]->rx_ring)
-                       break;
+               XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,
+                                      pblx8);
+
+               if (pdata->channel[i]->tx_ring)
+                       XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,
+                                              PBL, pbl);
 
-               XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, PBL,
-                                      pdata->rx_pbl);
+               if (pdata->channel[i]->rx_ring)
+                       XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR,
+                                              PBL, pbl);
        }
 
        return 0;
@@ -2141,7 +2119,7 @@ static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
 
        /* Set the System Bus mode */
        XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
-       XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
+       XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN, pdata->blen >> 2);
 }
 
 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
@@ -3381,9 +3359,7 @@ static int xgbe_init(struct xgbe_prv_data *pdata)
        xgbe_config_dma_bus(pdata);
        xgbe_config_dma_cache(pdata);
        xgbe_config_osp_mode(pdata);
-       xgbe_config_pblx8(pdata);
-       xgbe_config_tx_pbl_val(pdata);
-       xgbe_config_rx_pbl_val(pdata);
+       xgbe_config_pbl_val(pdata);
        xgbe_config_rx_coalesce(pdata);
        xgbe_config_tx_coalesce(pdata);
        xgbe_config_rx_buffer_size(pdata);
@@ -3511,13 +3487,6 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
        /* For TX DMA Operating on Second Frame config */
        hw_if->config_osp_mode = xgbe_config_osp_mode;
 
-       /* For RX and TX PBL config */
-       hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
-       hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
-       hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
-       hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
-       hw_if->config_pblx8 = xgbe_config_pblx8;
-
        /* For MMC statistics support */
        hw_if->tx_mmc_int = xgbe_tx_mmc_int;
        hw_if->rx_mmc_int = xgbe_rx_mmc_int;

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
index 982368b560ba2ed00b7c08cb528fcfd9774b0efb..8eec9f5991f5412b2b1827dcddd96a3a20ac1473 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
@@ -140,14 +140,13 @@ static void xgbe_default_config(struct xgbe_prv_data *pdata)
 {
        DBGPR("-->xgbe_default_config\n");
 
-       pdata->pblx8 = DMA_PBL_X8_ENABLE;
+       pdata->blen = DMA_SBMR_BLEN_256;
+       pdata->pbl = DMA_PBL_128;
        pdata->tx_sf_mode = MTL_TSF_ENABLE;
        pdata->tx_threshold = MTL_TX_THRESHOLD_64;
-       pdata->tx_pbl = DMA_PBL_16;
        pdata->tx_osp_mode = DMA_OSP_ENABLE;
        pdata->rx_sf_mode = MTL_RSF_DISABLE;
        pdata->rx_threshold = MTL_RX_THRESHOLD_64;
-       pdata->rx_pbl = DMA_PBL_16;
        pdata->pause_autoneg = 1;
        pdata->tx_pause = 1;
        pdata->rx_pause = 1;

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index 46780aa74301e1e061b141bf0840883b498a5dea..4bf82eb23ae6598edc326f7535cd28f55643ccd6 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -737,13 +737,6 @@ struct xgbe_hw_if {
        /* For TX DMA Operate on Second Frame config */
        int (*config_osp_mode)(struct xgbe_prv_data *);
 
-       /* For RX and TX PBL config */
-       int (*config_rx_pbl_val)(struct xgbe_prv_data *);
-       int (*get_rx_pbl_val)(struct xgbe_prv_data *);
-       int (*config_tx_pbl_val)(struct xgbe_prv_data *);
-       int (*get_tx_pbl_val)(struct xgbe_prv_data *);
-       int (*config_pblx8)(struct xgbe_prv_data *);
-
        /* For MMC statistics */
        void (*rx_mmc_int)(struct xgbe_prv_data *);
        void (*tx_mmc_int)(struct xgbe_prv_data *);
@@ -1029,19 +1022,18 @@ struct xgbe_prv_data {
        unsigned int rx_q_count;
 
        /* Tx/Rx common settings */
-       unsigned int pblx8;
+       unsigned int blen;
+       unsigned int pbl;
 
        /* Tx settings */
        unsigned int tx_sf_mode;
        unsigned int tx_threshold;
-       unsigned int tx_pbl;
        unsigned int tx_osp_mode;
        unsigned int tx_max_fifo_size;
 
        /* Rx settings */
        unsigned int rx_sf_mode;
        unsigned int rx_threshold;
-       unsigned int rx_pbl;
        unsigned int rx_max_fifo_size;
 
        /* Tx coalescing settings */