dt-bindings: cpufreq: move MediaTek cpufreq dt-bindings document to proper place

The old place is Documentation/devicetree/bindings/clock/ that would
let people hard to find how to use MediaTek cpufreq driver, so moving
it to the appropriate place as other cpufreq drivers done would be
better.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

diff --git a/Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt b/Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
deleted file mode 100644 (file)
index 52b457c..0000000
--- a/Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
-
-Required properties:
-- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
-- clock-names: Should contain the following:
-       "cpu"           - The multiplexer for clock input of CPU cluster.
-       "intermediate"  - A parent of "cpu" clock which is used as "intermediate" clock
-                         source (usually MAINPLL) when the original CPU PLL is under
-                         transition and not stable yet.
-       Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
-       generic clock consumer properties.
-- proc-supply: Regulator for Vproc of CPU cluster.
-
-Optional properties:
-- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
-              needs to do "voltage tracking" to step by step scale up/down Vproc and
-              Vsram to fit SoC specific needs. When absent, the voltage scaling
-              flow is handled by hardware, hence no software "voltage tracking" is
-              needed.
-
-Example:
---------
-       cpu0: cpu@0 {
-               device_type = "cpu";
-               compatible = "arm,cortex-a53";
-               reg = <0x000>;
-               enable-method = "psci";
-               cpu-idle-states = <&CPU_SLEEP_0>;
-               clocks = <&infracfg CLK_INFRA_CA53SEL>,
-                        <&apmixedsys CLK_APMIXED_MAINPLL>;
-               clock-names = "cpu", "intermediate";
-       };
-
-       cpu1: cpu@1 {
-               device_type = "cpu";
-               compatible = "arm,cortex-a53";
-               reg = <0x001>;
-               enable-method = "psci";
-               cpu-idle-states = <&CPU_SLEEP_0>;
-               clocks = <&infracfg CLK_INFRA_CA53SEL>,
-                        <&apmixedsys CLK_APMIXED_MAINPLL>;
-               clock-names = "cpu", "intermediate";
-       };
-
-       cpu2: cpu@100 {
-               device_type = "cpu";
-               compatible = "arm,cortex-a57";
-               reg = <0x100>;
-               enable-method = "psci";
-               cpu-idle-states = <&CPU_SLEEP_0>;
-               clocks = <&infracfg CLK_INFRA_CA57SEL>,
-                        <&apmixedsys CLK_APMIXED_MAINPLL>;
-               clock-names = "cpu", "intermediate";
-       };
-
-       cpu3: cpu@101 {
-               device_type = "cpu";
-               compatible = "arm,cortex-a57";
-               reg = <0x101>;
-               enable-method = "psci";
-               cpu-idle-states = <&CPU_SLEEP_0>;
-               clocks = <&infracfg CLK_INFRA_CA57SEL>,
-                        <&apmixedsys CLK_APMIXED_MAINPLL>;
-               clock-names = "cpu", "intermediate";
-       };
-
-       &cpu0 {
-               proc-supply = <&mt6397_vpca15_reg>;
-       };
-
-       &cpu1 {
-               proc-supply = <&mt6397_vpca15_reg>;
-       };
-
-       &cpu2 {
-               proc-supply = <&da9211_vcpu_reg>;
-               sram-supply = <&mt6397_vsramca7_reg>;
-       };
-
-       &cpu3 {
-               proc-supply = <&da9211_vcpu_reg>;
-               sram-supply = <&mt6397_vsramca7_reg>;
-       };

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
new file mode 100644 (file)
index 0000000..52b457c
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
@@ -0,0 +1,83 @@
+Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
+
+Required properties:
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
+- clock-names: Should contain the following:
+       "cpu"           - The multiplexer for clock input of CPU cluster.
+       "intermediate"  - A parent of "cpu" clock which is used as "intermediate" clock
+                         source (usually MAINPLL) when the original CPU PLL is under
+                         transition and not stable yet.
+       Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
+       generic clock consumer properties.
+- proc-supply: Regulator for Vproc of CPU cluster.
+
+Optional properties:
+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
+              needs to do "voltage tracking" to step by step scale up/down Vproc and
+              Vsram to fit SoC specific needs. When absent, the voltage scaling
+              flow is handled by hardware, hence no software "voltage tracking" is
+              needed.
+
+Example:
+--------
+       cpu0: cpu@0 {
+               device_type = "cpu";
+               compatible = "arm,cortex-a53";
+               reg = <0x000>;
+               enable-method = "psci";
+               cpu-idle-states = <&CPU_SLEEP_0>;
+               clocks = <&infracfg CLK_INFRA_CA53SEL>,
+                        <&apmixedsys CLK_APMIXED_MAINPLL>;
+               clock-names = "cpu", "intermediate";
+       };
+
+       cpu1: cpu@1 {
+               device_type = "cpu";
+               compatible = "arm,cortex-a53";
+               reg = <0x001>;
+               enable-method = "psci";
+               cpu-idle-states = <&CPU_SLEEP_0>;
+               clocks = <&infracfg CLK_INFRA_CA53SEL>,
+                        <&apmixedsys CLK_APMIXED_MAINPLL>;
+               clock-names = "cpu", "intermediate";
+       };
+
+       cpu2: cpu@100 {
+               device_type = "cpu";
+               compatible = "arm,cortex-a57";
+               reg = <0x100>;
+               enable-method = "psci";
+               cpu-idle-states = <&CPU_SLEEP_0>;
+               clocks = <&infracfg CLK_INFRA_CA57SEL>,
+                        <&apmixedsys CLK_APMIXED_MAINPLL>;
+               clock-names = "cpu", "intermediate";
+       };
+
+       cpu3: cpu@101 {
+               device_type = "cpu";
+               compatible = "arm,cortex-a57";
+               reg = <0x101>;
+               enable-method = "psci";
+               cpu-idle-states = <&CPU_SLEEP_0>;
+               clocks = <&infracfg CLK_INFRA_CA57SEL>,
+                        <&apmixedsys CLK_APMIXED_MAINPLL>;
+               clock-names = "cpu", "intermediate";
+       };
+
+       &cpu0 {
+               proc-supply = <&mt6397_vpca15_reg>;
+       };
+
+       &cpu1 {
+               proc-supply = <&mt6397_vpca15_reg>;
+       };
+
+       &cpu2 {
+               proc-supply = <&da9211_vcpu_reg>;
+               sram-supply = <&mt6397_vsramca7_reg>;
+       };
+
+       &cpu3 {
+               proc-supply = <&da9211_vcpu_reg>;
+               sram-supply = <&mt6397_vsramca7_reg>;
+       };