serial: exar: Move register defines from uapi header to consumer site

None of these registers is relevant for the userspace API.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c
index 9af4266eff96843a8559ee9fd1a0786dc0fe8134..f612da326e82bf0fc9142b8582fd304cff7cb574 100644 (file)
--- a/drivers/tty/serial/8250/8250_exar.c
+++ b/drivers/tty/serial/8250/8250_exar.c
@@ -34,6 +34,19 @@
 #define PCI_DEVICE_ID_EXAR_XR17V4358           0x4358
 #define PCI_DEVICE_ID_EXAR_XR17V8358           0x8358
 
+#define UART_EXAR_8XMODE       0x88    /* 8X sampling rate select */
+
+#define UART_EXAR_FCTR         0x08    /* Feature Control Register */
+#define UART_FCTR_EXAR_IRDA    0x10    /* IrDa data encode select */
+#define UART_FCTR_EXAR_485     0x20    /* Auto 485 half duplex dir ctl */
+#define UART_FCTR_EXAR_TRGA    0x00    /* FIFO trigger table A */
+#define UART_FCTR_EXAR_TRGB    0x60    /* FIFO trigger table B */
+#define UART_FCTR_EXAR_TRGC    0x80    /* FIFO trigger table C */
+#define UART_FCTR_EXAR_TRGD    0xc0    /* FIFO trigger table D programmable */
+
+#define UART_EXAR_TXTRG                0x0a    /* Tx FIFO trigger level write-only */
+#define UART_EXAR_RXTRG                0x0b    /* Rx FIFO trigger level write-only */
+
 #define UART_EXAR_MPIOINT_7_0  0x8f    /* MPIOINT[7:0] */
 #define UART_EXAR_MPIOLVL_7_0  0x90    /* MPIOLVL[7:0] */
 #define UART_EXAR_MPIO3T_7_0   0x91    /* MPIO3T[7:0] */

diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index ec6b5e3dcaaafc4352a6b017bca46d760c909c6d..6119516ef5fcd3a604ae0a41a70b9f6f51f7fa1d 100644 (file)
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -44,6 +44,12 @@
 
 #include "8250.h"
 
+/*
+ * These are definitions for the Exar XR17V35X and XR17(C|D)15X
+ */
+#define UART_EXAR_SLEEP                0x8b    /* Sleep mode */
+#define UART_EXAR_DVID         0x8d    /* Device identification */
+
 /*
  * Debugging.
  */

diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h
index 25b93a764a1a18a9c1bd6c314dec021b11870b64..5db76880b4adfc23fc86487d9816ad28df291973 100644 (file)
--- a/include/uapi/linux/serial_reg.h
+++ b/include/uapi/linux/serial_reg.h
@@ -366,24 +366,6 @@
 #define UART_OMAP_MDR1_CIR_MODE                0x06    /* CIR mode */
 #define UART_OMAP_MDR1_DISABLE         0x07    /* Disable (default state) */
 
-/*
- * These are definitions for the Exar XR17V35X and XR17(C|D)15X
- */
-#define UART_EXAR_8XMODE       0x88    /* 8X sampling rate select */
-#define UART_EXAR_SLEEP                0x8b    /* Sleep mode */
-#define UART_EXAR_DVID         0x8d    /* Device identification */
-
-#define UART_EXAR_FCTR         0x08    /* Feature Control Register */
-#define UART_FCTR_EXAR_IRDA    0x10    /* IrDa data encode select */
-#define UART_FCTR_EXAR_485     0x20    /* Auto 485 half duplex dir ctl */
-#define UART_FCTR_EXAR_TRGA    0x00    /* FIFO trigger table A */
-#define UART_FCTR_EXAR_TRGB    0x60    /* FIFO trigger table B */
-#define UART_FCTR_EXAR_TRGC    0x80    /* FIFO trigger table C */
-#define UART_FCTR_EXAR_TRGD    0xc0    /* FIFO trigger table D programmable */
-
-#define UART_EXAR_TXTRG                0x0a    /* Tx FIFO trigger level write-only */
-#define UART_EXAR_RXTRG                0x0b    /* Rx FIFO trigger level write-only */
-
 /*
  * These are definitions for the Altera ALTR_16550_F32/F64/F128
  * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs).