grace = time_after(jiffies, card->reset_jiffies + DIV_ROUND_UP(HZ, 8));
- if (is_next_generation(generation, card->bm_generation) ||
+ if ((is_next_generation(generation, card->bm_generation) &&
+ !card->bm_abdicate) ||
(card->bm_generation != generation && grace)) {
/*
* This first step is to figure out who is IRM and
smp_wmb();
card->generation = generation;
card->reset_jiffies = jiffies;
+ card->bm_abdicate = card->csr_abdicate;
+ card->csr_abdicate = false;
fw_schedule_bm_work(card, 0);
local_node = build_tree(card, self_ids, self_id_count);
/* Bit 8 (cmstr): */
value |= card->driver->read_csr_reg(card, CSR_STATE_CLEAR);
+ /* Bit 10 (abdicate): */
+ if (card->csr_abdicate)
+ value |= CSR_STATE_BIT_ABDICATE;
+
return value;
}
} else if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
card->driver->write_csr_reg(card, CSR_STATE_CLEAR,
be32_to_cpu(*data));
+ if (*data & cpu_to_be32(CSR_STATE_BIT_ABDICATE))
+ card->csr_abdicate = false;
} else {
rcode = RCODE_TYPE_ERROR;
}
} else if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
card->driver->write_csr_reg(card, CSR_STATE_SET,
be32_to_cpu(*data));
- /* FIXME: implement abdicate */
+ if (*data & cpu_to_be32(CSR_STATE_BIT_ABDICATE))
+ card->csr_abdicate = true;
} else {
rcode = RCODE_TYPE_ERROR;
}
break;
case CSR_RESET_START:
- if (tcode != TCODE_WRITE_QUADLET_REQUEST)
+ if (tcode == TCODE_WRITE_QUADLET_REQUEST)
+ card->csr_abdicate = false;
+ else
rcode = RCODE_TYPE_ERROR;
break;
int bm_retries;
int bm_generation;
__be32 bm_transaction_data[2];
+ bool bm_abdicate; /* value of csr_abdicate before last bus reset */
+ bool csr_abdicate; /* visible in CSR STATE_CLEAR/SET registers */
bool broadcast_channel_allocated;
u32 broadcast_channel;