drm/amdgpu: fetch cu_info once at init
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 3 May 2016 20:25:53 +0000 (16:25 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 11 May 2016 16:31:21 +0000 (12:31 -0400)
Fetch this info once at init and just store the results
for future requests.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
drivers/gpu/drm/amd/amdgpu/vi.c

index abe62ecaaef427cef0054aa6c4912c223292341b..6589d43bd094daf13ab4d7062f7213ad2749d85a 100644 (file)
@@ -1148,6 +1148,12 @@ struct amdgpu_gca_config {
        uint32_t macrotile_mode_array[16];
 };
 
+struct amdgpu_cu_info {
+       uint32_t number; /* total active CU number */
+       uint32_t ao_cu_mask;
+       uint32_t bitmap[4][4];
+};
+
 struct amdgpu_gfx {
        struct mutex                    gpu_clock_mutex;
        struct amdgpu_gca_config        config;
@@ -1180,9 +1186,10 @@ struct amdgpu_gfx {
        struct amdgpu_irq_src           priv_reg_irq;
        struct amdgpu_irq_src           priv_inst_irq;
        /* gfx status */
-       uint32_t gfx_current_status;
+       uint32_t                        gfx_current_status;
        /* ce ram size*/
-       unsigned ce_ram_size;
+       unsigned                        ce_ram_size;
+       struct amdgpu_cu_info           cu_info;
 };
 
 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
@@ -1794,13 +1801,6 @@ struct amdgpu_allowed_register_entry {
        bool grbm_indexed;
 };
 
-struct amdgpu_cu_info {
-       uint32_t number; /* total active CU number */
-       uint32_t ao_cu_mask;
-       uint32_t bitmap[4][4];
-};
-
-
 /*
  * ASIC specific functions.
  */
@@ -1818,7 +1818,6 @@ struct amdgpu_asic_funcs {
        u32 (*get_xclk)(struct amdgpu_device *adev);
        /* get the gpu clock counter */
        uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
-       int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
        /* MM block clocks */
        int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
        int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
@@ -2210,7 +2209,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
-#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
index 490464e39322e7fe6b0184a14a867cb3d3ed0f58..199f76baf22c3eea20207fec60c1e868d173d1cb 100644 (file)
@@ -793,7 +793,6 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
                                struct cgs_system_info *sys_info)
 {
        CGS_FUNC_ADEV;
-       struct amdgpu_cu_info cu_info;
 
        if (NULL == sys_info)
                return -ENODEV;
@@ -818,8 +817,7 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
                sys_info->value = adev->pg_flags;
                break;
        case CGS_SYSTEM_INFO_GFX_CU_INFO:
-               amdgpu_asic_get_cu_info(adev, &cu_info);
-               sys_info->value = cu_info.number;
+               sys_info->value = adev->gfx.cu_info.number;
                break;
        default:
                return -ENODEV;
index 7db271278e70f0644f68bb251b40b7fa1532e829..40a23704a981072472877fd14ccc2a8393391e3b 100644 (file)
@@ -427,7 +427,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
        }
        case AMDGPU_INFO_DEV_INFO: {
                struct drm_amdgpu_info_device dev_info = {};
-               struct amdgpu_cu_info cu_info;
 
                dev_info.device_id = dev->pdev->device;
                dev_info.chip_rev = adev->rev_id;
@@ -461,11 +460,11 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                                             AMDGPU_GPU_PAGE_SIZE;
                dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 
-               amdgpu_asic_get_cu_info(adev, &cu_info);
-               dev_info.cu_active_number = cu_info.number;
-               dev_info.cu_ao_mask = cu_info.ao_cu_mask;
+               dev_info.cu_active_number = adev->gfx.cu_info.number;
+               dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
                dev_info.ce_ram_size = adev->gfx.ce_ram_size;
-               memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
+               memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
+                      sizeof(adev->gfx.cu_info.bitmap));
                dev_info.vram_type = adev->mc.vram_type;
                dev_info.vram_bit_width = adev->mc.vram_width;
                dev_info.vce_harvest_config = adev->vce.harvest_config;
index c6127d66de11d39d2dc5722398557ce2b0f348db..68e569853c95a7cd6b4e34d241c4489b0660c4a8 100644 (file)
@@ -2007,7 +2007,6 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
        .get_xclk = &cik_get_xclk,
        .set_uvd_clocks = &cik_set_uvd_clocks,
        .set_vce_clocks = &cik_set_vce_clocks,
-       .get_cu_info = &gfx_v7_0_get_cu_info,
        /* these should be moved to their own ip modules */
        .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
        .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle,
index 03108909a2751d4b9f8c7d6b77fce2aacf4a107d..0014a9ceaf291868267b308d57fe647005f82a9c 100644 (file)
@@ -53,7 +53,6 @@
 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
-int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *);
 
 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
 MODULE_FIRMWARE("radeon/bonaire_me.bin");
@@ -882,6 +881,7 @@ static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
+static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 
 /*
  * Core functions
@@ -1718,6 +1718,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
        gfx_v7_0_tiling_mode_table_init(adev);
 
        gfx_v7_0_setup_rb(adev);
+       gfx_v7_0_get_cu_info(adev);
 
        /* set HW defaults for 3D engine */
        WREG32(mmCP_MEQ_THRESHOLDS,
@@ -3869,18 +3870,13 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
 
 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
 {
-       uint32_t tmp, active_cu_number;
-       struct amdgpu_cu_info cu_info;
-
-       gfx_v7_0_get_cu_info(adev, &cu_info);
-       tmp = cu_info.ao_cu_mask;
-       active_cu_number = cu_info.number;
+       u32 tmp;
 
-       WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp);
+       WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
 
        tmp = RREG32(mmRLC_MAX_PG_CU);
        tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
-       tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
+       tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
        WREG32(mmRLC_MAX_PG_CU, tmp);
 }
 
@@ -5015,14 +5011,11 @@ static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
 }
 
 
-int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
-                        struct amdgpu_cu_info *cu_info)
+static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
 {
        int i, j, k, counter, active_cu_number = 0;
        u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
-
-       if (!adev || !cu_info)
-               return -EINVAL;
+       struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
 
        memset(cu_info, 0, sizeof(*cu_info));
 
@@ -5053,6 +5046,4 @@ int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
 
        cu_info->number = active_cu_number;
        cu_info->ao_cu_mask = ao_cu_mask;
-
-       return 0;
 }
index c04bfbabfc880edc347fbbf9244c482b50cf5183..e747aa935c88dc2342562ed5f80f316f8e952490 100644 (file)
@@ -32,6 +32,5 @@ void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev);
 void gfx_v7_0_rlc_stop(struct amdgpu_device *adev);
 uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
-int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info);
 
 #endif
index 4ea4b4eb0bc5fb3879631eb621a35bcf17d3716b..7525f99858f13f0e7ecb3e8a4e2ecc76fdaf81eb 100644 (file)
@@ -636,6 +636,7 @@ static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
+static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
 
 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
@@ -3431,6 +3432,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
        gfx_v8_0_tiling_mode_table_init(adev);
 
        gfx_v8_0_setup_rb(adev);
+       gfx_v8_0_get_cu_info(adev);
 
        /* XXX SH_MEM regs */
        /* where to put LDS, scratch, GPUVM in FSA64 space */
@@ -6212,14 +6214,11 @@ static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
        return (~data) & mask;
 }
 
-int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
-                        struct amdgpu_cu_info *cu_info)
+static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
 {
        int i, j, k, counter, active_cu_number = 0;
        u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
-
-       if (!adev || !cu_info)
-               return -EINVAL;
+       struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
 
        memset(cu_info, 0, sizeof(*cu_info));
 
@@ -6250,6 +6249,4 @@ int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
 
        cu_info->number = active_cu_number;
        cu_info->ao_cu_mask = ao_cu_mask;
-
-       return 0;
 }
index 021e05193cb9630e1783a9d45f7c4742832e071a..16a49f53a2fa2aecbf78296e87100dcd36426647 100644 (file)
@@ -28,6 +28,5 @@ extern const struct amd_ip_funcs gfx_v8_0_ip_funcs;
 
 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
-int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info);
 
 #endif
index 31dd6304f2084ae681a1e4b409cab0534a55a946..b7da094f8bf9421e6c8b6715b50aa35cebc4c020 100644 (file)
@@ -1118,7 +1118,6 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
        .get_xclk = &vi_get_xclk,
        .set_uvd_clocks = &vi_set_uvd_clocks,
        .set_vce_clocks = &vi_set_vce_clocks,
-       .get_cu_info = &gfx_v8_0_get_cu_info,
        /* these should be moved to their own ip modules */
        .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
        .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,