outl(0x0, dev->iobase + APCI1564_DO_IRQ_REG);
outl(0x0, dev->iobase + APCI1564_WDOG_IRQ_REG);
if (devpriv->counters) {
- outl(0x0,
- devpriv->counters + APCI1564_COUNTER_IRQ_REG(0));
- outl(0x0,
- devpriv->counters + APCI1564_COUNTER_IRQ_REG(1));
- outl(0x0,
- devpriv->counters + APCI1564_COUNTER_IRQ_REG(2));
+ unsigned long iobase;
+
+ iobase = devpriv->counters + ADDI_TCW_IRQ_REG;
+ outl(0x0, iobase + APCI1564_COUNTER(0));
+ outl(0x0, iobase + APCI1564_COUNTER(1));
+ outl(0x0, iobase + APCI1564_COUNTER(2));
}
} else {
/* disable Timer interrupt */
{
struct apci1564_private *devpriv = dev->private;
unsigned int chan = CR_CHAN(insn->chanspec);
+ unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
unsigned int ctrl;
devpriv->tsk_current = current;
/* First Stop The Counter */
- ctrl = inl(devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
+ ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
ctrl &= 0xfffff9fe;
/* Stop The Timer */
- outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
+ outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
/* Set the reload value */
- outl(data[3], devpriv->counters + APCI1564_COUNTER_RELOAD_REG(chan));
+ outl(data[3], iobase + ADDI_TCW_RELOAD_REG);
/* Set the mode : */
/* - Disable the hardware */
ctrl &= 0xfffc19e2;
ctrl |= 0x80000 | (data[4] << 16);
- outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
+ outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
/* Enable or Disable Interrupt */
ctrl &= 0xfffff9fd;
ctrl |= (data[1] << 1);
- outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
+ outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
/* Set the Up/Down selection */
ctrl &= 0xfffbf9ff;
ctrl |= (data[6] << 18);
- outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
+ outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
return insn->n;
}
{
struct apci1564_private *devpriv = dev->private;
unsigned int chan = CR_CHAN(insn->chanspec);
+ unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
unsigned int ctrl;
- ctrl = inl(devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
+ ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
switch (data[1]) {
case 0: /* Stops the Counter subdevice */
ctrl = 0;
ctrl |= 0x400;
break;
}
- outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
+ outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
return insn->n;
}
{
struct apci1564_private *devpriv = dev->private;
unsigned int chan = CR_CHAN(insn->chanspec);
+ unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
unsigned int status;
/* Read the Counter Actual Value. */
- data[0] = inl(devpriv->counters + APCI1564_COUNTER_REG(chan));
+ data[0] = inl(iobase + ADDI_TCW_VAL_REG);
- status = inl(devpriv->counters + APCI1564_COUNTER_STATUS_REG(chan));
+ status = inl(iobase + ADDI_TCW_STATUS_REG);
data[1] = (status >> 1) & 1; /* software trigger status */
data[2] = (status >> 2) & 1; /* hardware trigger status */
data[3] = (status >> 3) & 1; /* software clear status */
*/
/*
- * devpriv->counters Register Map
+ * devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
* PLD Revision 2.x - PCI BAR 1 + 0x00
*/
-#define APCI1564_COUNTER_REG(x) (0x00 + ((x) * 0x20))
-#define APCI1564_COUNTER_RELOAD_REG(x) (0x04 + ((x) * 0x20))
-#define APCI1564_COUNTER_TIMEBASE_REG(x) (0x08 + ((x) * 0x20))
-#define APCI1564_COUNTER_CTRL_REG(x) (0x0c + ((x) * 0x20))
-#define APCI1564_COUNTER_STATUS_REG(x) (0x10 + ((x) * 0x20))
-#define APCI1564_COUNTER_IRQ_REG(x) (0x14 + ((x) * 0x20))
-#define APCI1564_COUNTER_WARN_TIMEVAL_REG(x) (0x18 + ((x) * 0x20))
-#define APCI1564_COUNTER_WARN_TIMEBASE_REG(x) (0x1c + ((x) * 0x20))
+#define APCI1564_COUNTER(x) ((x) * 0x20)
struct apci1564_private {
unsigned long eeprom; /* base address of EEPROM register */
outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
if (devpriv->counters) {
+ unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG;
+
/* Reset the counter registers */
- outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(0));
- outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(1));
- outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(2));
+ outl(0x0, iobase + APCI1564_COUNTER(0));
+ outl(0x0, iobase + APCI1564_COUNTER(1));
+ outl(0x0, iobase + APCI1564_COUNTER(2));
}
return 0;
if (devpriv->counters) {
for (chan = 0; chan < 4; chan++) {
- status = inl(devpriv->counters +
- APCI1564_COUNTER_IRQ_REG(chan));
+ unsigned long iobase;
+
+ iobase = devpriv->counters + APCI1564_COUNTER(chan);
+
+ status = inl(iobase + ADDI_TCW_IRQ_REG);
if (status & 0x01) {
/* Disable Counter Interrupt */
- ctrl = inl(devpriv->counters +
- APCI1564_COUNTER_CTRL_REG(chan));
- outl(0x0, devpriv->counters +
- APCI1564_COUNTER_CTRL_REG(chan));
+ ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
+ outl(0x0, iobase + ADDI_TCW_CTRL_REG);
/* Send a signal to from kernel to user space */
send_sig(SIGIO, devpriv->tsk_current, 0);
/* Enable Counter Interrupt */
- outl(ctrl, devpriv->counters +
- APCI1564_COUNTER_CTRL_REG(chan));
+ outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
}
}
}