drm/i915: Apply some ocd for IMR vs. IER order during irq enable

When disabling interrupts we do the writes in this order:
IMR,IER,IIR,IIR. But when enabling interrupts we don't do use the
mirrored order, and instead do IIR,IIR,IMR,IER.

I like consistency unless there's a good reason against it, which I
can't think of here, so change the enable order to IIR,IIR,IER,IMR.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a2b013d97fb6e7bc3483d056b185681164983842..98a8d650768b7294043b2c0f529f10300ffbfa64 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -126,16 +126,16 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
 
 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
        GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
-       I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
        I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
-       POSTING_READ(GEN8_##type##_IER(which)); \
+       I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
+       POSTING_READ(GEN8_##type##_IMR(which)); \
 } while (0)
 
 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
        GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
-       I915_WRITE(type##IMR, (imr_val)); \
        I915_WRITE(type##IER, (ier_val)); \
-       POSTING_READ(type##IER); \
+       I915_WRITE(type##IMR, (imr_val)); \
+       POSTING_READ(type##IMR); \
 } while (0)
 
 /* For display hotplug interrupt */