drm/gk208-/gr: stop touching 0x260 inappropriately
authorBen Skeggs <bskeggs@redhat.com>
Thu, 12 Jun 2014 12:15:21 +0000 (22:15 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Sat, 9 Aug 2014 19:11:07 +0000 (05:11 +1000)
As a side note.. It's a bit hard to figure out how to name this commit..
GK20A is NVEA, which is before NV108 (GK208).. Confusing.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
15 files changed:
drivers/gpu/drm/nouveau/Makefile
drivers/gpu/drm/nouveau/core/engine/device/gm100.c
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
drivers/gpu/drm/nouveau/core/include/subdev/mc.h
drivers/gpu/drm/nouveau/core/subdev/mc/base.c
drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h
drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c
drivers/gpu/drm/nouveau/core/subdev/mc/priv.h [new file with mode: 0644]

index b5b108115c74b3dd10380d2e8a2dfaf99b3c6273..b530d49ca92a44663d8322953cc564ebd31336db 100644 (file)
@@ -161,6 +161,7 @@ nouveau-y += core/subdev/mc/nv94.o
 nouveau-y += core/subdev/mc/nv98.o
 nouveau-y += core/subdev/mc/nvc0.o
 nouveau-y += core/subdev/mc/nvc3.o
+nouveau-y += core/subdev/mc/gk20a.o
 nouveau-y += core/subdev/mxm/base.o
 nouveau-y += core/subdev/mxm/mxms.o
 nouveau-y += core/subdev/mxm/nv50.o
index 829e7ae5218bd8004dd51ebc4ac009d8dd71f1f7..a2e8fb889ef11c46a37779307dca6e20c665233d 100644 (file)
@@ -68,7 +68,7 @@ gm100_identify(struct nouveau_device *device)
 #endif
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm107_devinit_oclass;
-               device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
+               device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
                device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
index d07eeca1c2d69ecc7dfa2150cddd3c4db88ed047..cc992d6e23380efa2333d4b187b6d0bdae61d2ea 100644 (file)
@@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device)
                break;
        case 0xea:
                device->cname = "GK20A";
-               device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
+               device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
                device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  gk20a_fb_oclass;
@@ -248,7 +248,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
                device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
-               device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
+               device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
                device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
                device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
index 833a96508c4e8fa96c6c3d2b3da0f16a8c1dd26c..6a2a288dc253a633dabdd3b545697b48c4592505 100644 (file)
@@ -1170,7 +1170,7 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 {
        struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 
-       nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
+       nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
 
        nvc0_graph_mmio(priv, oclass->hub);
        nvc0_graph_mmio(priv, oclass->gpc);
@@ -1192,7 +1192,7 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
        nvc0_graph_icmd(priv, oclass->icmd);
        nv_wr32(priv, 0x404154, 0x00000400);
        nvc0_graph_mthd(priv, oclass->mthd);
-       nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
+       nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 }
 
 int
index 1dbc8d7f2e86553b2450e3f901430a116d7024da..944d90bef9599b3da3f118469519e59f52e1f862 100644 (file)
@@ -223,7 +223,7 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
        struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
        int i;
 
-       nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
+       nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
 
        nvc0_graph_mmio(priv, oclass->hub);
        nvc0_graph_mmio(priv, oclass->gpc);
@@ -248,7 +248,7 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
        nvc0_graph_icmd(priv, oclass->icmd);
        nv_wr32(priv, 0x404154, 0x00000400);
        nvc0_graph_mthd(priv, oclass->mthd);
-       nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
+       nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 }
 
 struct nouveau_oclass *
index c5b24923858792fb69869c697e9c34f5431918dd..cd036322d2d8cfd4ce32a7ca4a38afbafa298663 100644 (file)
@@ -957,7 +957,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
        struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
        int i;
 
-       nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
+       nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
 
        nvc0_graph_mmio(priv, oclass->hub);
        nvc0_graph_mmio(priv, oclass->gpc);
@@ -991,7 +991,7 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
        nvc0_graph_icmd(priv, oclass->icmd);
        nv_wr32(priv, 0x404154, 0x00000400);
        nvc0_graph_mthd(priv, oclass->mthd);
-       nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
+       nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 
        nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
        nv_mask(priv, 0x41be10, 0x00800000, 0x00800000);
index aa08389163540819c769db5ebae8852e09419191..cda70fca9bc43bdbbc1716115d86174d07812086 100644 (file)
@@ -969,17 +969,16 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
 {
        struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass;
        struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
-       u32 r000260;
        int i;
 
        if (priv->firmware) {
                /* load fuc microcode */
-               r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
+               nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
                nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c,
                                                   &priv->fuc409d);
                nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac,
                                                   &priv->fuc41ad);
-               nv_wr32(priv, 0x000260, r000260);
+               nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 
                /* start both of them running */
                nv_wr32(priv, 0x409840, 0xffffffff);
@@ -1066,7 +1065,7 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
        }
 
        /* load HUB microcode */
-       r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
+       nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
        nv_wr32(priv, 0x4091c0, 0x01000000);
        for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
                nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]);
@@ -1089,7 +1088,7 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
                        nv_wr32(priv, 0x41a188, i >> 6);
                nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]);
        }
-       nv_wr32(priv, 0x000260, r000260);
+       nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 
        /* load register lists */
        nvc0_graph_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
index 65d6f7be0e35c598fb44fb9c3f29e3f5fdc4edb3..a599b4fb5dd79d33d01bd0baca42f45c0ade4462 100644 (file)
@@ -34,6 +34,7 @@
 #include <subdev/vm.h>
 #include <subdev/bar.h>
 #include <subdev/timer.h>
+#include <subdev/mc.h>
 
 #include <engine/fifo.h>
 #include <engine/graph.h>
index 72b176831be62ca009041d82155e21b6d9d9d1f8..568e4dfc5e9ebc5701ac1c040992ea559f49bc87 100644 (file)
@@ -4,15 +4,11 @@
 #include <core/subdev.h>
 #include <core/device.h>
 
-struct nouveau_mc_intr {
-       u32 stat;
-       u32 unit;
-};
-
 struct nouveau_mc {
        struct nouveau_subdev base;
        bool use_msi;
        unsigned int irq;
+       void (*unk260)(struct nouveau_mc *, u32);
 };
 
 static inline struct nouveau_mc *
@@ -21,30 +17,6 @@ nouveau_mc(void *obj)
        return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MC];
 }
 
-#define nouveau_mc_create(p,e,o,d)                                             \
-       nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nouveau_mc_destroy(p) ({                                               \
-       struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc));        \
-})
-#define nouveau_mc_init(p) ({                                                  \
-       struct nouveau_mc *pmc = (p); _nouveau_mc_init(nv_object(pmc));        \
-})
-#define nouveau_mc_fini(p,s) ({                                                \
-       struct nouveau_mc *pmc = (p); _nouveau_mc_fini(nv_object(pmc), (s));   \
-})
-
-int  nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *,
-                       struct nouveau_oclass *, int, void **);
-void _nouveau_mc_dtor(struct nouveau_object *);
-int  _nouveau_mc_init(struct nouveau_object *);
-int  _nouveau_mc_fini(struct nouveau_object *, bool);
-
-struct nouveau_mc_oclass {
-       struct nouveau_oclass base;
-       const struct nouveau_mc_intr *intr;
-       void (*msi_rearm)(struct nouveau_mc *);
-};
-
 extern struct nouveau_oclass *nv04_mc_oclass;
 extern struct nouveau_oclass *nv40_mc_oclass;
 extern struct nouveau_oclass *nv44_mc_oclass;
@@ -54,5 +26,6 @@ extern struct nouveau_oclass *nv94_mc_oclass;
 extern struct nouveau_oclass *nv98_mc_oclass;
 extern struct nouveau_oclass *nvc0_mc_oclass;
 extern struct nouveau_oclass *nvc3_mc_oclass;
+extern struct nouveau_oclass *gk20a_mc_oclass;
 
 #endif
index 8a5555192fa5ea503d97aa11efc84ed6968c7e6d..ca7cee3a314ad6ab4b3f055358c7fbee9c9aae82 100644 (file)
  * Authors: Ben Skeggs
  */
 
-#include <subdev/mc.h>
+#include "priv.h"
 #include <core/option.h>
 
+static inline void
+nouveau_mc_unk260(struct nouveau_mc *pmc, u32 data)
+{
+       const struct nouveau_mc_oclass *impl = (void *)nv_oclass(pmc);
+       if (impl->unk260)
+               impl->unk260(pmc, data);
+}
+
 static inline u32
 nouveau_mc_intr_mask(struct nouveau_mc *pmc)
 {
@@ -114,6 +122,8 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
        if (ret)
                return ret;
 
+       pmc->unk260 = nouveau_mc_unk260;
+
        if (nv_device_is_pci(device))
                switch (device->pdev->device & 0x0ff0) {
                case 0x00f0:
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c
new file mode 100644 (file)
index 0000000..b8d6cb4
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "nv04.h"
+
+struct nouveau_oclass *
+gk20a_mc_oclass = &(struct nouveau_mc_oclass) {
+       .base.handle = NV_SUBDEV(MC, 0xea),
+       .base.ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = nv04_mc_ctor,
+               .dtor = _nouveau_mc_dtor,
+               .init = nv50_mc_init,
+               .fini = _nouveau_mc_fini,
+       },
+       .intr = nvc0_mc_intr,
+       .msi_rearm = nv40_mc_msi_rearm,
+}.base;
index 81a408e7d034636f6b940107839394b9a03b0cab..4d9ea46c47c24e27ef4aa38c488a8b49e7462b04 100644 (file)
@@ -1,7 +1,7 @@
 #ifndef __NVKM_MC_NV04_H__
 #define __NVKM_MC_NV04_H__
 
-#include <subdev/mc.h>
+#include "priv.h"
 
 struct nv04_mc_priv {
        struct nouveau_mc base;
index f9c6a678b47d81b1509215fe14d7f34c7398ca20..2b4af9610ee9775ec7437a806d99f476182384f4 100644 (file)
@@ -56,6 +56,12 @@ nvc0_mc_msi_rearm(struct nouveau_mc *pmc)
        nv_wr32(priv, 0x088704, 0x00000000);
 }
 
+void
+nvc0_mc_unk260(struct nouveau_mc *pmc, u32 data)
+{
+       nv_wr32(pmc, 0x000260, data);
+}
+
 struct nouveau_oclass *
 nvc0_mc_oclass = &(struct nouveau_mc_oclass) {
        .base.handle = NV_SUBDEV(MC, 0xc0),
@@ -67,4 +73,5 @@ nvc0_mc_oclass = &(struct nouveau_mc_oclass) {
        },
        .intr = nvc0_mc_intr,
        .msi_rearm = nvc0_mc_msi_rearm,
+       .unk260 = nvc0_mc_unk260,
 }.base;
index 837e545aeb9fabae87c33586d3ea443e3dfc9916..68b5f61aadb5fc60a0d9f594548bec1a1b677f6f 100644 (file)
@@ -35,4 +35,5 @@ nvc3_mc_oclass = &(struct nouveau_mc_oclass) {
        },
        .intr = nvc0_mc_intr,
        .msi_rearm = nv40_mc_msi_rearm,
+       .unk260 = nvc0_mc_unk260,
 }.base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h
new file mode 100644 (file)
index 0000000..911e663
--- /dev/null
@@ -0,0 +1,38 @@
+#ifndef __NVKM_MC_PRIV_H__
+#define __NVKM_MC_PRIV_H__
+
+#include <subdev/mc.h>
+
+#define nouveau_mc_create(p,e,o,d)                                             \
+       nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
+#define nouveau_mc_destroy(p) ({                                               \
+       struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc));        \
+})
+#define nouveau_mc_init(p) ({                                                  \
+       struct nouveau_mc *pmc = (p); _nouveau_mc_init(nv_object(pmc));        \
+})
+#define nouveau_mc_fini(p,s) ({                                                \
+       struct nouveau_mc *pmc = (p); _nouveau_mc_fini(nv_object(pmc), (s));   \
+})
+
+int  nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *,
+                       struct nouveau_oclass *, int, void **);
+void _nouveau_mc_dtor(struct nouveau_object *);
+int  _nouveau_mc_init(struct nouveau_object *);
+int  _nouveau_mc_fini(struct nouveau_object *, bool);
+
+struct nouveau_mc_intr {
+       u32 stat;
+       u32 unit;
+};
+
+struct nouveau_mc_oclass {
+       struct nouveau_oclass base;
+       const struct nouveau_mc_intr *intr;
+       void (*msi_rearm)(struct nouveau_mc *);
+       void (*unk260)(struct nouveau_mc *, u32);
+};
+
+void nvc0_mc_unk260(struct nouveau_mc *, u32);
+
+#endif