EMAC driver: define MDC_CLK=2.5MHz and caculate mdc_div according to SCLK.

Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index 4006a5dea654d43dda723e31692ed9cb85e2c056..ee398196ea80ce7867d7b4d289b9bda2cfcb793e 100644 (file)
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -412,20 +412,26 @@ static void bf537_adjust_link(struct net_device *dev)
        spin_unlock_irqrestore(&lp->lock, flags);
 }
 
+/* MDC  = 2.5 MHz */
+#define MDC_CLK 2500000
+
 static int mii_probe(struct net_device *dev)
 {
        struct bf537mac_local *lp = netdev_priv(dev);
        struct phy_device *phydev = NULL;
        unsigned short sysctl;
        int i;
+       u32 sclk, mdc_div;
 
        /* Enable PHY output early */
        if (!(bfin_read_VR_CTL() & PHYCLKOE))
                bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE);
 
-       /* MDC  = 2.5 MHz */
+       sclk = get_sclk();
+       mdc_div = ((sclk / MDC_CLK) / 2) - 1;
+
        sysctl = bfin_read_EMAC_SYSCTL();
-       sysctl |= SET_MDCDIV(24);
+       sysctl |= SET_MDCDIV(mdc_div);
        bfin_write_EMAC_SYSCTL(sysctl);
 
        /* search for connect PHY device */
@@ -477,8 +483,10 @@ static int mii_probe(struct net_device *dev)
        lp->phydev = phydev;
 
        printk(KERN_INFO "%s: attached PHY driver [%s] "
-              "(mii_bus:phy_addr=%s, irq=%d)\n",
-              DRV_NAME, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
+              "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
+              "@sclk=%dMHz)\n",
+              DRV_NAME, phydev->drv->name, phydev->dev.bus_id, phydev->irq,
+              MDC_CLK, mdc_div, sclk/1000000);
 
        return 0;
 }