drm/i915: Use intel_gpu_freq() and intel_freq_opcode()

Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.

Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)

@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)

@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
-  E2 = intel_gpu_freq(E3, E4);
- } else {
-  E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
-  E2 = intel_freq_opcode(E3, E4);
- } else {
-  E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)

One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.

Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2ad4c48c8cb7e7deab1fce853c996371ea159655..b315f01966360e1a6f10ef584bb053367e6bbbbd 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1113,7 +1113,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
                        reqf >>= 24;
                else
                        reqf >>= 25;
-               reqf *= GT_FREQUENCY_MULTIPLIER;
+               reqf = intel_gpu_freq(dev_priv, reqf);
 
                rpmodectl = I915_READ(GEN6_RP_CONTROL);
                rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
@@ -1130,7 +1130,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
                        cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
                else
                        cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
-               cagf *= GT_FREQUENCY_MULTIPLIER;
+               cagf = intel_gpu_freq(dev_priv, cagf);
 
                intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
                mutex_unlock(&dev->struct_mutex);
@@ -1178,18 +1178,18 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 
                max_freq = (rp_state_cap & 0xff0000) >> 16;
                seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
-                          max_freq * GT_FREQUENCY_MULTIPLIER);
+                          intel_gpu_freq(dev_priv, max_freq));
 
                max_freq = (rp_state_cap & 0xff00) >> 8;
                seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
-                          max_freq * GT_FREQUENCY_MULTIPLIER);
+                          intel_gpu_freq(dev_priv, max_freq));
 
                max_freq = rp_state_cap & 0xff;
                seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
-                          max_freq * GT_FREQUENCY_MULTIPLIER);
+                          intel_gpu_freq(dev_priv, max_freq));
 
                seq_printf(m, "Max overclocked frequency: %dMHz\n",
-                          dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
+                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
        } else if (IS_VALLEYVIEW(dev)) {
                u32 freq_sts;
 
@@ -1199,16 +1199,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
                seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
 
                seq_printf(m, "max GPU freq: %d MHz\n",
-                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
 
                seq_printf(m, "min GPU freq: %d MHz\n",
-                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
 
-               seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
-                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
+               seq_printf(m,
+                          "efficient (RPe) frequency: %d MHz\n",
+                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
 
                seq_printf(m, "current GPU freq: %d MHz\n",
-                          vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
+                          intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
                mutex_unlock(&dev_priv->rps.hw_lock);
        } else {
                seq_puts(m, "no P-state info available\n");
@@ -1677,7 +1678,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
                                       GEN6_PCODE_READ_MIN_FREQ_TABLE,
                                       &ia_freq);
                seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
-                          gpu_freq * GT_FREQUENCY_MULTIPLIER,
+                          intel_gpu_freq(dev_priv, gpu_freq),
                           ((ia_freq >> 0) & 0xff) * 100,
                           ((ia_freq >> 8) & 0xff) * 100);
        }
@@ -4119,10 +4120,7 @@ i915_max_freq_get(void *data, u64 *val)
        if (ret)
                return ret;
 
-       if (IS_VALLEYVIEW(dev))
-               *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
-       else
-               *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
+       *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
        mutex_unlock(&dev_priv->rps.hw_lock);
 
        return 0;
@@ -4151,12 +4149,12 @@ i915_max_freq_set(void *data, u64 val)
         * Turbo will still be enabled, but won't go above the set value.
         */
        if (IS_VALLEYVIEW(dev)) {
-               val = vlv_freq_opcode(dev_priv, val);
+               val = intel_freq_opcode(dev_priv, val);
 
                hw_max = dev_priv->rps.max_freq;
                hw_min = dev_priv->rps.min_freq;
        } else {
-               do_div(val, GT_FREQUENCY_MULTIPLIER);
+               val = intel_freq_opcode(dev_priv, val);
 
                rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
                hw_max = dev_priv->rps.max_freq;
@@ -4200,10 +4198,7 @@ i915_min_freq_get(void *data, u64 *val)
        if (ret)
                return ret;
 
-       if (IS_VALLEYVIEW(dev))
-               *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
-       else
-               *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
+       *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
        mutex_unlock(&dev_priv->rps.hw_lock);
 
        return 0;
@@ -4232,12 +4227,12 @@ i915_min_freq_set(void *data, u64 val)
         * Turbo will still be enabled, but won't go below the set value.
         */
        if (IS_VALLEYVIEW(dev)) {
-               val = vlv_freq_opcode(dev_priv, val);
+               val = intel_freq_opcode(dev_priv, val);
 
                hw_max = dev_priv->rps.max_freq;
                hw_min = dev_priv->rps.min_freq;
        } else {
-               do_div(val, GT_FREQUENCY_MULTIPLIER);
+               val = intel_freq_opcode(dev_priv, val);
 
                rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
                hw_max = dev_priv->rps.max_freq;

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5f36c6c81cedb7b33f6f44827f56a597e91c5dd3..3e81d9aaa50a0baf48c3cc8fbb7566a55b45b871 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3236,8 +3236,6 @@ void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
-int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
-int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
 
 #define I915_READ8(reg)                dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
 #define I915_WRITE8(reg, val)  dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 532ad3477997c279bdd2e12346e6d3026ece53f7..49f5ade0edb70ba4fab2cb227bb1c78fabcd94a8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -297,14 +297,14 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
        if (IS_VALLEYVIEW(dev_priv->dev)) {
                u32 freq;
                freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-               ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
+               ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
        } else {
                u32 rpstat = I915_READ(GEN6_RPSTAT1);
                if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                        ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
                else
                        ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
-               ret *= GT_FREQUENCY_MULTIPLIER;
+               ret = intel_gpu_freq(dev_priv, ret);
        }
        mutex_unlock(&dev_priv->rps.hw_lock);
 
@@ -326,11 +326,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
        intel_runtime_pm_get(dev_priv);
 
        mutex_lock(&dev_priv->rps.hw_lock);
-       if (IS_VALLEYVIEW(dev_priv->dev)) {
-               ret = vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
-       } else {
-               ret = dev_priv->rps.cur_freq * GT_FREQUENCY_MULTIPLIER;
-       }
+       ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
        mutex_unlock(&dev_priv->rps.hw_lock);
 
        intel_runtime_pm_put(dev_priv);
@@ -345,8 +341,9 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
        struct drm_device *dev = minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
 
-       return snprintf(buf, PAGE_SIZE, "%d\n",
-                       vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
+       return snprintf(buf, PAGE_SIZE,
+                       "%d\n",
+                       intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
 }
 
 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
@@ -359,10 +356,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
        flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 
        mutex_lock(&dev_priv->rps.hw_lock);
-       if (IS_VALLEYVIEW(dev_priv->dev))
-               ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
-       else
-               ret = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
+       ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
        mutex_unlock(&dev_priv->rps.hw_lock);
 
        return snprintf(buf, PAGE_SIZE, "%d\n", ret);
@@ -386,10 +380,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
        mutex_lock(&dev_priv->rps.hw_lock);
 
-       if (IS_VALLEYVIEW(dev_priv->dev))
-               val = vlv_freq_opcode(dev_priv, val);
-       else
-               val /= GT_FREQUENCY_MULTIPLIER;
+       val = intel_freq_opcode(dev_priv, val);
 
        if (val < dev_priv->rps.min_freq ||
            val > dev_priv->rps.max_freq ||
@@ -400,7 +391,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
        if (val > dev_priv->rps.rp0_freq)
                DRM_DEBUG("User requested overclocking to %d\n",
-                         val * GT_FREQUENCY_MULTIPLIER);
+                         intel_gpu_freq(dev_priv, val));
 
        dev_priv->rps.max_freq_softlimit = val;
 
@@ -431,10 +422,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
        flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 
        mutex_lock(&dev_priv->rps.hw_lock);
-       if (IS_VALLEYVIEW(dev_priv->dev))
-               ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
-       else
-               ret = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
+       ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
        mutex_unlock(&dev_priv->rps.hw_lock);
 
        return snprintf(buf, PAGE_SIZE, "%d\n", ret);
@@ -458,10 +446,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
        mutex_lock(&dev_priv->rps.hw_lock);
 
-       if (IS_VALLEYVIEW(dev))
-               val = vlv_freq_opcode(dev_priv, val);
-       else
-               val /= GT_FREQUENCY_MULTIPLIER;
+       val = intel_freq_opcode(dev_priv, val);
 
        if (val < dev_priv->rps.min_freq ||
            val > dev_priv->rps.max_freq ||
@@ -521,19 +506,22 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
 
        if (attr == &dev_attr_gt_RP0_freq_mhz) {
                if (IS_VALLEYVIEW(dev))
-                       val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
+                       val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
                else
-                       val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
+                       val = intel_gpu_freq(dev_priv,
+                                            ((rp_state_cap & 0x0000ff) >> 0));
        } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
                if (IS_VALLEYVIEW(dev))
-                       val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
+                       val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
                else
-                       val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
+                       val = intel_gpu_freq(dev_priv,
+                                            ((rp_state_cap & 0x00ff00) >> 8));
        } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
                if (IS_VALLEYVIEW(dev))
-                       val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq);
+                       val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
                else
-                       val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
+                       val = intel_gpu_freq(dev_priv,
+                                            ((rp_state_cap & 0xff0000) >> 16));
        } else {
                BUG();
        }

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bc243a2840c47d8d41f58ba55170fbae8b1b8da6..dbeecb03c9e11c0d60e0cc63fe0c5375e169d8b2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3883,7 +3883,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 
        dev_priv->rps.cur_freq = val;
-       trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
+       trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
 }
 
 static void gen9_disable_rps(struct drm_device *dev)
@@ -4619,22 +4619,22 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
        dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
        dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
        DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
                         dev_priv->rps.max_freq);
 
        dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
        DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
                         dev_priv->rps.efficient_freq);
 
        dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
        DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
                         dev_priv->rps.rp1_freq);
 
        dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
        DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
                         dev_priv->rps.min_freq);
 
        /* Preserve min/max settings in case of re-init */
@@ -4688,22 +4688,22 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
        dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
        dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
        DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
                         dev_priv->rps.max_freq);
 
        dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
        DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
                         dev_priv->rps.efficient_freq);
 
        dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
        DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
                         dev_priv->rps.rp1_freq);
 
        dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
        DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
                         dev_priv->rps.min_freq);
 
        WARN_ONCE((dev_priv->rps.max_freq |
@@ -4807,11 +4807,11 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
        dev_priv->rps.cur_freq = (val >> 8) & 0xff;
        DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
                         dev_priv->rps.cur_freq);
 
        DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
                         dev_priv->rps.efficient_freq);
 
        valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
@@ -4891,11 +4891,11 @@ static void valleyview_enable_rps(struct drm_device *dev)
 
        dev_priv->rps.cur_freq = (val >> 8) & 0xff;
        DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
                         dev_priv->rps.cur_freq);
 
        DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
-                        vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+                        intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
                         dev_priv->rps.efficient_freq);
 
        valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
@@ -6625,11 +6625,6 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
                return val * GT_FREQUENCY_MULTIPLIER;
 }
 
-int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
-{
-       return intel_gpu_freq(dev_priv, val);
-}
-
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
        if (IS_CHERRYVIEW(dev_priv->dev))
@@ -6640,11 +6635,6 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
                return val / GT_FREQUENCY_MULTIPLIER;
 }
 
-int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
-{
-       return intel_freq_opcode(dev_priv, val);
-}
-
 void intel_pm_setup(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;