dev->drm_fw_buf.daddr, 0, 0);
if (ret != DRMDRV_OK) {
mfc_err_ctx("failed MFC DRM F/W prot(%#x)\n", ret);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
dev->fw.drm_status = 0;
} else {
dev->fw.drm_status = 1;
/* Request buffer unprotection for DRM F/W */
smc_ret = exynos_smc(SMC_DRM_PPMP_MFCFW_UNPROT,
dev->drm_fw_buf.daddr, 0, 0);
- if (smc_ret != DRMDRV_OK)
+ if (smc_ret != DRMDRV_OK) {
mfc_err_ctx("failed MFC DRM F/W unprot(%#x)\n", smc_ret);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
+ }
}
#endif
dev->drm_fw_buf.daddr, 0, 0);
if (ret != DRMDRV_OK) {
mfc_err_ctx("failed MFC DRM F/W unprot(%#x)\n", ret);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_release;
}
}
return 0;
}
+static inline int is_err_condition(unsigned int err)
+{
+ if (err == S5P_FIMV_ERR_NO_AVAILABLE_DPB ||
+ err == S5P_FIMV_ERR_INSUFFICIENT_DPB_SIZE ||
+ err == S5P_FIMV_ERR_INSUFFICIENT_NUM_DPB ||
+ err == S5P_FIMV_ERR_INSUFFICIENT_MV_BUF_SIZE ||
+ err == S5P_FIMV_ERR_INSUFFICIENT_SCRATCH_BUF_SIZE)
+ return 1;
+
+ return 0;
+}
+
irqreturn_t s5p_mfc_top_half_irq(int irq, void *priv)
{
struct s5p_mfc_dev *dev = priv;
if (s5p_mfc_pm_get_pwr_ref_cnt(dev) == 0) {
mfc_err_dev("no mfc power on\n");
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto irq_end;
}
(err && (reason != S5P_FIMV_R2H_CMD_ERR_RET)))
call_dop(dev, dump_regs, dev);
+ if (is_err_condition(err))
+ call_dop(dev, dump_and_stop_debug_mode, dev);
+
#ifdef NAL_Q_ENABLE
if (dev->nal_q_handle) {
ret = mfc_nal_q_irq(dev, reason, err);
if (IS_ERR(special_buf->dma_buf)) {
mfc_err_ctx("Failed to allocate buffer (err %ld)\n",
PTR_ERR(special_buf->dma_buf));
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_ion_alloc;
}
if (IS_ERR(special_buf->attachment)) {
mfc_err_ctx("Failed to get dma_buf_attach (err %ld)\n",
PTR_ERR(special_buf->attachment));
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_attach;
}
if (IS_ERR(special_buf->sgt)) {
mfc_err_ctx("Failed to get sgt (err %ld)\n",
PTR_ERR(special_buf->sgt));
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_map;
}
if (IS_ERR_VALUE(special_buf->daddr)) {
mfc_err_ctx("Failed to allocate iova (err 0x%p)\n",
&special_buf->daddr);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_iovmm;
}
if (IS_ERR(special_buf->vaddr)) {
mfc_err_ctx("Failed to get vaddr (err 0x%p)\n",
&special_buf->vaddr);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_vaddr;
}
if (IS_ERR(mfc_buf->dmabufs[i][plane])) {
mfc_err_ctx("Failed to get dma_buf (err %ld)",
PTR_ERR(mfc_buf->dmabufs[i][plane]));
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_get_daddr;
}
if (IS_ERR(mfc_buf->attachments[i][plane])) {
mfc_err_ctx("Failed to get dma_buf_attach (err %ld)",
PTR_ERR(mfc_buf->attachments[i][plane]));
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_get_daddr;
}
if (IS_ERR_VALUE(mfc_buf->addr[i][plane])) {
mfc_err_ctx("Failed to allocate iova (err %pa)",
&mfc_buf->addr[i][plane]);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_get_daddr;
}
ret = clk_enable(dev->pm.clock);
if (ret < 0) {
mfc_err_dev("clk_enable failed (%d)\n", ret);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
return ret;
}
dev->pm.clock_on_steps |= 0x1 << 1;
dev->pm.clock_on_steps |= 0x1 << 3;
if (ret != DRMDRV_OK) {
mfc_err_dev("Protection Enable failed! ret(%u)\n", ret);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
spin_unlock_irqrestore(&dev->pm.clklock, flags);
clk_disable(dev->pm.clock);
return -EACCES;
dev->id, SMC_PROTECTION_DISABLE);
if (ret != DRMDRV_OK) {
mfc_err_dev("Protection Disable failed! ret(%u)\n", ret);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
spin_unlock_irqrestore(&dev->pm.clklock, flags);
clk_disable(dev->pm.clock);
return;
ret = pm_runtime_get_sync(dev->pm.device);
if (ret < 0) {
mfc_err_dev("Failed to get power: ret(%d)\n", ret);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
goto err_power_on;
}
ret = pm_runtime_put_sync(dev->pm.device);
if (ret < 0) {
mfc_err_dev("Failed to put power: ret(%d)\n", ret);
+ call_dop(dev, dump_and_stop_debug_mode, dev);
return ret;
}
#define S5P_FIMV_WARN_STATUS_MASK 0xFFFF
#define S5P_FIMV_WARN_STATUS_SHIFT 16
/* Error number */
+#define S5P_FIMV_ERR_NO_AVAILABLE_DPB 33
#define S5P_FIMV_ERR_NO_KEY_FRAME 34
#define S5P_FIMV_ERR_VPS_ONLY_ERROR 42
+#define S5P_FIMV_ERR_INSUFFICIENT_DPB_SIZE 57
+#define S5P_FIMV_ERR_INSUFFICIENT_NUM_DPB 58
+#define S5P_FIMV_ERR_INSUFFICIENT_MV_BUF_SIZE 60
#define S5P_FIMV_ERR_NULL_SCRATCH 61
+#define S5P_FIMV_ERR_INSUFFICIENT_SCRATCH_BUF_SIZE 62
#define S5P_FIMV_ERR_UNSUPPORTED_FEATURE 100
#define S5P_FIMV_ERR_UNSUPPORTED_RESOLUTION 101