/*
* intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
*
- * (C) Copyright 2008-2010 Intel Corporation
+ * (C) Copyright 2008-2010,2015 Intel Corporation
* Author: Sreedhara DS (sreedhara.ds@intel.com)
*
* This program is free software; you can redistribute it and/or
#define PCI_DEVICE_ID_CLOVERVIEW 0x08ea
#define PCI_DEVICE_ID_TANGIER 0x11a0
-/* intel scu ipc driver data*/
+/* intel scu ipc driver data */
struct intel_scu_ipc_pdata_t {
u32 ipc_base;
u32 i2c_base;
static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
-static int platform; /* Platform type */
-
/*
* IPC Read Buffer (Read Only):
* 16 byte buffer for receiving data from SCU, if IPC command
* Format:
* |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
*/
-
static inline u8 ipc_read_status(void)
{
return __raw_readl(ipcdev.ipc_base + 0x04);
return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
}
-static inline int busy_loop(void) /* Wait till scu status is busy */
+/* Wait till scu status is busy */
+static inline int busy_loop(void)
{
u32 status = 0;
u32 loop_count = 0;
return 0;
}
-int intel_scu_ipc_check_status(void)
+static int intel_scu_ipc_check_status(void)
{
return ipcdev.irq_mode ? ipc_wait_for_interrupt() : busy_loop();
}
if (id == IPC_CMD_PCNTRL_R) {
for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
ipc_data_writel(wbuf[nc], offset);
- ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
+ ipc_command((count * 2) << 16 | id << 12 | 0 << 8 | op);
} else if (id == IPC_CMD_PCNTRL_W) {
for (nc = 0; nc < count; nc++, offset += 1)
cbuf[offset] = data[nc];
for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
ipc_data_writel(wbuf[nc], offset);
- ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
+ ipc_command((count * 3) << 16 | id << 12 | 0 << 8 | op);
} else if (id == IPC_CMD_PCNTRL_M) {
cbuf[offset] = data[0];
cbuf[offset + 1] = data[1];
ipc_data_writel(wbuf[0], 0); /* Write wbuff */
- ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
+ ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
}
err = intel_scu_ipc_check_status();
*/
int intel_scu_ipc_ioread16(u16 addr, u16 *data)
{
- u16 x[2] = {addr, addr + 1 };
+ u16 x[2] = {addr, addr + 1};
return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
}
EXPORT_SYMBOL(intel_scu_ipc_ioread16);
*/
int intel_scu_ipc_iowrite16(u16 addr, u16 data)
{
- u16 x[2] = {addr, addr + 1 };
+ u16 x[2] = {addr, addr + 1};
return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
}
EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
}
EXPORT_SYMBOL(intel_scu_ipc_writev);
-
/**
* intel_scu_ipc_update_register - r/m/w a register
* @addr: register address
* Issue a command to the SCU which involves data transfers. Do the
* data copies under the lock but leave it for the caller to interpret
*/
-
int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
- u32 *out, int outlen)
+ u32 *out, int outlen)
{
int i, err;
}
EXPORT_SYMBOL(intel_scu_ipc_command);
-/*I2C commands */
+/* I2C commands */
#define IPC_I2C_WRITE 1 /* I2C Write command */
#define IPC_I2C_READ 2 /* I2C Read command */
.remove = ipc_remove,
};
-
static int __init intel_scu_ipc_init(void)
{
+ int platform; /* Platform type */
+
platform = intel_mid_identify_cpu();
if (platform == 0)
return -ENODEV;