--- /dev/null
+#if defined(__UFS_CAL_U_BOOT__)
+#include <linux/types.h>
+#include <ufs-cal-9610.h>
+#elif defined(__UFS_CAL_FW__)
+#include <types.h>
+#include <include/ufs-cal.h>
+#else
+#include <linux/types.h>
+#include "ufs-cal-9610.h"
+#endif
+
+#ifndef _UFS_CAL_
+#define _UFS_CAL_
+
+/* UFSHCI */
+#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
+ ((sel) & 0xFFFF))
+#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
+
+/* Unipro.h */
+#define IS_PWR_MODE_HS(m) (((m) == FAST_MODE) || ((m) == FASTAUTO_MODE))
+#define IS_PWR_MODE_PWM(m) (((m) == SLOW_MODE) || ((m) == SLOWAUTO_MODE))
+
+enum {
+ PA_HS_MODE_A = 1,
+ PA_HS_MODE_B = 2,
+};
+
+enum {
+ FAST_MODE = 1,
+ SLOW_MODE = 2,
+ FASTAUTO_MODE = 4,
+ SLOWAUTO_MODE = 5,
+ UNCHANGED = 7,
+};
+
+/* User defined */
+#define UNIPRO_MCLK_PERIOD(p) (1000000000L / p->mclk_rate)
+
+#define PHY_PMA_COMN_ADDR(reg) (reg)
+#define PHY_PMA_TRSV_ADDR(reg, lane) ((reg) + (0x140 * (lane)))
+
+#define NUM_OF_UFS_HOST 1
+
+enum {
+ PHY_CFG_NONE = 0,
+ PHY_PCS_COMN,
+ PHY_PCS_RXTX,
+ PHY_PMA_COMN,
+ PHY_PMA_TRSV,
+ PHY_PLL_WAIT,
+ PHY_CDR_WAIT,
+ UNIPRO_STD_MIB,
+ UNIPRO_DBG_MIB,
+ UNIPRO_DBG_APB,
+
+ /* Since exynos8895 */
+ PHY_PCS_RX,
+ PHY_PCS_TX,
+ PHY_PCS_RX_PRD,
+ PHY_PCS_TX_PRD,
+ UNIPRO_DBG_PRD,
+ PHY_PMA_TRSV_LANE1_SQ_OFF,
+ COMMON_WAIT,
+};
+
+enum {
+ TX_LANE_0 = 0,
+ TX_LANE_1 = 1,
+ TX_LANE_2 = 2,
+ TX_LANE_3 = 3,
+ RX_LANE_0 = 4,
+ RX_LANE_1 = 5,
+ RX_LANE_2 = 6,
+ RX_LANE_3 = 7,
+};
+
+enum {
+ __PMD_PWM_G1_L1,
+ __PMD_PWM_G1_L2,
+ __PMD_PWM_G2_L1,
+ __PMD_PWM_G2_L2,
+ __PMD_PWM_G3_L1,
+ __PMD_PWM_G3_L2,
+ __PMD_PWM_G4_L1,
+ __PMD_PWM_G4_L2,
+ __PMD_PWM_G5_L1,
+ __PMD_PWM_G5_L2,
+ __PMD_HS_G1_L1,
+ __PMD_HS_G1_L2,
+ __PMD_HS_G2_L1,
+ __PMD_HS_G2_L2,
+ __PMD_HS_G3_L1,
+ __PMD_HS_G3_L2,
+};
+
+#define PMD_PWM_G1_L1 (1U << __PMD_PWM_G1_L1)
+#define PMD_PWM_G1_L2 (1U << __PMD_PWM_G1_L2)
+#define PMD_PWM_G2_L1 (1U << __PMD_PWM_G2_L1)
+#define PMD_PWM_G2_L2 (1U << __PMD_PWM_G2_L2)
+#define PMD_PWM_G3_L1 (1U << __PMD_PWM_G3_L1)
+#define PMD_PWM_G3_L2 (1U << __PMD_PWM_G3_L2)
+#define PMD_PWM_G4_L1 (1U << __PMD_PWM_G4_L1)
+#define PMD_PWM_G4_L2 (1U << __PMD_PWM_G4_L2)
+#define PMD_PWM_G5_L1 (1U << __PMD_PWM_G5_L1)
+#define PMD_PWM_G5_L2 (1U << __PMD_PWM_G5_L2)
+#define PMD_HS_G1_L1 (1U << __PMD_HS_G1_L1)
+#define PMD_HS_G1_L2 (1U << __PMD_HS_G1_L2)
+#define PMD_HS_G2_L1 (1U << __PMD_HS_G2_L1)
+#define PMD_HS_G2_L2 (1U << __PMD_HS_G2_L2)
+#define PMD_HS_G3_L1 (1U << __PMD_HS_G3_L1)
+#define PMD_HS_G3_L2 (1U << __PMD_HS_G3_L2)
+
+#define PMD_ALL (PMD_HS_G3_L2 - 1)
+#define PMD_PWM (PMD_PWM_G4_L2 - 1)
+#define PMD_HS (PMD_ALL ^ PMD_PWM)
+
+struct ufs_cal_phy_cfg {
+ u32 addr;
+ u32 val;
+ u32 flg;
+ u32 lyr;
+ u8 board;
+};
+
+#define for_each_phy_cfg(cfg) \
+ for (; (cfg)->flg != PHY_CFG_NONE; (cfg)++)
+
+#endif /*_UFS_CAL_ */
+
+static struct ufs_cal_param *ufs_cal[NUM_OF_UFS_HOST];
+static unsigned long ufs_cal_lock_timeout = 0xFFFFFFFF;
+
+static const struct ufs_cal_phy_cfg init_cfg[] = {
+ {0x9514, 0x00, PMD_ALL, UNIPRO_DBG_PRD, 0},
+
+ {0x200, 0x40, PMD_ALL, PHY_PCS_COMN, 0},
+ {0x12, 0x00, PMD_ALL, PHY_PCS_RX_PRD, 0},
+ {0xAA, 0x00, PMD_ALL, PHY_PCS_TX_PRD, 0},
+ {0x5C, 0x38, PMD_ALL, PHY_PCS_RX, 0},
+ {0x0F, 0x0, PMD_ALL, PHY_PCS_RX, 0},
+ {0x65, 0x01, PMD_ALL, PHY_PCS_RX, 0},
+ {0x69, 0x1, PMD_ALL, PHY_PCS_RX, 0},
+ {0x21, 0x0, PMD_ALL, PHY_PCS_RX, 0},
+ {0x22, 0x0, PMD_ALL, PHY_PCS_RX, 0},
+ {0x84, 0x1, PMD_ALL, PHY_PCS_RX, 0},
+ {0x04, 0x1, PMD_ALL, PHY_PCS_TX, 0},
+ {0x8F, 0x3E, PMD_ALL, PHY_PCS_TX, 0},
+ {0x200, 0x0, PMD_ALL, PHY_PCS_COMN, 0},
+
+ {0x9536, 0x4E20, PMD_ALL, UNIPRO_DBG_MIB, 0},
+ {0x9564, 0x2e820183, PMD_ALL, UNIPRO_DBG_MIB, 0},
+ {0x155E, 0x0, PMD_ALL, UNIPRO_STD_MIB, 0},
+ {0x3000, 0x0, PMD_ALL, UNIPRO_STD_MIB, 0},
+ {0x3001, 0x1, PMD_ALL, UNIPRO_STD_MIB, 0},
+ {0x4021, 0x1, PMD_ALL, UNIPRO_STD_MIB, 0},
+ {0x4020, 0x1, PMD_ALL, UNIPRO_STD_MIB, 0},
+
+ {0x8C, 0x80, PMD_ALL, PHY_PMA_COMN, 0},
+ {0x74, 0x10, PMD_ALL, PHY_PMA_COMN, 0},
+ {0x110, 0xB5, PMD_ALL, PHY_PMA_TRSV, 0}, // 0xBB
+ {0x134, 0x43, PMD_ALL, PHY_PMA_TRSV, 0}, // 0x03
+ {0x16C, 0x20, PMD_ALL, PHY_PMA_TRSV, 0},
+ {0x178, 0xC0, PMD_ALL, PHY_PMA_TRSV, 0}, // 0x80
+ {0x1B0, 0x94, PMD_ALL, PHY_PMA_TRSV, 0}, // 0x14
+ {0xE0, 0x12, PMD_ALL, PHY_PMA_TRSV, 0}, // 0x38
+ {0x164, 0x58, PMD_ALL, PHY_PMA_TRSV, 0}, // 0x50
+ {0x8C, 0xC0, PMD_ALL, PHY_PMA_COMN, 0},
+ {0x8C, 0x00, PMD_ALL, PHY_PMA_COMN, 0},
+ {},
+};
+
+static struct ufs_cal_phy_cfg post_init_cfg[] = {
+ {0x9529, 0x1, PMD_ALL, UNIPRO_DBG_MIB, 0},
+ {0x15A4, 0xFA, PMD_ALL, UNIPRO_STD_MIB, 0},
+ {0x9529, 0x0, PMD_ALL, UNIPRO_DBG_MIB, 0},
+ {0x200, 0x40, PMD_ALL, PHY_PCS_COMN, 0},
+ {0x35, 0x05, PMD_ALL, PHY_PCS_RX, 0},
+ {0x73, 0x01, PMD_ALL, PHY_PCS_RX, 0},
+ {0x41, 0x02, PMD_ALL, PHY_PCS_RX, 0},
+ {0x42, 0xAC, PMD_ALL, PHY_PCS_RX, 0},
+ {0x200, 0x0, PMD_ALL, PHY_PCS_COMN, 0},
+ {},
+};
+
+static struct ufs_cal_phy_cfg calib_of_pwm[] = {
+ {0x2041, 8064, PMD_PWM, UNIPRO_STD_MIB, 0},
+ {0x2042, 28224, PMD_PWM, UNIPRO_STD_MIB, 0},
+ {0x2043, 20160, PMD_PWM, UNIPRO_STD_MIB, 0},
+ {0x15B0, 12000, PMD_PWM, UNIPRO_STD_MIB, 0},
+ {0x15B1, 32000, PMD_PWM, UNIPRO_STD_MIB, 0},
+ {0x15B2, 16000, PMD_PWM, UNIPRO_STD_MIB, 0},
+
+ {0x7888, 8064, PMD_PWM, UNIPRO_DBG_APB, 0},
+ {0x788C, 28224, PMD_PWM, UNIPRO_DBG_APB, 0},
+ {0x7890, 20160, PMD_PWM, UNIPRO_DBG_APB, 0},
+ {0x78B8, 12000, PMD_PWM, UNIPRO_DBG_APB, 0},
+ {0x78BC, 32000, PMD_PWM, UNIPRO_DBG_APB, 0},
+ {0x78C0, 16000, PMD_PWM, UNIPRO_DBG_APB, 0},
+
+ //MPHY tuning value
+ {0xC8, 0x40, PMD_PWM, PHY_PMA_TRSV, 0},
+ {0xF0, 0x77, PMD_PWM, PHY_PMA_TRSV, 0},
+ {0x120, 0x80, PMD_PWM, PHY_PMA_TRSV, 0},
+ {0x128, 0x00, PMD_PWM, PHY_PMA_TRSV, 0},
+ {0x12C, 0x00, PMD_PWM, PHY_PMA_TRSV, 0},
+ {0x134, 0x43, PMD_PWM, PHY_PMA_TRSV, 0},
+ {},
+};
+
+static struct ufs_cal_phy_cfg post_calib_of_pwm[] = {
+ {},
+};
+static struct ufs_cal_phy_cfg calib_of_hs_rate_a[] = {
+ {0x2041, 8064, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x2042, 28224, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x2043, 20160, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x15B0, 12000, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x15B1, 32000, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x15B2, 16000, PMD_HS, UNIPRO_STD_MIB, 0},
+
+ {0x7888, 8064, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x788C, 28224, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x7890, 20160, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x78B8, 12000, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x78BC, 32000, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x78C0, 16000, PMD_HS, UNIPRO_DBG_APB, 0},
+
+ //MPHY tuning value
+ {0xC8, 0xBC, PMD_HS, PHY_PMA_TRSV, 0},
+ {0xF0, 0x7F, PMD_HS, PHY_PMA_TRSV, 0},
+ {0x120, 0xC0, PMD_HS, PHY_PMA_TRSV, 0},
+ {0x128, 0x08, PMD_HS_G1_L2, PHY_PMA_TRSV, 0},
+ {0x128, 0x02, PMD_HS_G2_L2, PHY_PMA_TRSV, 0},
+ {0x128, 0x00, PMD_HS_G3_L2, PHY_PMA_TRSV, 0},
+ {0x12C, 0x10, PMD_HS_G1_L2|PMD_HS_G3_L2, PHY_PMA_TRSV, 0},
+ {0x12C, 0x00, PMD_HS_G2_L2, PHY_PMA_TRSV, 0},
+ {0x134, 0xd3, PMD_HS_G1_L2, PHY_PMA_TRSV, 0},
+ {0x134, 0x73, PMD_HS_G2_L2, PHY_PMA_TRSV, 0},
+ {0x134, 0x63, PMD_HS_G3_L2, PHY_PMA_TRSV, 0},
+ {},
+};
+
+static struct ufs_cal_phy_cfg post_calib_of_hs_rate_a[] = {
+ {0x1fc, 0x40, PMD_HS, PHY_CDR_WAIT, 0},
+ {},
+};
+
+static struct ufs_cal_phy_cfg calib_of_hs_rate_b[] = {
+ {0x2041, 8064, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x2042, 28224, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x2043, 20160, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x15B0, 12000, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x15B1, 32000, PMD_HS, UNIPRO_STD_MIB, 0},
+ {0x15B2, 16000, PMD_HS, UNIPRO_STD_MIB, 0},
+
+ {0x7888, 8064, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x788C, 28224, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x7890, 20160, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x78B8, 12000, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x78BC, 32000, PMD_HS, UNIPRO_DBG_APB, 0},
+ {0x78C0, 16000, PMD_HS, UNIPRO_DBG_APB, 0},
+
+ //MPHY tuning value
+ {0xC8, 0xBC, PMD_HS, PHY_PMA_TRSV, 0},
+ {0xF0, 0x7F, PMD_HS, PHY_PMA_TRSV, 0},
+ {0x120, 0xC0, PMD_HS, PHY_PMA_TRSV, 0},
+ {0x128, 0x08, PMD_HS_G1_L2, PHY_PMA_TRSV, 0},
+ {0x128, 0x02, PMD_HS_G2_L2, PHY_PMA_TRSV, 0},
+ {0x128, 0x00, PMD_HS_G3_L2, PHY_PMA_TRSV, 0},
+ {0x12C, 0x10, PMD_HS_G1_L2|PMD_HS_G3_L2, PHY_PMA_TRSV, 0},
+ {0x12C, 0x00, PMD_HS_G2_L2, PHY_PMA_TRSV, 0},
+ {0x134, 0xd3, PMD_HS_G1_L2, PHY_PMA_TRSV, 0},
+ {0x134, 0x73, PMD_HS_G2_L2, PHY_PMA_TRSV, 0},
+ {0x134, 0x63, PMD_HS_G3_L2, PHY_PMA_TRSV, 0},
+ {},
+};
+
+static struct ufs_cal_phy_cfg post_calib_of_hs_rate_b[] = {
+ {0x1fc, 0x40, PMD_HS, PHY_CDR_WAIT, 0},
+ {},
+};
+
+static struct ufs_cal_phy_cfg lane1_sq_off[] = {
+ {0x0C4, 0x19, PMD_ALL, PHY_PMA_TRSV_LANE1_SQ_OFF, 0},
+ {0x0E8, 0xFF, PMD_ALL, PHY_PMA_TRSV_LANE1_SQ_OFF, 0},
+ {},
+};
+
+static struct ufs_cal_phy_cfg post_h8_enter[] = {
+ {0x0C4, 0x99, PMD_ALL, PHY_PMA_TRSV, 0},
+ {0x0E8, 0x7F, PMD_ALL, PHY_PMA_TRSV, 0},
+ {0x004, 0x02, PMD_ALL, PHY_PMA_COMN, 0},
+ {},
+};
+
+static struct ufs_cal_phy_cfg pre_h8_exit[] = {
+ {0x004, 0x00, PMD_ALL, PHY_PMA_COMN, 0},
+ {0x0C4, 0xD9, PMD_ALL, PHY_PMA_TRSV, 0},
+ {0x0E8, 0x77, PMD_ALL, PHY_PMA_TRSV, 0},
+ {},
+};
+
+static inline ufs_cal_errno __match_board_by_cfg(u8 board, u8 cfg_board)
+{
+ ufs_cal_errno match = UFS_CAL_ERROR;
+
+ if (cfg_board == 0)
+ match = UFS_CAL_NO_ERROR;
+ else if (board == cfg_board)
+ match = UFS_CAL_NO_ERROR;
+
+ return match;
+}
+
+static inline ufs_cal_errno __match_mode_by_cfg(struct uic_pwr_mode *pmd,
+ int mode)
+{
+ ufs_cal_errno match = UFS_CAL_ERROR;
+ u8 _m, _l, _g;
+
+ _m = pmd->mode;
+ _g = pmd->gear;
+ _l = pmd->lane;
+
+ if (mode == PMD_ALL)
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_HS(_m) && mode == PMD_HS)
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && mode == PMD_PWM)
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_HS(_m) && _g == 1 && _l == 1
+ && (mode & (PMD_HS_G1_L1|PMD_HS_G1_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_HS(_m) && _g == 1 && _l == 2
+ && (mode & (PMD_HS_G1_L1|PMD_HS_G1_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_HS(_m) && _g == 2 && _l == 1
+ && (mode & (PMD_HS_G2_L1|PMD_HS_G2_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_HS(_m) && _g == 2 && _l == 2
+ && (mode & (PMD_HS_G2_L1|PMD_HS_G2_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_HS(_m) && _g == 3 && _l == 1
+ && (mode & (PMD_HS_G3_L1|PMD_HS_G3_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_HS(_m) && _g == 3 && _l == 2
+ && (mode & (PMD_HS_G3_L1|PMD_HS_G3_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 1 && _l == 1
+ && (mode & (PMD_PWM_G1_L1|PMD_PWM_G1_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 1 && _l == 2
+ && (mode & (PMD_PWM_G1_L1|PMD_PWM_G1_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 2 && _l == 1
+ && (mode & (PMD_PWM_G2_L1|PMD_PWM_G2_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 2 && _l == 2
+ && (mode & (PMD_PWM_G2_L1|PMD_PWM_G2_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 3 && _l == 1
+ && (mode & (PMD_PWM_G3_L1|PMD_PWM_G3_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 3 && _l == 2
+ && (mode & (PMD_PWM_G3_L1|PMD_PWM_G3_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 4 && _l == 1
+ && (mode & (PMD_PWM_G4_L1|PMD_PWM_G4_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 4 && _l == 2
+ && (mode & (PMD_PWM_G4_L1|PMD_PWM_G4_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 5 && _l == 1
+ && (mode & (PMD_PWM_G5_L1|PMD_PWM_G5_L2)))
+ match = UFS_CAL_NO_ERROR;
+ else if (IS_PWR_MODE_PWM(_m) && _g == 5 && _l == 2
+ && (mode & (PMD_PWM_G5_L1|PMD_PWM_G5_L2)))
+ match = UFS_CAL_NO_ERROR;
+
+ return match;
+}
+
+static inline ufs_cal_errno ufs_cal_wait_pll_lock(void *hba,
+ u32 addr, u32 mask)
+{
+ u32 delay_us = 1;
+ u32 period_ms = 1;
+ u32 reg;
+ unsigned long timeout = ufs_lld_get_time_count(0) + ufs_cal_lock_timeout;
+
+ do {
+ reg = ufs_lld_pma_read(hba, PHY_PMA_COMN_ADDR(addr));
+ if (mask == (reg & mask))
+ return UFS_CAL_NO_ERROR;
+ ufs_lld_usleep_delay(delay_us, delay_us);
+ } while ((long)(ufs_lld_get_time_count(period_ms) - timeout) >= 0);
+
+ return UFS_CAL_ERROR;
+}
+
+static inline ufs_cal_errno ufs_cal_wait_cdr_lock(void *hba,
+ u32 addr, u32 mask, int lane)
+{
+ u32 delay_us = 1;
+ u32 period_ms = 1;
+ u32 reg;
+ unsigned long timeout = ufs_lld_get_time_count(0) + ufs_cal_lock_timeout;
+
+ do {
+ reg = ufs_lld_pma_read(hba, PHY_PMA_TRSV_ADDR(addr, lane));
+ if (mask == (reg & mask))
+ return UFS_CAL_NO_ERROR;
+ ufs_lld_usleep_delay(delay_us, delay_us);
+ } while ((long)(ufs_lld_get_time_count(period_ms) - timeout) >= 0);
+
+ return UFS_CAL_ERROR;
+
+}
+
+static ufs_cal_errno ufs_cal_config_uic(struct ufs_cal_param *p,
+ const struct ufs_cal_phy_cfg *cfg,
+ struct uic_pwr_mode *pmd)
+{
+ void *hba = p->host;
+ u8 i = 0;
+
+ if (!cfg)
+ return UFS_CAL_INV_ARG;
+
+ for_each_phy_cfg(cfg) {
+ for (i = 0; i < p->target_lane; i++) {
+ if (p->board && UFS_CAL_ERROR ==
+ __match_board_by_cfg(p->board, cfg->board))
+ continue;
+ if (pmd && UFS_CAL_ERROR ==
+ __match_mode_by_cfg(pmd, cfg->flg))
+ continue;
+
+ switch (cfg->lyr) {
+ case PHY_PCS_COMN:
+ case UNIPRO_STD_MIB:
+ case UNIPRO_DBG_MIB:
+ if (i == 0)
+ ufs_lld_dme_set(hba, UIC_ARG_MIB(cfg->addr),
+ cfg->val);
+ break;
+ case PHY_PCS_RXTX:
+ ufs_lld_dme_set(hba, UIC_ARG_MIB_SEL(cfg->addr, i),
+ cfg->val);
+ break;
+ case UNIPRO_DBG_PRD:
+ if (i == 0)
+ ufs_lld_dme_set(hba, UIC_ARG_MIB(cfg->addr),
+ UNIPRO_MCLK_PERIOD(p));
+ break;
+ case PHY_PCS_RX:
+ ufs_lld_dme_set(hba, UIC_ARG_MIB_SEL(cfg->addr,
+ RX_LANE_0+i), cfg->val);
+ break;
+ case PHY_PCS_TX:
+ ufs_lld_dme_set(hba, UIC_ARG_MIB_SEL(cfg->addr,
+ TX_LANE_0+i), cfg->val);
+ break;
+ case PHY_PCS_RX_PRD:
+ ufs_lld_dme_set(hba, UIC_ARG_MIB_SEL(cfg->addr,
+ RX_LANE_0+i), UNIPRO_MCLK_PERIOD(p));
+ break;
+
+ case PHY_PCS_TX_PRD:
+ ufs_lld_dme_set(hba, UIC_ARG_MIB_SEL(cfg->addr,
+ TX_LANE_0+i), UNIPRO_MCLK_PERIOD(p));
+ break;
+ case PHY_PMA_COMN:
+ if (i == 0)
+ ufs_lld_pma_write(hba, cfg->val,
+ PHY_PMA_COMN_ADDR(cfg->addr));
+ break;
+ case PHY_PMA_TRSV:
+ ufs_lld_pma_write(hba, cfg->val,
+ PHY_PMA_TRSV_ADDR(cfg->addr, i));
+ break;
+ case PHY_PMA_TRSV_LANE1_SQ_OFF:
+ if (i == 1)
+ ufs_lld_pma_write(hba, cfg->val,
+ PHY_PMA_TRSV_ADDR(cfg->addr, i));
+ break;
+ case UNIPRO_DBG_APB:
+ ufs_lld_unipro_write(hba, cfg->val, cfg->addr);
+ break;
+ case PHY_PLL_WAIT:
+ if (i == 0) {
+ if (ufs_cal_wait_pll_lock(hba,
+ cfg->addr, cfg->val) ==
+ UFS_CAL_ERROR)
+ return UFS_CAL_TIMEOUT;
+ }
+ break;
+ case PHY_CDR_WAIT:
+ if (ufs_cal_wait_cdr_lock(hba,
+ cfg->addr, cfg->val, i) ==
+ UFS_CAL_ERROR)
+ return UFS_CAL_TIMEOUT;
+ break;
+ case COMMON_WAIT:
+ if (i == 0)
+ ufs_lld_udelay(cfg->val);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ return UFS_CAL_NO_ERROR;
+}
+
+/*
+ * This is a recommendation from Samsung UFS device vendor.
+ *
+ * Activate time: host < device
+ * Hibern time: host > device
+ */
+static void ufs_cal_calib_hibern8_values(void *hba)
+{
+ u32 hw_cap_min_tactivate;
+ u32 peer_rx_min_actv_time_cap;
+ u32 max_rx_hibern8_time_cap;
+
+ ufs_lld_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, RX_LANE_0),
+ &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */
+
+ ufs_lld_dme_get(hba, UIC_ARG_MIB(0x15A8),
+ &peer_rx_min_actv_time_cap); /* PA_TActivate */
+ ufs_lld_dme_get(hba, UIC_ARG_MIB(0x15A7),
+ &max_rx_hibern8_time_cap); /* PA_Hibern8Time */
+
+ if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate)
+ ufs_lld_dme_peer_set(hba, UIC_ARG_MIB(0x15A8),
+ peer_rx_min_actv_time_cap + 1);
+ ufs_lld_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap + 1);
+}
+
+ufs_cal_errno ufs_cal_post_h8_enter(struct ufs_cal_param *p)
+{
+ ufs_cal_errno ret = UFS_CAL_NO_ERROR;
+
+ ret = ufs_cal_config_uic(p, post_h8_enter, p->pmd);
+
+ return ret;
+}
+
+ufs_cal_errno ufs_cal_pre_h8_exit(struct ufs_cal_param *p)
+{
+ ufs_cal_errno ret = UFS_CAL_NO_ERROR;
+
+ ret = ufs_cal_config_uic(p, pre_h8_exit, p->pmd);
+
+ return ret;
+}
+
+/*
+ * This currently uses only SLOW_MODE and FAST_MODE.
+ * If you want others, you should modify this function.
+ */
+ufs_cal_errno ufs_cal_pre_pmc(struct ufs_cal_param *p)
+{
+ ufs_cal_errno ret = UFS_CAL_NO_ERROR;
+ struct ufs_cal_phy_cfg *cfg;
+
+ if ((p->pmd->mode == SLOW_MODE) || (p->pmd->mode == SLOWAUTO_MODE))
+ cfg = calib_of_pwm;
+ else if (p->pmd->hs_series == PA_HS_MODE_B)
+ cfg = calib_of_hs_rate_b;
+ else if (p->pmd->hs_series == PA_HS_MODE_A)
+ cfg = calib_of_hs_rate_a;
+ else
+ return UFS_CAL_INV_ARG;
+
+ /*
+ * If a number of target lanes is 1 and a host's
+ * a number of available lanes is 2,
+ * you should turn off phy power of lane #1.
+ *
+ * This must be modified when a number of avaiable lanes
+ * would grow in the future.
+ */
+ if ((p->available_lane == 2) && (p->target_lane == 1))
+ ret = ufs_cal_config_uic(p, lane1_sq_off, NULL);
+
+ ret = ufs_cal_config_uic(p, cfg, p->pmd);
+
+ return ret;
+}
+
+/*
+ * This currently uses only SLOW_MODE and FAST_MODE.
+ * If you want others, you should modify this function.
+ */
+ufs_cal_errno ufs_cal_post_pmc(struct ufs_cal_param *p)
+{
+ ufs_cal_errno ret = UFS_CAL_NO_ERROR;
+ struct ufs_cal_phy_cfg *cfg;
+
+ if ((p->pmd->mode == SLOWAUTO_MODE) || (p->pmd->mode == SLOW_MODE))
+ cfg = post_calib_of_pwm;
+ else if (p->pmd->hs_series == PA_HS_MODE_B)
+ cfg = post_calib_of_hs_rate_b;
+ else if (p->pmd->hs_series == PA_HS_MODE_A)
+ cfg = post_calib_of_hs_rate_a;
+ else
+ return UFS_CAL_INV_ARG;
+
+ ret = ufs_cal_config_uic(p, cfg, p->pmd);
+
+ return ret;
+}
+
+ufs_cal_errno ufs_cal_post_link(struct ufs_cal_param *p)
+{
+ ufs_cal_errno ret = UFS_CAL_NO_ERROR;
+
+ ufs_cal_calib_hibern8_values(p->host);
+
+ ret = ufs_cal_config_uic(p, post_init_cfg, NULL);
+
+ return ret;
+}
+
+ufs_cal_errno ufs_cal_pre_link(struct ufs_cal_param *p)
+{
+ ufs_cal_errno ret = UFS_CAL_NO_ERROR;
+
+ ret = ufs_cal_config_uic(p, init_cfg, NULL);
+
+ return ret;
+}
+
+ufs_cal_errno ufs_cal_init(struct ufs_cal_param *p, int idx)
+{
+ /*
+ * Return if innput index is greater than
+ * the maximum that cal supports
+ */
+ if (idx >= NUM_OF_UFS_HOST)
+ return UFS_CAL_INV_ARG;
+
+ ufs_cal[idx] = p;
+
+ ufs_cal_lock_timeout = ufs_lld_calc_timeout(100);
+
+ return UFS_CAL_NO_ERROR;
+}
#include "mphy.h"
#include "ufs-exynos.h"
-#if !defined(CONFIG_SOC_EXYNOS7420) && !defined(CONFIG_SOC_EXYNOS8890)
+#if defined(CONFIG_SOC_EXYNOS9610)
+static struct exynos_ufs_sfr_log ufs_log_sfr[] = {
+ {"STD HCI SFR" , LOG_STD_HCI_SFR, 0},
+
+ {"INTERRUPT STATUS" , REG_INTERRUPT_STATUS, 0},
+ {"INTERRUPT ENABLE" , REG_INTERRUPT_ENABLE, 0},
+ {"CONTROLLER STATUS" , REG_CONTROLLER_STATUS, 0},
+ {"CONTROLLER ENABLE" , REG_CONTROLLER_ENABLE, 0},
+ {"UIC ERR PHY ADAPTER LAYER" , REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER, 0},
+ {"UIC ERR DATA LINK LAYER" , REG_UIC_ERROR_CODE_DATA_LINK_LAYER, 0},
+ {"UIC ERR NETWORK LATER" , REG_UIC_ERROR_CODE_NETWORK_LAYER, 0},
+ {"UIC ERR TRANSPORT LAYER" , REG_UIC_ERROR_CODE_TRANSPORT_LAYER, 0},
+ {"UIC ERR DME" , REG_UIC_ERROR_CODE_DME, 0},
+ {"UTP TRANSF REQ INT AGG CNTRL" , REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL, 0},
+ {"UTP TRANSF REQ LIST BASE L" , REG_UTP_TRANSFER_REQ_LIST_BASE_L, 0},
+ {"UTP TRANSF REQ LIST BASE H" , REG_UTP_TRANSFER_REQ_LIST_BASE_H, 0},
+ {"UTP TRANSF REQ DOOR BELL" , REG_UTP_TRANSFER_REQ_DOOR_BELL, 0},
+ {"UTP TRANSF REQ LIST CLEAR" , REG_UTP_TRANSFER_REQ_LIST_CLEAR, 0},
+ {"UTP TRANSF REQ LIST RUN STOP" , REG_UTP_TRANSFER_REQ_LIST_RUN_STOP, 0},
+ {"UTP TRANSF REQ LIST CNR" , REG_UTP_TRANSFER_REQ_LIST_CNR, 0},
+ {"UTP TASK REQ LIST BASE L" , REG_UTP_TASK_REQ_LIST_BASE_L, 0},
+ {"UTP TASK REQ LIST BASE H" , REG_UTP_TASK_REQ_LIST_BASE_H, 0},
+ {"UTP TASK REQ DOOR BELL" , REG_UTP_TASK_REQ_DOOR_BELL, 0},
+ {"UTP TASK REQ LIST CLEAR" , REG_UTP_TASK_REQ_LIST_CLEAR, 0},
+ {"UTP TASK REQ LIST RUN STOP" , REG_UTP_TASK_REQ_LIST_RUN_STOP, 0},
+ {"UIC COMMAND" , REG_UIC_COMMAND, 0},
+ {"UIC COMMAND ARG1" , REG_UIC_COMMAND_ARG_1, 0},
+ {"UIC COMMAND ARG2" , REG_UIC_COMMAND_ARG_2, 0},
+ {"UIC COMMAND ARG3" , REG_UIC_COMMAND_ARG_3, 0},
+ {"CCAP" , REG_CRYPTO_CAPABILITY, 0},
+
+
+ {"VS HCI SFR" , LOG_VS_HCI_SFR, 0},
+
+ {"TXPRDT ENTRY SIZE" , HCI_TXPRDT_ENTRY_SIZE, 0},
+ {"RXPRDT ENTRY SIZE" , HCI_RXPRDT_ENTRY_SIZE, 0},
+ {"TO CNT DIV VAL" , HCI_TO_CNT_DIV_VAL, 0},
+ {"1US TO CNT VAL" , HCI_1US_TO_CNT_VAL, 0},
+ {"INVALID UPIU CTRL" , HCI_INVALID_UPIU_CTRL, 0},
+ {"INVALID UPIU BADDR" , HCI_INVALID_UPIU_BADDR, 0},
+ {"INVALID UPIU UBADDR" , HCI_INVALID_UPIU_UBADDR, 0},
+ {"INVALID UTMR OFFSET ADDR" , HCI_INVALID_UTMR_OFFSET_ADDR, 0},
+ {"INVALID UTR OFFSET ADDR" , HCI_INVALID_UTR_OFFSET_ADDR, 0},
+ {"INVALID DIN OFFSET ADDR" , HCI_INVALID_DIN_OFFSET_ADDR, 0},
+ {"VENDOR SPECIFIC IS" , HCI_VENDOR_SPECIFIC_IS, 0},
+ {"VENDOR SPECIFIC IE" , HCI_VENDOR_SPECIFIC_IE, 0},
+ {"UTRL NEXUS TYPE" , HCI_UTRL_NEXUS_TYPE, 0},
+ {"UTMRL NEXUS TYPE" , HCI_UTMRL_NEXUS_TYPE, 0},
+ {"SW RST" , HCI_SW_RST, 0},
+ {"RX UPIU MATCH ERROR CODE" , HCI_RX_UPIU_MATCH_ERROR_CODE, 0},
+ {"DATA REORDER" , HCI_DATA_REORDER, 0},
+ {"AXIDMA RWDATA BURST LEN" , HCI_AXIDMA_RWDATA_BURST_LEN, 0},
+ {"WRITE DMA CTRL" , HCI_WRITE_DMA_CTRL, 0},
+ {"V2P1 CTRL" , HCI_UFSHCI_V2P1_CTRL, 0},
+ {"CLKSTOP CTRL" , HCI_CLKSTOP_CTRL, 0},
+ {"FORCE HCS" , HCI_FORCE_HCS, 0},
+ {"FSM MONITOR" , HCI_FSM_MONITOR, 0},
+ {"DMA0 MONITOR STATE" , HCI_DMA0_MONITOR_STATE, 0},
+ {"DMA0 MONITOR CNT" , HCI_DMA0_MONITOR_CNT, 0},
+ {"DMA1 MONITOR STATE" , HCI_DMA1_MONITOR_STATE, 0},
+ {"DMA1 MONITOR CNT" , HCI_DMA1_MONITOR_CNT, 0},
+ {"AXI DMA IF CTRL" , HCI_UFS_AXI_DMA_IF_CTRL, 0},
+ {"UFS ACG DISABLE" , HCI_UFS_ACG_DISABLE, 0},
+ {"MPHY REFCLK SEL" , HCI_MPHY_REFCLK_SEL, 0},
+ {"SMU ABORT MATCH INFO" , HCI_SMU_ABORT_MATCH_INFO, 0},
+ {"DBR DUPLICATION INFO" , HCI_DBR_DUPLICATION_INFO, 0},
+ {"DBR TIMER CONFIG" , HCI_DBR_TIMER_CONFIG, 0},
+ {"DBR TIMER ENABLE" , HCI_DBR_TIMER_ENABLE, 0},
+ {"DBR TIMER STATUS" , HCI_DBR_TIMER_STATUS, 0},
+ {"UTRL DBR 3 0 TIMER EXPIRED VALUE" , HCI_UTRL_DBR_3_0_TIMER_EXPIRED_VALUE, 0},
+ {"UTRL DBR 7 4 TIMER EXPIRED VALUE" , HCI_UTRL_DBR_7_4_TIMER_EXPIRED_VALUE, 0},
+ {"UTRL DBR 11 8 TIMER EXPIRED VALUE" , HCI_UTRL_DBR_11_8_TIMER_EXPIRED_VALUE, 0},
+ {"UTRL DBR 15 12 TIMER EXPIRED VALUE" , HCI_UTRL_DBR_15_12_TIMER_EXPIRED_VALUE, 0},
+ {"UTMRL DBR 3 0 TIMER EXPIRED VALUE" , HCI_UTMRL_DBR_3_0_TIMER_EXPIRED_VALUE, 0},
+
+ {"FMP SFR" , LOG_FMP_SFR, 0},
+
+ {"UFSPRCTRL" , UFSPRCTRL, 0},
+ {"UFSPRSTAT" , UFSPRSTAT, 0},
+ {"UFSPRSECURITY" , UFSPRSECURITY, 0},
+ {"UFSPWCTRL" , UFSPWCTRL, 0},
+ {"UFSPWSTAT" , UFSPWSTAT, 0},
+ {"UFSPSBEGIN0" , UFSPSBEGIN0, 0},
+ {"UFSPSEND0" , UFSPSEND0, 0},
+ {"UFSPSLUN0" , UFSPSLUN0, 0},
+ {"UFSPSCTRL0" , UFSPSCTRL0, 0},
+ {"UFSPSBEGIN1" , UFSPSBEGIN1, 0},
+ {"UFSPSEND1" , UFSPSEND1, 0},
+ {"UFSPSLUN1" , UFSPSLUN1, 0},
+ {"UFSPSCTRL1" , UFSPSCTRL1, 0},
+ {"UFSPSBEGIN2" , UFSPSBEGIN2, 0},
+ {"UFSPSEND2" , UFSPSEND2, 0},
+ {"UFSPSLUN2" , UFSPSLUN2, 0},
+ {"UFSPSCTRL2" , UFSPSCTRL2, 0},
+ {"UFSPSBEGIN3" , UFSPSBEGIN3, 0},
+ {"UFSPSEND3" , UFSPSEND3, 0},
+ {"UFSPSLUN3" , UFSPSLUN3, 0},
+ {"UFSPSCTRL3" , UFSPSCTRL3, 0},
+ {"UFSPSBEGIN4" , UFSPSBEGIN4, 0},
+ {"UFSPSLUN4" , UFSPSLUN4, 0},
+ {"UFSPSCTRL4" , UFSPSCTRL4, 0},
+ {"UFSPSBEGIN5" , UFSPSBEGIN5, 0},
+ {"UFSPSEND5" , UFSPSEND5, 0},
+ {"UFSPSLUN5" , UFSPSLUN5, 0},
+ {"UFSPSCTRL5" , UFSPSCTRL5, 0},
+ {"UFSPSBEGIN6" , UFSPSBEGIN6, 0},
+ {"UFSPSEND6" , UFSPSEND6, 0},
+ {"UFSPSLUN6" , UFSPSLUN6, 0},
+ {"UFSPSCTRL6" , UFSPSCTRL6, 0},
+ {"UFSPSBEGIN7" , UFSPSBEGIN7, 0},
+ {"UFSPSEND7" , UFSPSEND7, 0},
+ {"UFSPSLUN7" , UFSPSLUN7, 0},
+ {"UFSPSCTRL7" , UFSPSCTRL7, 0},
+
+ {"UNIPRO SFR" , LOG_UNIPRO_SFR, 0},
+
+ {"DME_LINKSTARTUP_CNF_RESULT" , UNIP_DME_LINKSTARTUP_CNF_RESULT , 0},
+ {"DME_HIBERN8_ENTER_CNF_RESULT" , UNIP_DME_HIBERN8_ENTER_CNF_RESULT, 0},
+ {"DME_HIBERN8_ENTER_IND_RESULT" , UNIP_DME_HIBERN8_ENTER_IND_RESULT, 0},
+ {"DME_HIBERN8_EXIT_CNF_RESULT" , UNIP_DME_HIBERN8_EXIT_CNF_RESULT, 0},
+ {"DME_HIBERN8_EXIT_IND_RESULT" , UNIP_DME_HIBERN8_EXIT_IND_RESULT, 0},
+ {"DME_PWR_IND_RESULT" , UNIP_DME_PWR_IND_RESULT , 0},
+ {"DME_INTR_STATUS_LSB" , UNIP_DME_INTR_STATUS_LSB, 0},
+ {"DME_INTR_STATUS_MSB" , UNIP_DME_INTR_STATUS_MSB, 0},
+ {"DME_INTR_ERROR_CODE" , UNIP_DME_INTR_ERROR_CODE, 0},
+ {"DME_DISCARD_PORT_ID" , UNIP_DME_DISCARD_PORT_ID, 0},
+ {"DME_DBG_OPTION_SUITE" , UNIP_DME_DBG_OPTION_SUITE, 0},
+ {"DME_DBG_CTRL_FSM" , UNIP_DME_DBG_CTRL_FSM, 0},
+ {"DME_DBG_FLAG_STATUS" , UNIP_DME_DBG_FLAG_STATUS, 0},
+ {"DME_DBG_LINKCFG_FSM" , UNIP_DME_DBG_LINKCFG_FSM, 0},
+
+ {"PMA SFR" , LOG_PMA_SFR, 0},
+
+ {"0x74", 0x74, 0},
+ {"0x110", 0x110, 0},
+ {"0x134", 0x134, 0},
+ {"0x16C", 0x16C, 0},
+ {"0x178", 0x178, 0},
+ {"0x1B0", 0x1B0, 0},
+ {"0xE0", 0xE0, 0},
+ {"0x164", 0x164, 0},
+ {"0x8C", 0x8C, 0},
+
+ {"0xC8", 0xC8, 0},
+ {"0xF0", 0xF0, 0},
+ {"0x120",0x120, 0},
+ {},
+};
+
+static struct exynos_ufs_attr_log ufs_log_attr[] = {
+ /* PA Standard */
+ {UIC_ARG_MIB(0x1520), 0, 0},
+ {UIC_ARG_MIB(0x1540), 0, 0},
+ {UIC_ARG_MIB(0x1543), 0, 0},
+ {UIC_ARG_MIB(0x155C), 0, 0},
+ {UIC_ARG_MIB(0x155D), 0, 0},
+ {UIC_ARG_MIB(0x155E), 0, 0},
+ {UIC_ARG_MIB(0x155F), 0, 0},
+ {UIC_ARG_MIB(0x1560), 0, 0},
+ {UIC_ARG_MIB(0x1561), 0, 0},
+ {UIC_ARG_MIB(0x1564), 0, 0},
+ {UIC_ARG_MIB(0x1567), 0, 0},
+ {UIC_ARG_MIB(0x1568), 0, 0},
+ {UIC_ARG_MIB(0x1569), 0, 0},
+ {UIC_ARG_MIB(0x156A), 0, 0},
+ {UIC_ARG_MIB(0x1571), 0, 0},
+ {UIC_ARG_MIB(0x1580), 0, 0},
+ {UIC_ARG_MIB(0x1581), 0, 0},
+ {UIC_ARG_MIB(0x1582), 0, 0},
+ {UIC_ARG_MIB(0x1583), 0, 0},
+ {UIC_ARG_MIB(0x1584), 0, 0},
+ {UIC_ARG_MIB(0x1585), 0, 0},
+ {UIC_ARG_MIB(0x1590), 0, 0},
+ {UIC_ARG_MIB(0x1591), 0, 0},
+ {UIC_ARG_MIB(0x15A1), 0, 0},
+ {UIC_ARG_MIB(0x15A2), 0, 0},
+ {UIC_ARG_MIB(0x15A3), 0, 0},
+ {UIC_ARG_MIB(0x15A4), 0, 0},
+ {UIC_ARG_MIB(0x15A7), 0, 0},
+ {UIC_ARG_MIB(0x15A8), 0, 0},
+ {UIC_ARG_MIB(0x15C0), 0, 0},
+ {UIC_ARG_MIB(0x15C1), 0, 0},
+
+ /* PA Debug */
+
+ /* DL Standard */
+ {UIC_ARG_MIB(0x2046), 0, 0},
+ {UIC_ARG_MIB(0x2047), 0, 0},
+ {UIC_ARG_MIB(0x2066), 0, 0},
+ {UIC_ARG_MIB(0x2067), 0, 0},
+
+ /* DL Debug */
+
+ /* NL Standard */
+ {UIC_ARG_MIB(0x3000), 0, 0},
+ {UIC_ARG_MIB(0x3001), 0, 0},
+
+ /* NL Debug */
+
+ /* TL Standard */
+ {UIC_ARG_MIB(0x4020), 0, 0},
+ {UIC_ARG_MIB(0x4021), 0, 0},
+ {UIC_ARG_MIB(0x4022), 0, 0},
+ {UIC_ARG_MIB(0x4023), 0, 0},
+ {UIC_ARG_MIB(0x4025), 0, 0},
+ {UIC_ARG_MIB(0x402B), 0, 0},
+
+ /* TL Debug */
+
+ /* MPHY PCS Lane 0 Standard*/
+ {UIC_ARG_MIB_SEL(0x0004, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0021, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0022, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0023, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0024, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0028, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0029, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x002A, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x002B, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x002C, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x002D, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0033, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0035, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0036, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x0041, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB(0x8F), 0, 0},
+
+ {UIC_ARG_MIB_SEL(0x0F, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x65, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x69, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x21, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x22, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x84, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x35, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x73, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x41, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x42, RX_LANE_0+0), 0, 0},
+
+ {UIC_ARG_MIB_SEL(0x00A1, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x00A2, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x00A3, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x00A4, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x00A7, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x00C1, RX_LANE_0+0), 0, 0},
+ {},
+};
+
+static struct exynos_ufs_sfr_log ufs_show_sfr[] = {
+ {},
+};
+
+static struct exynos_ufs_attr_log ufs_show_attr[] = {
+ {},
+};
+#elif defined(CONFIG_SOC_EXYNOS9810)
/*
* This is a list for latest SoC.
*/
{"PMA SFR" , LOG_PMA_SFR, 0},
{"COMN 0x00" , (0x00<<2), 0},
- {"COMN 0x01" , (0x01<<2), 0},
- {"COMN 0x02" , (0x02<<2), 0},
- {"COMN 0x03" , (0x03<<2), 0},
- {"COMN 0x04" , (0x04<<2), 0},
- {"COMN 0x05" , (0x05<<2), 0},
- {"COMN 0x06" , (0x06<<2), 0},
- {"COMN 0x07" , (0x07<<2), 0},
- {"COMN 0x08" , (0x08<<2), 0},
- {"COMN 0x0a" , (0x0a<<2), 0},
- {"COMN 0x0b" , (0x0b<<2), 0},
- {"COMN 0x0c" , (0x0c<<2), 0},
- {"COMN 0x0d" , (0x0d<<2), 0},
- {"COMN 0x0e" , (0x0e<<2), 0},
- {"COMN 0x0f" , (0x0f<<2), 0},
- {"COMN 0x10" , (0x10<<2), 0},
- {"COMN 0x11" , (0x11<<2), 0},
- {"COMN 0x12" , (0x12<<2), 0},
- {"COMN 0x13" , (0x13<<2), 0},
- {"COMN 0x14" , (0x14<<2), 0},
- {"COMN 0x15" , (0x15<<2), 0},
- {"COMN 0x16" , (0x16<<2), 0},
- {"COMN 0x17" , (0x17<<2), 0},
- {"COMN 0x18" , (0x18<<2), 0},
- {"COMN 0x19" , (0x19<<2), 0},
- {"COMN 0x1a" , (0x1a<<2), 0},
- {"COMN 0x1b" , (0x1b<<2), 0},
- {"COMN 0x1c" , (0x1c<<2), 0},
- {"COMN 0x1d" , (0x1d<<2), 0},
- {"COMN 0x1e" , (0x1e<<2), 0},
- {"COMN 0x1f" , (0x1f<<2), 0},
- {"COMN 0x20" , (0x20<<2), 0},
- {"COMN 0x21" , (0x21<<2), 0},
- {"COMN 0x22" , (0x22<<2), 0},
- {"COMN 0x23" , (0x23<<2), 0},
- {"COMN 0x24" , (0x24<<2), 0},
- {"COMN 0x25" , (0x25<<2), 0},
- {"COMN 0x26" , (0x26<<2), 0},
- {"COMN 0x27" , (0x27<<2), 0},
- {"COMN 0x28" , (0x28<<2), 0},
- {"COMN 0x29" , (0x29<<2), 0},
- {"COMN 0x2a" , (0x2a<<2), 0},
- {"COMN 0x2b" , (0x2b<<2), 0},
- {"COMN 0x2c" , (0x2c<<2), 0},
- {"COMN 0x2d" , (0x2d<<2), 0},
- {"COMN 0x2e" , (0x2e<<2), 0},
- {"COMN 0x2f" , (0x2f<<2), 0},
- {"COMN 0x30" , (0x30<<2), 0},
{"TRSV 0x31" , (0x31<<2), 0},
- {"TRSV 0x32" , (0x32<<2), 0},
- {"TRSV 0x33" , (0x33<<2), 0},
- {"TRSV 0x34" , (0x34<<2), 0},
- {"TRSV 0x35" , (0x35<<2), 0},
- {"TRSV 0x36" , (0x36<<2), 0},
- {"TRSV 0x37" , (0x37<<2), 0},
- {"TRSV 0x38" , (0x38<<2), 0},
- {"TRSV 0x3a" , (0x3a<<2), 0},
- {"TRSV 0x3b" , (0x3b<<2), 0},
- {"TRSV 0x3c" , (0x3c<<2), 0},
- {"TRSV 0x3d" , (0x3d<<2), 0},
- {"TRSV 0x3e" , (0x3e<<2), 0},
- {"TRSV 0x3f" , (0x3f<<2), 0},
- {"TRSV 0x40" , (0x40<<2), 0},
- {"TRSV 0x41" , (0x41<<2), 0},
- {"TRSV 0x42" , (0x42<<2), 0},
- {"TRSV 0x43" , (0x43<<2), 0},
- {"TRSV 0x44" , (0x44<<2), 0},
- {"TRSV 0x45" , (0x45<<2), 0},
- {"TRSV 0x46" , (0x46<<2), 0},
- {"TRSV 0x47" , (0x47<<2), 0},
- {"TRSV 0x48" , (0x48<<2), 0},
- {"TRSV 0x49" , (0x49<<2), 0},
- {"TRSV 0x4a" , (0x4a<<2), 0},
- {"TRSV 0x4b" , (0x4b<<2), 0},
- {"TRSV 0x4c" , (0x4c<<2), 0},
- {"TRSV 0x4d" , (0x4d<<2), 0},
- {"TRSV 0x4e" , (0x4e<<2), 0},
- {"TRSV 0x4f" , (0x4f<<2), 0},
- {"TRSV 0x50" , (0x50<<2), 0},
- {"TRSV 0x51" , (0x51<<2), 0},
- {"TRSV 0x52" , (0x52<<2), 0},
- {"TRSV 0x53" , (0x53<<2), 0},
- {"TRSV 0x54" , (0x54<<2), 0},
- {"TRSV 0x55" , (0x55<<2), 0},
- {"TRSV 0x56" , (0x56<<2), 0},
- {"TRSV 0x57" , (0x57<<2), 0},
- {"TRSV 0x58" , (0x58<<2), 0},
- {"TRSV 0x59" , (0x59<<2), 0},
- {"TRSV 0x5a" , (0x5a<<2), 0},
- {"TRSV 0x5b" , (0x5b<<2), 0},
- {"TRSV 0x5c" , (0x5c<<2), 0},
- {"TRSV 0x5d" , (0x5d<<2), 0},
- {"TRSV 0x5e" , (0x5e<<2), 0},
- {"TRSV 0x5f" , (0x5f<<2), 0},
- {"TRSV 0x60" , (0x60<<2), 0},
- {"TRSV 0x61" , (0x61<<2), 0},
- {"TRSV 0x62" , (0x62<<2), 0},
- {"TRSV 0x63" , (0x63<<2), 0},
- {"TRSV 0x64" , (0x64<<2), 0},
- {"TRSV 0x65" , (0x65<<2), 0},
- {"TRSV 0x66" , (0x66<<2), 0},
- {"TRSV 0x67" , (0x67<<2), 0},
- {"TRSV 0x68" , (0x68<<2), 0},
- {"TRSV 0x6a" , (0x6a<<2), 0},
- {"TRSV 0x6b" , (0x6b<<2), 0},
- {"TRSV 0x6c" , (0x6c<<2), 0},
- {"TRSV 0x6d" , (0x6d<<2), 0},
- {"TRSV 0x6e" , (0x6e<<2), 0},
- {"TRSV 0x6f" , (0x6f<<2), 0},
- {"TRSV 0x70" , (0x70<<2), 0},
- {"TRSV 0x71" , (0x71<<2), 0},
- {"TRSV 0x72" , (0x72<<2), 0},
- {"TRSV 0x73" , (0x73<<2), 0},
- {"TRSV 0x74" , (0x74<<2), 0},
- {"TRSV 0x75" , (0x75<<2), 0},
- {"TRSV 0x76" , (0x76<<2), 0},
- {"TRSV 0x77" , (0x77<<2), 0},
- {"TRSV 0x78" , (0x78<<2), 0},
- {"TRSV 0x79" , (0x79<<2), 0},
- {"TRSV 0x7a" , (0x7a<<2), 0},
- {"TRSV 0x7b" , (0x7b<<2), 0},
- {"TRSV 0x7c" , (0x7c<<2), 0},
- {"TRSV 0x7d" , (0x7d<<2), 0},
- {"TRSV 0x7e" , (0x7e<<2), 0},
- {"TRSV 0x7f" , (0x7f<<2), 0},
{},
};
{UIC_ARG_MIB(0x15C0), 0, 0},
{UIC_ARG_MIB(0x15C1), 0, 0},
/* PA Debug */
- {UIC_ARG_MIB(0x9500), 0, 0},
- {UIC_ARG_MIB(0x9501), 0, 0},
- {UIC_ARG_MIB(0x9502), 0, 0},
- {UIC_ARG_MIB(0x9503), 0, 0},
- {UIC_ARG_MIB(0x9510), 0, 0},
- {UIC_ARG_MIB(0x9511), 0, 0},
- {UIC_ARG_MIB(0x9514), 0, 0},
- {UIC_ARG_MIB(0x9515), 0, 0},
- {UIC_ARG_MIB(0x9516), 0, 0},
- {UIC_ARG_MIB(0x9517), 0, 0},
- {UIC_ARG_MIB(0x9520), 0, 0},
- {UIC_ARG_MIB(0x9521), 0, 0},
- {UIC_ARG_MIB(0x9522), 0, 0},
- {UIC_ARG_MIB(0x9523), 0, 0},
- {UIC_ARG_MIB(0x9525), 0, 0},
- {UIC_ARG_MIB(0x9528), 0, 0},
- {UIC_ARG_MIB(0x9529), 0, 0},
- {UIC_ARG_MIB(0x952A), 0, 0},
- {UIC_ARG_MIB(0x952B), 0, 0},
- {UIC_ARG_MIB(0x952C), 0, 0},
- {UIC_ARG_MIB(0x9534), 0, 0},
- {UIC_ARG_MIB(0x9535), 0, 0},
- {UIC_ARG_MIB(0x9536), 0, 0},
- {UIC_ARG_MIB(0x9539), 0, 0},
- {UIC_ARG_MIB(0x9540), 0, 0},
- {UIC_ARG_MIB(0x9541), 0, 0},
- {UIC_ARG_MIB(0x9542), 0, 0},
- {UIC_ARG_MIB(0x9543), 0, 0},
- {UIC_ARG_MIB(0x9546), 0, 0},
- {UIC_ARG_MIB(0x9551), 0, 0},
- {UIC_ARG_MIB(0x9552), 0, 0},
- {UIC_ARG_MIB(0x9554), 0, 0},
- {UIC_ARG_MIB(0x9556), 0, 0},
- {UIC_ARG_MIB(0x9557), 0, 0},
- {UIC_ARG_MIB(0x9558), 0, 0},
- {UIC_ARG_MIB(0x9559), 0, 0},
- {UIC_ARG_MIB(0x9560), 0, 0},
- {UIC_ARG_MIB(0x9561), 0, 0},
- {UIC_ARG_MIB(0x9562), 0, 0},
- {UIC_ARG_MIB(0x9563), 0, 0},
- {UIC_ARG_MIB(0x9564), 0, 0},
- {UIC_ARG_MIB(0x9565), 0, 0},
- {UIC_ARG_MIB(0x9566), 0, 0},
- {UIC_ARG_MIB(0x9567), 0, 0},
- {UIC_ARG_MIB(0x9568), 0, 0},
- {UIC_ARG_MIB(0x9569), 0, 0},
- {UIC_ARG_MIB(0x9570), 0, 0},
- {UIC_ARG_MIB(0x9571), 0, 0},
- {UIC_ARG_MIB(0x9572), 0, 0},
- {UIC_ARG_MIB(0x9573), 0, 0},
+
/* DL Standard */
{UIC_ARG_MIB(0x2002), 0, 0},
{UIC_ARG_MIB(0x2003), 0, 0},
{UIC_ARG_MIB(0x2065), 0, 0},
{UIC_ARG_MIB(0x2066), 0, 0},
{UIC_ARG_MIB(0x2067), 0, 0},
+
/* DL Debug */
- {UIC_ARG_MIB(0xA000), 0, 0},
- {UIC_ARG_MIB(0xA003), 0, 0},
- {UIC_ARG_MIB(0xA004), 0, 0},
- {UIC_ARG_MIB(0xA005), 0, 0},
- {UIC_ARG_MIB(0xA006), 0, 0},
- {UIC_ARG_MIB(0xA007), 0, 0},
- {UIC_ARG_MIB(0xA009), 0, 0},
- {UIC_ARG_MIB(0xA010), 0, 0},
- {UIC_ARG_MIB(0xA011), 0, 0},
- {UIC_ARG_MIB(0xA012), 0, 0},
- {UIC_ARG_MIB(0xA013), 0, 0},
- {UIC_ARG_MIB(0xA014), 0, 0},
- {UIC_ARG_MIB(0xA015), 0, 0},
- {UIC_ARG_MIB(0xA016), 0, 0},
- {UIC_ARG_MIB(0xA020), 0, 0},
- {UIC_ARG_MIB(0xA021), 0, 0},
- {UIC_ARG_MIB(0xA022), 0, 0},
- {UIC_ARG_MIB(0xA023), 0, 0},
- {UIC_ARG_MIB(0xA024), 0, 0},
- {UIC_ARG_MIB(0xA025), 0, 0},
- {UIC_ARG_MIB(0xA026), 0, 0},
- {UIC_ARG_MIB(0xA027), 0, 0},
- {UIC_ARG_MIB(0xA028), 0, 0},
- {UIC_ARG_MIB(0xA029), 0, 0},
- {UIC_ARG_MIB(0xA02A), 0, 0},
- {UIC_ARG_MIB(0xA02B), 0, 0},
- {UIC_ARG_MIB(0xA02C), 0, 0},
- {UIC_ARG_MIB(0xA02D), 0, 0},
- {UIC_ARG_MIB(0xA02E), 0, 0},
- {UIC_ARG_MIB(0xA02F), 0, 0},
- {UIC_ARG_MIB(0xA030), 0, 0},
- {UIC_ARG_MIB(0xA031), 0, 0},
- {UIC_ARG_MIB(0xA041), 0, 0},
- {UIC_ARG_MIB(0xA042), 0, 0},
- {UIC_ARG_MIB(0xA043), 0, 0},
- {UIC_ARG_MIB(0xA044), 0, 0},
- {UIC_ARG_MIB(0xA045), 0, 0},
- {UIC_ARG_MIB(0xA046), 0, 0},
- {UIC_ARG_MIB(0xA047), 0, 0},
- {UIC_ARG_MIB(0xA060), 0, 0},
- {UIC_ARG_MIB(0xA061), 0, 0},
- {UIC_ARG_MIB(0xA062), 0, 0},
- {UIC_ARG_MIB(0xA063), 0, 0},
- {UIC_ARG_MIB(0xA064), 0, 0},
- {UIC_ARG_MIB(0xA065), 0, 0},
- {UIC_ARG_MIB(0xA066), 0, 0},
- {UIC_ARG_MIB(0xA067), 0, 0},
- {UIC_ARG_MIB(0xA068), 0, 0},
- {UIC_ARG_MIB(0xA069), 0, 0},
- {UIC_ARG_MIB(0xA06A), 0, 0},
- {UIC_ARG_MIB(0xA06B), 0, 0},
- {UIC_ARG_MIB(0xA06C), 0, 0},
- {UIC_ARG_MIB(0xA080), 0, 0},
+
/* NL Standard */
{UIC_ARG_MIB(0x3000), 0, 0},
{UIC_ARG_MIB(0x3001), 0, 0},
{UIC_ARG_MIB(0x4023), 0, 0},
{UIC_ARG_MIB(0x4025), 0, 0},
{UIC_ARG_MIB(0x402B), 0, 0},
- /* MPHY */
+
+ /* MPHY PCS Lane 0 Standard*/
{UIC_ARG_MIB(0x0021), 0, 0},
{UIC_ARG_MIB(0x0022), 0, 0},
{UIC_ARG_MIB(0x0023), 0, 0},
{UIC_ARG_MIB(0x0035), 0, 0},
{UIC_ARG_MIB(0x0036), 0, 0},
{UIC_ARG_MIB(0x0041), 0, 0},
+
{UIC_ARG_MIB(0x00A1), 0, 0},
{UIC_ARG_MIB(0x00A2), 0, 0},
{UIC_ARG_MIB(0x00A3), 0, 0},
{UIC_ARG_MIB(0x00A4), 0, 0},
{UIC_ARG_MIB(0x00A7), 0, 0},
{UIC_ARG_MIB(0x00C1), 0, 0},
- {UIC_ARG_MIB(0x029b), 0, 0},
- {UIC_ARG_MIB(0x035d), 0, 0},
- {UIC_ARG_MIB(0x028B), 0, 0},
- {UIC_ARG_MIB(0x029A), 0, 0},
- {UIC_ARG_MIB(0x0277), 0, 0},
{},
};
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff