drm/i915/gen10: Set value of Indirect Context Offset for gen10

Indirect Context Offset Pointer has changed for Cannonlake.

INDIRECT_CTX_OFFSET[15:6] valid value for CNL is 19h per Spec.

v2: rebased to intel_lr_indirect_ctx_offset

v3: Commit message added per Tvrtko request.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1496781040-20888-9-git-send-email-rodrigo.vivi@intel.com

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 014b30ace8a0af394960d4a8ed259dc712758b52..d49dbaa931b5ea075319e0fb13600a2bf624dcbd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -204,6 +204,7 @@
 
 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT       0x17
 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT       0x26
+#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT      0x19
 
 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
@@ -1861,6 +1862,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
        default:
                MISSING_CASE(INTEL_GEN(engine->i915));
                /* fall through */
+       case 10:
+               indirect_ctx_offset =
+                       GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
+               break;
        case 9:
                indirect_ctx_offset =
                        GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;