clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE

Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 4ee6d03bc575fa485f196b6fdd5905dcaf88a674..eaab060cda2425dcb9c44b391a7afb926a3843d7 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -108,6 +108,9 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
        if (!(pll->flags & TEGRA_PLL_USE_LOCK))
                return;
 
+       if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
+               return;
+
        val = pll_readl_misc(pll);
        val |= BIT(pll->params->lock_enable_bit_idx);
        pll_writel_misc(val, pll);
@@ -675,6 +678,7 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
        struct clk *clk;
 
        pll_flags |= TEGRA_PLL_BYPASS;
+       pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
                              freq_table, lock);
        if (IS_ERR(pll))
@@ -698,6 +702,7 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
        struct clk *clk;
 
        pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
+       pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
                              freq_table, lock);
        if (IS_ERR(pll))

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index fff520ae72fcd376fdd566daa946173332b4bbac..17ddb22f7a5083ecdebb64c17c86459e81ee39db 100644 (file)
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -185,6 +185,7 @@ struct tegra_clk_pll_params {
  * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
  *     base register.
  * TEGRA_PLL_BYPASS - PLL has bypass bit
+ * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
  */
 struct tegra_clk_pll {
        struct clk_hw   hw;
@@ -215,6 +216,7 @@ struct tegra_clk_pll {
 #define TEGRA_PLLE_CONFIGURE BIT(7)
 #define TEGRA_PLL_LOCK_MISC BIT(8)
 #define TEGRA_PLL_BYPASS BIT(9)
+#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
 
 extern const struct clk_ops tegra_clk_pll_ops;
 extern const struct clk_ops tegra_clk_plle_ops;