ARM: dts: uniphier: fix size of sdctrl nodes

All registers are located within 0x400 size from the base address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 41a6493ed29a86c8953428e08aa54abb0447d2da..b026bcd42a069351b1786959be0af090eaef21d3 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -292,7 +292,7 @@
                sdctrl@59810000 {
                        compatible = "socionext,uniphier-pro5-sdctrl",
                                     "simple-mfd", "syscon";
-                       reg = <0x59810000 0x800>;
+                       reg = <0x59810000 0x400>;
 
                        sd_clk: clock {
                                compatible = "socionext,uniphier-pro5-sd-clock";

diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 37bbaa4b4de5527e5b7703c9a32341a103023b09..90b020c950837d5d0c9d2a43d74d4a2c208b7463 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -276,7 +276,7 @@
                sdctrl@59810000 {
                        compatible = "socionext,uniphier-pxs2-sdctrl",
                                     "simple-mfd", "syscon";
-                       reg = <0x59810000 0x800>;
+                       reg = <0x59810000 0x400>;
 
                        sd_clk: clock {
                                compatible = "socionext,uniphier-pxs2-sd-clock";