media: stm32-dcmi: revisit control register handling

Simplify bits handling of DCMI_CR register.

Signed-off-by: Hugues Fruchet <hugues.fruchet@st.com>
Signed-off-by: Hans Verkuil <hansverk@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>

diff --git a/drivers/media/platform/stm32/stm32-dcmi.c b/drivers/media/platform/stm32/stm32-dcmi.c
index 7ffb2d3e99be679ff47c6d17c48b237764c71898..1fe2d0f0f5de74988401845be1cd670c0201e5ee 100644 (file)
--- a/drivers/media/platform/stm32/stm32-dcmi.c
+++ b/drivers/media/platform/stm32/stm32-dcmi.c
@@ -490,7 +490,7 @@ static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count)
 {
        struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
        struct dcmi_buf *buf, *node;
-       u32 val;
+       u32 val = 0;
        int ret;
 
        ret = clk_enable(dcmi->mclk);
@@ -510,22 +510,16 @@ static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count)
 
        spin_lock_irq(&dcmi->irqlock);
 
-       val = reg_read(dcmi->regs, DCMI_CR);
-
-       val &= ~(CR_PCKPOL | CR_HSPOL | CR_VSPOL |
-                CR_EDM_0 | CR_EDM_1 | CR_FCRC_0 |
-                CR_FCRC_1 | CR_JPEG | CR_ESS);
-
        /* Set bus width */
        switch (dcmi->bus.bus_width) {
        case 14:
-               val &= CR_EDM_0 + CR_EDM_1;
+               val |= CR_EDM_0 | CR_EDM_1;
                break;
        case 12:
-               val &= CR_EDM_1;
+               val |= CR_EDM_1;
                break;
        case 10:
-               val &= CR_EDM_0;
+               val |= CR_EDM_0;
                break;
        default:
                /* Set bus width to 8 bits by default */