iwlwifi: fix rf configuration
authorEmmanuel Grumbach <emmanuel.grumbach@intel.com>
Tue, 29 May 2012 14:30:43 +0000 (17:30 +0300)
committerJohannes Berg <johannes.berg@intel.com>
Wed, 6 Jun 2012 11:22:11 +0000 (13:22 +0200)
Johannes noticed this was completely messed up.
We got confused between masks and bit position.

Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
drivers/net/wireless/iwlwifi/dvm/eeprom.c
drivers/net/wireless/iwlwifi/iwl-csr.h

index b4da76d5d97e62c243e085257db41348152198e5..b382b16b89d7da1fa21be4f3f5981ccf47a03bdc 100644 (file)
@@ -1136,10 +1136,19 @@ void iwl_rf_config(struct iwl_priv *priv)
 
        /* write radio config values to register */
        if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
-               iwl_set_bit(priv->trans, CSR_HW_IF_CONFIG_REG,
-                           EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
-                           EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
-                           EEPROM_RF_CFG_DASH_MSK(radio_cfg));
+               u32 reg_val =
+                       EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <<
+                               CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE |
+                       EEPROM_RF_CFG_STEP_MSK(radio_cfg) <<
+                               CSR_HW_IF_CONFIG_REG_POS_PHY_STEP |
+                       EEPROM_RF_CFG_DASH_MSK(radio_cfg) <<
+                               CSR_HW_IF_CONFIG_REG_POS_PHY_DASH;
+
+               iwl_set_bits_mask(priv->trans, CSR_HW_IF_CONFIG_REG,
+                                 CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE |
+                                 CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP |
+                                 CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH, reg_val);
+
                IWL_INFO(priv, "Radio type=0x%x-0x%x-0x%x\n",
                         EEPROM_RF_CFG_TYPE_MSK(radio_cfg),
                         EEPROM_RF_CFG_STEP_MSK(radio_cfg),
index 59750543fce7366ce68ccafa7bfeab2c4e923b54..41dc6911b164252e5c58022704eba393dcfcbf20 100644 (file)
 #define CSR_DBG_LINK_PWR_MGMT_REG      (CSR_BASE+0x250)
 
 /* Bits for CSR_HW_IF_CONFIG_REG */
-#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER     (0x00000C00)
-#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI        (0x00000100)
+#define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH      (0x00000003)
+#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP      (0x0000000C)
+#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER     (0x000000C0)
+#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI                (0x00000100)
 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI      (0x00000200)
+#define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE      (0x00000C00)
+#define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH      (0x00003000)
+#define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP      (0x0000C000)
+
+#define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH      (0)
+#define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP      (2)
+#define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER     (6)
+#define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE      (10)
+#define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH      (12)
+#define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP      (14)
 
 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A  (0x00080000)
 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM        (0x00200000)