Merge branch 'next/dt2' into HEAD
authorOlof Johansson <olof@lixom.net>
Mon, 1 Oct 2012 21:37:01 +0000 (14:37 -0700)
committerOlof Johansson <olof@lixom.net>
Mon, 1 Oct 2012 21:37:01 +0000 (14:37 -0700)
Conflicts:
arch/arm/mach-exynos/clock-exynos5.c

1  2 
arch/arm/boot/dts/exynos5250.dtsi
arch/arm/mach-exynos/clock-exynos5.c
arch/arm/mach-exynos/include/mach/map.h
arch/arm/mach-exynos/mach-exynos5-dt.c

Simple merge
index f3171c3f3d94a9af8ea340704338c8ee3be19053,17e6c77231fa0dbbd6c3ca4d0c16ddfcae335f3f..c44ca1ee1b8d0196de2ac413bad5af226bc83bc9
@@@ -1200,28 -1115,18 +1195,20 @@@ static struct clksrc_clk exynos5_clk_sc
        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
  };
  
 +struct clksrc_clk exynos5_clk_sclk_fimd1 = {
 +      .clk    = {
 +              .name           = "sclk_fimd",
 +              .devname        = "exynos5-fb.1",
 +              .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 +              .ctrlbit        = (1 << 0),
 +      },
 +      .sources = &exynos5_clkset_group,
 +      .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
 +      .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
 +};
 +
  static struct clksrc_clk exynos5_clksrcs[] = {
        {
--              .clk    = {
-                       .name           = "sclk_dwmci",
-                       .parent         = &exynos5_clk_dout_mmc4.clk,
-                       .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 16),
 -                      .name           = "sclk_fimd",
 -                      .devname        = "s3cfb.1",
 -                      .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 -                      .ctrlbit        = (1 << 0),
--              },
-               .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
 -              .sources = &exynos5_clkset_group,
 -              .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
 -              .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
--      }, {
                .clk    = {
                        .name           = "aclk_266_gscl",
                },