drm/radeon: make all functions work with multiple rings.
authorChristian König <deathsimple@vodafone.de>
Fri, 23 Sep 2011 13:11:23 +0000 (15:11 +0200)
committerDave Airlie <airlied@redhat.com>
Tue, 20 Dec 2011 19:49:46 +0000 (19:49 +0000)
Give all asic and radeon_ring_* functions a
radeon_cp parameter, so they know the ring to work with.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
20 files changed:
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/evergreen_blit_kms.c
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r200.c
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r420.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600_blit_kms.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_cs.c
drivers/gpu/drm/radeon/radeon_fence.c
drivers/gpu/drm/radeon/radeon_gem.c
drivers/gpu/drm/radeon/radeon_pm.c
drivers/gpu/drm/radeon/radeon_ring.c
drivers/gpu/drm/radeon/radeon_semaphore.c
drivers/gpu/drm/radeon/radeon_test.c
drivers/gpu/drm/radeon/rv515.c
drivers/gpu/drm/radeon/rv770.c

index 233cbc0a2b59390686ec05238d434cf1ec652fac..fa11a04ae62e4d9ad4cf6fa6338e632424080994 100644 (file)
@@ -1311,18 +1311,20 @@ void evergreen_mc_program(struct radeon_device *rdev)
  */
 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 {
+       struct radeon_cp *cp = &rdev->cp;
+
        /* set to DX10/11 mode */
-       radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
-       radeon_ring_write(rdev, 1);
+       radeon_ring_write(cp, PACKET3(PACKET3_MODE_CONTROL, 0));
+       radeon_ring_write(cp, 1);
        /* FIXME: implement */
-       radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+       radeon_ring_write(cp,
 #ifdef __BIG_ENDIAN
                          (2 << 0) |
 #endif
                          (ib->gpu_addr & 0xFFFFFFFC));
-       radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
-       radeon_ring_write(rdev, ib->length_dw);
+       radeon_ring_write(cp, upper_32_bits(ib->gpu_addr) & 0xFF);
+       radeon_ring_write(cp, ib->length_dw);
 }
 
 
@@ -1360,71 +1362,73 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev)
 
 static int evergreen_cp_start(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r, i;
        uint32_t cp_me;
 
-       r = radeon_ring_lock(rdev, 7);
+       r = radeon_ring_lock(rdev, cp, 7);
        if (r) {
                DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
                return r;
        }
-       radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
-       radeon_ring_write(rdev, 0x1);
-       radeon_ring_write(rdev, 0x0);
-       radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
-       radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_write(cp, PACKET3(PACKET3_ME_INITIALIZE, 5));
+       radeon_ring_write(cp, 0x1);
+       radeon_ring_write(cp, 0x0);
+       radeon_ring_write(cp, rdev->config.evergreen.max_hw_contexts - 1);
+       radeon_ring_write(cp, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_unlock_commit(rdev, cp);
 
        cp_me = 0xff;
        WREG32(CP_ME_CNTL, cp_me);
 
-       r = radeon_ring_lock(rdev, evergreen_default_size + 19);
+       r = radeon_ring_lock(rdev, cp, evergreen_default_size + 19);
        if (r) {
                DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
                return r;
        }
 
        /* setup clear context state */
-       radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
-       radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
+       radeon_ring_write(cp, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
+       radeon_ring_write(cp, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 
        for (i = 0; i < evergreen_default_size; i++)
-               radeon_ring_write(rdev, evergreen_default_state[i]);
+               radeon_ring_write(cp, evergreen_default_state[i]);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
-       radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
+       radeon_ring_write(cp, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
+       radeon_ring_write(cp, PACKET3_PREAMBLE_END_CLEAR_STATE);
 
        /* set clear context state */
-       radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_CLEAR_STATE, 0));
+       radeon_ring_write(cp, 0);
 
        /* SQ_VTX_BASE_VTX_LOC */
-       radeon_ring_write(rdev, 0xc0026f00);
-       radeon_ring_write(rdev, 0x00000000);
-       radeon_ring_write(rdev, 0x00000000);
-       radeon_ring_write(rdev, 0x00000000);
+       radeon_ring_write(cp, 0xc0026f00);
+       radeon_ring_write(cp, 0x00000000);
+       radeon_ring_write(cp, 0x00000000);
+       radeon_ring_write(cp, 0x00000000);
 
        /* Clear consts */
-       radeon_ring_write(rdev, 0xc0036f00);
-       radeon_ring_write(rdev, 0x00000bc4);
-       radeon_ring_write(rdev, 0xffffffff);
-       radeon_ring_write(rdev, 0xffffffff);
-       radeon_ring_write(rdev, 0xffffffff);
+       radeon_ring_write(cp, 0xc0036f00);
+       radeon_ring_write(cp, 0x00000bc4);
+       radeon_ring_write(cp, 0xffffffff);
+       radeon_ring_write(cp, 0xffffffff);
+       radeon_ring_write(cp, 0xffffffff);
 
-       radeon_ring_write(rdev, 0xc0026900);
-       radeon_ring_write(rdev, 0x00000316);
-       radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
-       radeon_ring_write(rdev, 0x00000010); /*  */
+       radeon_ring_write(cp, 0xc0026900);
+       radeon_ring_write(cp, 0x00000316);
+       radeon_ring_write(cp, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
+       radeon_ring_write(cp, 0x00000010); /*  */
 
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_unlock_commit(rdev, cp);
 
        return 0;
 }
 
 int evergreen_cp_resume(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 tmp;
        u32 rb_bufsz;
        int r;
@@ -1442,7 +1446,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
        RREG32(GRBM_SOFT_RESET);
 
        /* Set ring buffer size */
-       rb_bufsz = drm_order(rdev->cp.ring_size / 8);
+       rb_bufsz = drm_order(cp->ring_size / 8);
        tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 #ifdef __BIG_ENDIAN
        tmp |= BUF_SWAP_32BIT;
@@ -1456,8 +1460,8 @@ int evergreen_cp_resume(struct radeon_device *rdev)
        /* Initialize the ring buffer's read and write pointers */
        WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
        WREG32(CP_RB_RPTR_WR, 0);
-       rdev->cp.wptr = 0;
-       WREG32(CP_RB_WPTR, rdev->cp.wptr);
+       cp->wptr = 0;
+       WREG32(CP_RB_WPTR, cp->wptr);
 
        /* set the wb address wether it's enabled or not */
        WREG32(CP_RB_RPTR_ADDR,
@@ -1475,16 +1479,16 @@ int evergreen_cp_resume(struct radeon_device *rdev)
        mdelay(1);
        WREG32(CP_RB_CNTL, tmp);
 
-       WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
+       WREG32(CP_RB_BASE, cp->gpu_addr >> 8);
        WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
 
-       rdev->cp.rptr = RREG32(CP_RB_RPTR);
+       cp->rptr = RREG32(CP_RB_RPTR);
 
        evergreen_cp_start(rdev);
-       rdev->cp.ready = true;
-       r = radeon_ring_test(rdev);
+       cp->ready = true;
+       r = radeon_ring_test(rdev, cp);
        if (r) {
-               rdev->cp.ready = false;
+               cp->ready = false;
                return r;
        }
        return 0;
@@ -2353,7 +2357,7 @@ int evergreen_mc_init(struct radeon_device *rdev)
        return 0;
 }
 
-bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
+bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        u32 srbm_status;
        u32 grbm_status;
@@ -2366,19 +2370,19 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
        grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
        grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
        if (!(grbm_status & GUI_ACTIVE)) {
-               r100_gpu_lockup_update(lockup, &rdev->cp);
+               r100_gpu_lockup_update(lockup, cp);
                return false;
        }
        /* force CP activities */
-       r = radeon_ring_lock(rdev, 2);
+       r = radeon_ring_lock(rdev, cp, 2);
        if (!r) {
                /* PACKET2 NOP */
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_unlock_commit(rdev);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_unlock_commit(rdev, cp);
        }
-       rdev->cp.rptr = RREG32(CP_RB_RPTR);
-       return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
+       cp->rptr = RREG32(CP_RB_RPTR);
+       return r100_gpu_cp_is_lockup(rdev, lockup, cp);
 }
 
 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
@@ -3052,6 +3056,7 @@ restart_ih:
 
 static int evergreen_startup(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r;
 
        /* enable pcie gen2 link */
@@ -3115,7 +3120,7 @@ static int evergreen_startup(struct radeon_device *rdev)
        }
        evergreen_irq_set(rdev);
 
-       r = radeon_ring_init(rdev, rdev->cp.ring_size);
+       r = radeon_ring_init(rdev, cp, cp->ring_size);
        if (r)
                return r;
        r = evergreen_cp_load_microcode(rdev);
@@ -3150,7 +3155,7 @@ int evergreen_resume(struct radeon_device *rdev)
                return r;
        }
 
-       r = r600_ib_test(rdev);
+       r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
        if (r) {
                DRM_ERROR("radeon: failed testing IB (%d).\n", r);
                return r;
@@ -3162,9 +3167,11 @@ int evergreen_resume(struct radeon_device *rdev)
 
 int evergreen_suspend(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
+
        /* FIXME: we should wait for ring to be empty */
        r700_cp_stop(rdev);
-       rdev->cp.ready = false;
+       cp->ready = false;
        evergreen_irq_suspend(rdev);
        radeon_wb_disable(rdev);
        evergreen_pcie_gart_disable(rdev);
@@ -3244,7 +3251,7 @@ int evergreen_init(struct radeon_device *rdev)
                return r;
 
        rdev->cp.ring_obj = NULL;
-       r600_ring_init(rdev, 1024 * 1024);
+       r600_ring_init(rdev, &rdev->cp, 1024 * 1024);
 
        rdev->ih.ring_obj = NULL;
        r600_ih_ring_init(rdev, 64 * 1024);
@@ -3270,7 +3277,7 @@ int evergreen_init(struct radeon_device *rdev)
                        DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
                        rdev->accel_working = false;
                }
-               r = r600_ib_test(rdev);
+               r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
                if (r) {
                        DRM_ERROR("radeon: failed testing IB (%d).\n", r);
                        rdev->accel_working = false;
index 914e5af84163cc38b9e03e214af13db747b7dd80..75d0a6f0a395c8d59f402b7fdcae3c50a349df48 100644 (file)
@@ -49,6 +49,7 @@ static void
 set_render_target(struct radeon_device *rdev, int format,
                  int w, int h, u64 gpu_addr)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 cb_color_info;
        int pitch, slice;
 
@@ -62,23 +63,23 @@ set_render_target(struct radeon_device *rdev, int format,
        pitch = (w / 8) - 1;
        slice = ((w * h) / 64) - 1;
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
-       radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
-       radeon_ring_write(rdev, gpu_addr >> 8);
-       radeon_ring_write(rdev, pitch);
-       radeon_ring_write(rdev, slice);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, cb_color_info);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
+       radeon_ring_write(cp, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
+       radeon_ring_write(cp, gpu_addr >> 8);
+       radeon_ring_write(cp, pitch);
+       radeon_ring_write(cp, slice);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, cb_color_info);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, (w - 1) | ((h - 1) << 16));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
 }
 
 /* emits 5dw */
@@ -87,6 +88,7 @@ cp_set_surface_sync(struct radeon_device *rdev,
                    u32 sync_type, u32 size,
                    u64 mc_addr)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 cp_coher_size;
 
        if (size == 0xffffffff)
@@ -99,39 +101,40 @@ cp_set_surface_sync(struct radeon_device *rdev,
                 * to the RB directly. For IBs, the CP programs this as part of the
                 * surface_sync packet.
                 */
-               radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-               radeon_ring_write(rdev, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
-               radeon_ring_write(rdev, 0); /* CP_COHER_CNTL2 */
+               radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+               radeon_ring_write(cp, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
+               radeon_ring_write(cp, 0); /* CP_COHER_CNTL2 */
        }
-       radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
-       radeon_ring_write(rdev, sync_type);
-       radeon_ring_write(rdev, cp_coher_size);
-       radeon_ring_write(rdev, mc_addr >> 8);
-       radeon_ring_write(rdev, 10); /* poll interval */
+       radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
+       radeon_ring_write(cp, sync_type);
+       radeon_ring_write(cp, cp_coher_size);
+       radeon_ring_write(cp, mc_addr >> 8);
+       radeon_ring_write(cp, 10); /* poll interval */
 }
 
 /* emits 11dw + 1 surface sync = 16dw */
 static void
 set_shaders(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u64 gpu_addr;
 
        /* VS */
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
-       radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
-       radeon_ring_write(rdev, gpu_addr >> 8);
-       radeon_ring_write(rdev, 2);
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
+       radeon_ring_write(cp, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
+       radeon_ring_write(cp, gpu_addr >> 8);
+       radeon_ring_write(cp, 2);
+       radeon_ring_write(cp, 0);
 
        /* PS */
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
-       radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
-       radeon_ring_write(rdev, gpu_addr >> 8);
-       radeon_ring_write(rdev, 1);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 2);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
+       radeon_ring_write(cp, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
+       radeon_ring_write(cp, gpu_addr >> 8);
+       radeon_ring_write(cp, 1);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 2);
 
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
        cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
@@ -141,6 +144,7 @@ set_shaders(struct radeon_device *rdev)
 static void
 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
 
        /* high addr, stride */
@@ -155,16 +159,16 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
                SQ_VTCX_SEL_Z(SQ_SEL_Z) |
                SQ_VTCX_SEL_W(SQ_SEL_W);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
-       radeon_ring_write(rdev, 0x580);
-       radeon_ring_write(rdev, gpu_addr & 0xffffffff);
-       radeon_ring_write(rdev, 48 - 1); /* size */
-       radeon_ring_write(rdev, sq_vtx_constant_word2);
-       radeon_ring_write(rdev, sq_vtx_constant_word3);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 8));
+       radeon_ring_write(cp, 0x580);
+       radeon_ring_write(cp, gpu_addr & 0xffffffff);
+       radeon_ring_write(cp, 48 - 1); /* size */
+       radeon_ring_write(cp, sq_vtx_constant_word2);
+       radeon_ring_write(cp, sq_vtx_constant_word3);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
 
        if ((rdev->family == CHIP_CEDAR) ||
            (rdev->family == CHIP_PALM) ||
@@ -185,6 +189,7 @@ set_tex_resource(struct radeon_device *rdev,
                 int format, int w, int h, int pitch,
                 u64 gpu_addr, u32 size)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 sq_tex_resource_word0, sq_tex_resource_word1;
        u32 sq_tex_resource_word4, sq_tex_resource_word7;
 
@@ -208,16 +213,16 @@ set_tex_resource(struct radeon_device *rdev,
        cp_set_surface_sync(rdev,
                            PACKET3_TC_ACTION_ENA, size, gpu_addr);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, sq_tex_resource_word0);
-       radeon_ring_write(rdev, sq_tex_resource_word1);
-       radeon_ring_write(rdev, gpu_addr >> 8);
-       radeon_ring_write(rdev, gpu_addr >> 8);
-       radeon_ring_write(rdev, sq_tex_resource_word4);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, sq_tex_resource_word7);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 8));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, sq_tex_resource_word0);
+       radeon_ring_write(cp, sq_tex_resource_word1);
+       radeon_ring_write(cp, gpu_addr >> 8);
+       radeon_ring_write(cp, gpu_addr >> 8);
+       radeon_ring_write(cp, sq_tex_resource_word4);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, sq_tex_resource_word7);
 }
 
 /* emits 12 */
@@ -225,6 +230,7 @@ static void
 set_scissors(struct radeon_device *rdev, int x1, int y1,
             int x2, int y2)
 {
+       struct radeon_cp *cp = &rdev->cp;
        /* workaround some hw bugs */
        if (x2 == 0)
                x1 = 1;
@@ -235,43 +241,44 @@ set_scissors(struct radeon_device *rdev, int x1, int y1,
                        x2 = 2;
        }
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
-       radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
-       radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
-       radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+       radeon_ring_write(cp, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
+       radeon_ring_write(cp, (x1 << 0) | (y1 << 16));
+       radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
-       radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
-       radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
-       radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+       radeon_ring_write(cp, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
+       radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
+       radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
-       radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
-       radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
-       radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+       radeon_ring_write(cp, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
+       radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
+       radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
 }
 
 /* emits 10 */
 static void
 draw_auto(struct radeon_device *rdev)
 {
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-       radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
-       radeon_ring_write(rdev, DI_PT_RECTLIST);
+       struct radeon_cp *cp = &rdev->cp;
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+       radeon_ring_write(cp, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
+       radeon_ring_write(cp, DI_PT_RECTLIST);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET3(PACKET3_INDEX_TYPE, 0));
+       radeon_ring_write(cp,
 #ifdef __BIG_ENDIAN
                          (2 << 2) |
 #endif
                          DI_INDEX_SIZE_16_BIT);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
-       radeon_ring_write(rdev, 1);
+       radeon_ring_write(cp, PACKET3(PACKET3_NUM_INSTANCES, 0));
+       radeon_ring_write(cp, 1);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
-       radeon_ring_write(rdev, 3);
-       radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
+       radeon_ring_write(cp, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
+       radeon_ring_write(cp, 3);
+       radeon_ring_write(cp, DI_SRC_SEL_AUTO_INDEX);
 
 }
 
@@ -279,6 +286,7 @@ draw_auto(struct radeon_device *rdev)
 static void
 set_default_state(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
        u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
        u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
@@ -292,8 +300,8 @@ set_default_state(struct radeon_device *rdev)
        int dwords;
 
        /* set clear context state */
-       radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_CLEAR_STATE, 0));
+       radeon_ring_write(cp, 0);
 
        if (rdev->family < CHIP_CAYMAN) {
                switch (rdev->family) {
@@ -550,60 +558,60 @@ set_default_state(struct radeon_device *rdev)
                                            NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
 
                /* disable dyn gprs */
-               radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-               radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
-               radeon_ring_write(rdev, 0);
+               radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+               radeon_ring_write(cp, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
+               radeon_ring_write(cp, 0);
 
                /* setup LDS */
-               radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-               radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
-               radeon_ring_write(rdev, 0x10001000);
+               radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+               radeon_ring_write(cp, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
+               radeon_ring_write(cp, 0x10001000);
 
                /* SQ config */
-               radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
-               radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
-               radeon_ring_write(rdev, sq_config);
-               radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
-               radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
-               radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
-               radeon_ring_write(rdev, 0);
-               radeon_ring_write(rdev, 0);
-               radeon_ring_write(rdev, sq_thread_resource_mgmt);
-               radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
-               radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
-               radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
-               radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
+               radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 11));
+               radeon_ring_write(cp, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
+               radeon_ring_write(cp, sq_config);
+               radeon_ring_write(cp, sq_gpr_resource_mgmt_1);
+               radeon_ring_write(cp, sq_gpr_resource_mgmt_2);
+               radeon_ring_write(cp, sq_gpr_resource_mgmt_3);
+               radeon_ring_write(cp, 0);
+               radeon_ring_write(cp, 0);
+               radeon_ring_write(cp, sq_thread_resource_mgmt);
+               radeon_ring_write(cp, sq_thread_resource_mgmt_2);
+               radeon_ring_write(cp, sq_stack_resource_mgmt_1);
+               radeon_ring_write(cp, sq_stack_resource_mgmt_2);
+               radeon_ring_write(cp, sq_stack_resource_mgmt_3);
        }
 
        /* CONTEXT_CONTROL */
-       radeon_ring_write(rdev, 0xc0012800);
-       radeon_ring_write(rdev, 0x80000000);
-       radeon_ring_write(rdev, 0x80000000);
+       radeon_ring_write(cp, 0xc0012800);
+       radeon_ring_write(cp, 0x80000000);
+       radeon_ring_write(cp, 0x80000000);
 
        /* SQ_VTX_BASE_VTX_LOC */
-       radeon_ring_write(rdev, 0xc0026f00);
-       radeon_ring_write(rdev, 0x00000000);
-       radeon_ring_write(rdev, 0x00000000);
-       radeon_ring_write(rdev, 0x00000000);
+       radeon_ring_write(cp, 0xc0026f00);
+       radeon_ring_write(cp, 0x00000000);
+       radeon_ring_write(cp, 0x00000000);
+       radeon_ring_write(cp, 0x00000000);
 
        /* SET_SAMPLER */
-       radeon_ring_write(rdev, 0xc0036e00);
-       radeon_ring_write(rdev, 0x00000000);
-       radeon_ring_write(rdev, 0x00000012);
-       radeon_ring_write(rdev, 0x00000000);
-       radeon_ring_write(rdev, 0x00000000);
+       radeon_ring_write(cp, 0xc0036e00);
+       radeon_ring_write(cp, 0x00000000);
+       radeon_ring_write(cp, 0x00000012);
+       radeon_ring_write(cp, 0x00000000);
+       radeon_ring_write(cp, 0x00000000);
 
        /* set to DX10/11 mode */
-       radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
-       radeon_ring_write(rdev, 1);
+       radeon_ring_write(cp, PACKET3(PACKET3_MODE_CONTROL, 0));
+       radeon_ring_write(cp, 1);
 
        /* emit an IB pointing at default state */
        dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
-       radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
-       radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
-       radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
-       radeon_ring_write(rdev, dwords);
+       radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+       radeon_ring_write(cp, gpu_addr & 0xFFFFFFFC);
+       radeon_ring_write(cp, upper_32_bits(gpu_addr) & 0xFF);
+       radeon_ring_write(cp, dwords);
 
 }
 
index ef749950db08f310b275b037c53325aafc0fdf84..636b8c5f57976194a7c115009398f943f43bc5dc 100644 (file)
@@ -1049,63 +1049,64 @@ static int cayman_cp_load_microcode(struct radeon_device *rdev)
 
 static int cayman_cp_start(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r, i;
 
-       r = radeon_ring_lock(rdev, 7);
+       r = radeon_ring_lock(rdev, cp, 7);
        if (r) {
                DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
                return r;
        }
-       radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
-       radeon_ring_write(rdev, 0x1);
-       radeon_ring_write(rdev, 0x0);
-       radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1);
-       radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_write(cp, PACKET3(PACKET3_ME_INITIALIZE, 5));
+       radeon_ring_write(cp, 0x1);
+       radeon_ring_write(cp, 0x0);
+       radeon_ring_write(cp, rdev->config.cayman.max_hw_contexts - 1);
+       radeon_ring_write(cp, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_unlock_commit(rdev, cp);
 
        cayman_cp_enable(rdev, true);
 
-       r = radeon_ring_lock(rdev, cayman_default_size + 19);
+       r = radeon_ring_lock(rdev, cp, cayman_default_size + 19);
        if (r) {
                DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
                return r;
        }
 
        /* setup clear context state */
-       radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
-       radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
+       radeon_ring_write(cp, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
+       radeon_ring_write(cp, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 
        for (i = 0; i < cayman_default_size; i++)
-               radeon_ring_write(rdev, cayman_default_state[i]);
+               radeon_ring_write(cp, cayman_default_state[i]);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
-       radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
+       radeon_ring_write(cp, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
+       radeon_ring_write(cp, PACKET3_PREAMBLE_END_CLEAR_STATE);
 
        /* set clear context state */
-       radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_CLEAR_STATE, 0));
+       radeon_ring_write(cp, 0);
 
        /* SQ_VTX_BASE_VTX_LOC */
-       radeon_ring_write(rdev, 0xc0026f00);
-       radeon_ring_write(rdev, 0x00000000);
-       radeon_ring_write(rdev, 0x00000000);
-       radeon_ring_write(rdev, 0x00000000);
+       radeon_ring_write(cp, 0xc0026f00);
+       radeon_ring_write(cp, 0x00000000);
+       radeon_ring_write(cp, 0x00000000);
+       radeon_ring_write(cp, 0x00000000);
 
        /* Clear consts */
-       radeon_ring_write(rdev, 0xc0036f00);
-       radeon_ring_write(rdev, 0x00000bc4);
-       radeon_ring_write(rdev, 0xffffffff);
-       radeon_ring_write(rdev, 0xffffffff);
-       radeon_ring_write(rdev, 0xffffffff);
+       radeon_ring_write(cp, 0xc0036f00);
+       radeon_ring_write(cp, 0x00000bc4);
+       radeon_ring_write(cp, 0xffffffff);
+       radeon_ring_write(cp, 0xffffffff);
+       radeon_ring_write(cp, 0xffffffff);
 
-       radeon_ring_write(rdev, 0xc0026900);
-       radeon_ring_write(rdev, 0x00000316);
-       radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
-       radeon_ring_write(rdev, 0x00000010); /*  */
+       radeon_ring_write(cp, 0xc0026900);
+       radeon_ring_write(cp, 0x00000316);
+       radeon_ring_write(cp, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
+       radeon_ring_write(cp, 0x00000010); /*  */
 
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_unlock_commit(rdev, cp);
 
        /* XXX init other rings */
 
@@ -1115,11 +1116,12 @@ static int cayman_cp_start(struct radeon_device *rdev)
 static void cayman_cp_fini(struct radeon_device *rdev)
 {
        cayman_cp_enable(rdev, false);
-       radeon_ring_fini(rdev);
+       radeon_ring_fini(rdev, &rdev->cp);
 }
 
 int cayman_cp_resume(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp;
        u32 tmp;
        u32 rb_bufsz;
        int r;
@@ -1145,7 +1147,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
 
        /* ring 0 - compute and gfx */
        /* Set ring buffer size */
-       rb_bufsz = drm_order(rdev->cp.ring_size / 8);
+       cp = &rdev->cp;
+       rb_bufsz = drm_order(cp->ring_size / 8);
        tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 #ifdef __BIG_ENDIAN
        tmp |= BUF_SWAP_32BIT;
@@ -1154,8 +1157,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
 
        /* Initialize the ring buffer's read and write pointers */
        WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
-       rdev->cp.wptr = 0;
-       WREG32(CP_RB0_WPTR, rdev->cp.wptr);
+       cp->wptr = 0;
+       WREG32(CP_RB0_WPTR, cp->wptr);
 
        /* set the wb address wether it's enabled or not */
        WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1172,13 +1175,14 @@ int cayman_cp_resume(struct radeon_device *rdev)
        mdelay(1);
        WREG32(CP_RB0_CNTL, tmp);
 
-       WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);
+       WREG32(CP_RB0_BASE, cp->gpu_addr >> 8);
 
-       rdev->cp.rptr = RREG32(CP_RB0_RPTR);
+       cp->rptr = RREG32(CP_RB0_RPTR);
 
        /* ring1  - compute only */
        /* Set ring buffer size */
-       rb_bufsz = drm_order(rdev->cp1.ring_size / 8);
+       cp = &rdev->cp1;
+       rb_bufsz = drm_order(cp->ring_size / 8);
        tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 #ifdef __BIG_ENDIAN
        tmp |= BUF_SWAP_32BIT;
@@ -1187,8 +1191,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
 
        /* Initialize the ring buffer's read and write pointers */
        WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
-       rdev->cp1.wptr = 0;
-       WREG32(CP_RB1_WPTR, rdev->cp1.wptr);
+       cp->wptr = 0;
+       WREG32(CP_RB1_WPTR, cp->wptr);
 
        /* set the wb address wether it's enabled or not */
        WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1197,13 +1201,14 @@ int cayman_cp_resume(struct radeon_device *rdev)
        mdelay(1);
        WREG32(CP_RB1_CNTL, tmp);
 
-       WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);
+       WREG32(CP_RB1_BASE, cp->gpu_addr >> 8);
 
-       rdev->cp1.rptr = RREG32(CP_RB1_RPTR);
+       cp->rptr = RREG32(CP_RB1_RPTR);
 
        /* ring2 - compute only */
        /* Set ring buffer size */
-       rb_bufsz = drm_order(rdev->cp2.ring_size / 8);
+       cp = &rdev->cp2;
+       rb_bufsz = drm_order(cp->ring_size / 8);
        tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 #ifdef __BIG_ENDIAN
        tmp |= BUF_SWAP_32BIT;
@@ -1212,8 +1217,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
 
        /* Initialize the ring buffer's read and write pointers */
        WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
-       rdev->cp2.wptr = 0;
-       WREG32(CP_RB2_WPTR, rdev->cp2.wptr);
+       cp->wptr = 0;
+       WREG32(CP_RB2_WPTR, cp->wptr);
 
        /* set the wb address wether it's enabled or not */
        WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1222,9 +1227,9 @@ int cayman_cp_resume(struct radeon_device *rdev)
        mdelay(1);
        WREG32(CP_RB2_CNTL, tmp);
 
-       WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);
+       WREG32(CP_RB2_BASE, cp->gpu_addr >> 8);
 
-       rdev->cp2.rptr = RREG32(CP_RB2_RPTR);
+       cp->rptr = RREG32(CP_RB2_RPTR);
 
        /* start the rings */
        cayman_cp_start(rdev);
@@ -1232,7 +1237,7 @@ int cayman_cp_resume(struct radeon_device *rdev)
        rdev->cp1.ready = true;
        rdev->cp2.ready = true;
        /* this only test cp0 */
-       r = radeon_ring_test(rdev);
+       r = radeon_ring_test(rdev, &rdev->cp);
        if (r) {
                rdev->cp.ready = false;
                rdev->cp1.ready = false;
@@ -1243,7 +1248,7 @@ int cayman_cp_resume(struct radeon_device *rdev)
        return 0;
 }
 
-bool cayman_gpu_is_lockup(struct radeon_device *rdev)
+bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        u32 srbm_status;
        u32 grbm_status;
@@ -1256,20 +1261,20 @@ bool cayman_gpu_is_lockup(struct radeon_device *rdev)
        grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
        grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
        if (!(grbm_status & GUI_ACTIVE)) {
-               r100_gpu_lockup_update(lockup, &rdev->cp);
+               r100_gpu_lockup_update(lockup, cp);
                return false;
        }
        /* force CP activities */
-       r = radeon_ring_lock(rdev, 2);
+       r = radeon_ring_lock(rdev, cp, 2);
        if (!r) {
                /* PACKET2 NOP */
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_unlock_commit(rdev);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_unlock_commit(rdev, cp);
        }
        /* XXX deal with CP0,1,2 */
-       rdev->cp.rptr = RREG32(CP_RB0_RPTR);
-       return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
+       cp->rptr = RREG32(CP_RB0_RPTR);
+       return r100_gpu_cp_is_lockup(rdev, lockup, cp);
 }
 
 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
@@ -1338,6 +1343,7 @@ int cayman_asic_reset(struct radeon_device *rdev)
 
 static int cayman_startup(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r;
 
        /* enable pcie gen2 link */
@@ -1387,7 +1393,7 @@ static int cayman_startup(struct radeon_device *rdev)
        }
        evergreen_irq_set(rdev);
 
-       r = radeon_ring_init(rdev, rdev->cp.ring_size);
+       r = radeon_ring_init(rdev, cp, cp->ring_size);
        if (r)
                return r;
        r = cayman_cp_load_microcode(rdev);
@@ -1417,7 +1423,7 @@ int cayman_resume(struct radeon_device *rdev)
                return r;
        }
 
-       r = r600_ib_test(rdev);
+       r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
        if (r) {
                DRM_ERROR("radeon: failled testing IB (%d).\n", r);
                return r;
@@ -1448,6 +1454,7 @@ int cayman_suspend(struct radeon_device *rdev)
  */
 int cayman_init(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r;
 
        /* This don't do much */
@@ -1500,8 +1507,8 @@ int cayman_init(struct radeon_device *rdev)
        if (r)
                return r;
 
-       rdev->cp.ring_obj = NULL;
-       r600_ring_init(rdev, 1024 * 1024);
+       cp->ring_obj = NULL;
+       r600_ring_init(rdev, cp, 1024 * 1024);
 
        rdev->ih.ring_obj = NULL;
        r600_ih_ring_init(rdev, 64 * 1024);
@@ -1527,7 +1534,7 @@ int cayman_init(struct radeon_device *rdev)
                        DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
                        rdev->accel_working = false;
                }
-               r = r600_ib_test(rdev);
+               r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
                if (r) {
                        DRM_ERROR("radeon: failed testing IB (%d).\n", r);
                        rdev->accel_working = false;
index 2f18163e5e3252e949acafd270800b74f40e867a..271cee7f817c9e0c59d1c399f31e4787c64d4a0c 100644 (file)
@@ -811,30 +811,33 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 void r100_fence_ring_emit(struct radeon_device *rdev,
                          struct radeon_fence *fence)
 {
+       struct radeon_cp *cp = &rdev->cp;
+
        /* We have to make sure that caches are flushed before
         * CPU might read something from VRAM. */
-       radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
-       radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
+       radeon_ring_write(cp, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, RADEON_RB3D_DC_FLUSH_ALL);
+       radeon_ring_write(cp, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, RADEON_RB3D_ZC_FLUSH_ALL);
        /* Wait until IDLE & CLEAN */
-       radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
-       radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
-       radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
-       radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
+       radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
+       radeon_ring_write(cp, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
+       radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+       radeon_ring_write(cp, rdev->config.r100.hdp_cntl |
                                RADEON_HDP_READ_BUFFER_INVALIDATE);
-       radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
-       radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
+       radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+       radeon_ring_write(cp, rdev->config.r100.hdp_cntl);
        /* Emit fence sequence & fire IRQ */
-       radeon_ring_write(rdev, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
-       radeon_ring_write(rdev, fence->seq);
-       radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
-       radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
+       radeon_ring_write(cp, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
+       radeon_ring_write(cp, fence->seq);
+       radeon_ring_write(cp, PACKET0(RADEON_GEN_INT_STATUS, 0));
+       radeon_ring_write(cp, RADEON_SW_INT_FIRE);
 }
 
 void r100_semaphore_ring_emit(struct radeon_device *rdev,
+                             struct radeon_cp *cp,
                              struct radeon_semaphore *semaphore,
-                             unsigned ring, bool emit_wait)
+                             bool emit_wait)
 {
        /* Unused on older asics, since we don't have semaphores or multiple rings */
        BUG();
@@ -846,6 +849,7 @@ int r100_copy_blit(struct radeon_device *rdev,
                   unsigned num_gpu_pages,
                   struct radeon_fence *fence)
 {
+       struct radeon_cp *cp = &rdev->cp;
        uint32_t cur_pages;
        uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
        uint32_t pitch;
@@ -863,7 +867,7 @@ int r100_copy_blit(struct radeon_device *rdev,
 
        /* Ask for enough room for blit + flush + fence */
        ndw = 64 + (10 * num_loops);
-       r = radeon_ring_lock(rdev, ndw);
+       r = radeon_ring_lock(rdev, cp, ndw);
        if (r) {
                DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
                return -EINVAL;
@@ -877,8 +881,8 @@ int r100_copy_blit(struct radeon_device *rdev,
 
                /* pages are in Y direction - height
                   page width in X direction - width */
-               radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
-               radeon_ring_write(rdev,
+               radeon_ring_write(cp, PACKET3(PACKET3_BITBLT_MULTI, 8));
+               radeon_ring_write(cp,
                                  RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
                                  RADEON_GMC_DST_PITCH_OFFSET_CNTL |
                                  RADEON_GMC_SRC_CLIPPING |
@@ -890,26 +894,26 @@ int r100_copy_blit(struct radeon_device *rdev,
                                  RADEON_DP_SRC_SOURCE_MEMORY |
                                  RADEON_GMC_CLR_CMP_CNTL_DIS |
                                  RADEON_GMC_WR_MSK_DIS);
-               radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
-               radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
-               radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
-               radeon_ring_write(rdev, 0);
-               radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
-               radeon_ring_write(rdev, num_gpu_pages);
-               radeon_ring_write(rdev, num_gpu_pages);
-               radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
-       }
-       radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
-       radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
-       radeon_ring_write(rdev,
+               radeon_ring_write(cp, (pitch << 22) | (src_offset >> 10));
+               radeon_ring_write(cp, (pitch << 22) | (dst_offset >> 10));
+               radeon_ring_write(cp, (0x1fff) | (0x1fff << 16));
+               radeon_ring_write(cp, 0);
+               radeon_ring_write(cp, (0x1fff) | (0x1fff << 16));
+               radeon_ring_write(cp, num_gpu_pages);
+               radeon_ring_write(cp, num_gpu_pages);
+               radeon_ring_write(cp, cur_pages | (stride_pixels << 16));
+       }
+       radeon_ring_write(cp, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, RADEON_RB2D_DC_FLUSH_ALL);
+       radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
+       radeon_ring_write(cp,
                          RADEON_WAIT_2D_IDLECLEAN |
                          RADEON_WAIT_HOST_IDLECLEAN |
                          RADEON_WAIT_DMA_GUI_IDLE);
        if (fence) {
                r = radeon_fence_emit(rdev, fence);
        }
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_unlock_commit(rdev, cp);
        return r;
 }
 
@@ -930,19 +934,20 @@ static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 
 void r100_ring_start(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r;
 
-       r = radeon_ring_lock(rdev, 2);
+       r = radeon_ring_lock(rdev, cp, 2);
        if (r) {
                return;
        }
-       radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(RADEON_ISYNC_CNTL, 0));
+       radeon_ring_write(cp,
                          RADEON_ISYNC_ANY2D_IDLE3D |
                          RADEON_ISYNC_ANY3D_IDLE2D |
                          RADEON_ISYNC_WAIT_IDLEGUI |
                          RADEON_ISYNC_CPSCRATCH_IDLEGUI);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_unlock_commit(rdev, cp);
 }
 
 
@@ -1043,6 +1048,7 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
 
 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 {
+       struct radeon_cp *cp = &rdev->cp;
        unsigned rb_bufsz;
        unsigned rb_blksz;
        unsigned max_fetch;
@@ -1068,7 +1074,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        rb_bufsz = drm_order(ring_size / 8);
        ring_size = (1 << (rb_bufsz + 1)) * 4;
        r100_cp_load_microcode(rdev);
-       r = radeon_ring_init(rdev, ring_size);
+       r = radeon_ring_init(rdev, cp, ring_size);
        if (r) {
                return r;
        }
@@ -1077,7 +1083,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        rb_blksz = 9;
        /* cp will read 128bytes at a time (4 dwords) */
        max_fetch = 1;
-       rdev->cp.align_mask = 16 - 1;
+       cp->align_mask = 16 - 1;
        /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
        pre_write_timer = 64;
        /* Force CP_RB_WPTR write if written more than one time before the
@@ -1107,13 +1113,13 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
 
        /* Set ring address */
-       DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
-       WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
+       DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)cp->gpu_addr);
+       WREG32(RADEON_CP_RB_BASE, cp->gpu_addr);
        /* Force read & write ptr to 0 */
        WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
        WREG32(RADEON_CP_RB_RPTR_WR, 0);
-       rdev->cp.wptr = 0;
-       WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
+       cp->wptr = 0;
+       WREG32(RADEON_CP_RB_WPTR, cp->wptr);
 
        /* set the wb address whether it's enabled or not */
        WREG32(R_00070C_CP_RB_RPTR_ADDR,
@@ -1129,7 +1135,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 
        WREG32(RADEON_CP_RB_CNTL, tmp);
        udelay(10);
-       rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
+       cp->rptr = RREG32(RADEON_CP_RB_RPTR);
        /* Set cp mode to bus mastering & enable cp*/
        WREG32(RADEON_CP_CSQ_MODE,
               REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
@@ -1138,12 +1144,12 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
        WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
        radeon_ring_start(rdev);
-       r = radeon_ring_test(rdev);
+       r = radeon_ring_test(rdev, cp);
        if (r) {
                DRM_ERROR("radeon: cp isn't working (%d).\n", r);
                return r;
        }
-       rdev->cp.ready = true;
+       cp->ready = true;
        radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
        return 0;
 }
@@ -1155,7 +1161,7 @@ void r100_cp_fini(struct radeon_device *rdev)
        }
        /* Disable ring */
        r100_cp_disable(rdev);
-       radeon_ring_fini(rdev);
+       radeon_ring_fini(rdev, &rdev->cp);
        DRM_INFO("radeon: cp finalized\n");
 }
 
@@ -1173,9 +1179,9 @@ void r100_cp_disable(struct radeon_device *rdev)
        }
 }
 
-void r100_cp_commit(struct radeon_device *rdev)
+void r100_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp)
 {
-       WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
+       WREG32(RADEON_CP_RB_WPTR, cp->wptr);
        (void)RREG32(RADEON_CP_RB_WPTR);
 }
 
@@ -2160,26 +2166,26 @@ bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *l
        return false;
 }
 
-bool r100_gpu_is_lockup(struct radeon_device *rdev)
+bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        u32 rbbm_status;
        int r;
 
        rbbm_status = RREG32(R_000E40_RBBM_STATUS);
        if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
-               r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
+               r100_gpu_lockup_update(&rdev->config.r100.lockup, cp);
                return false;
        }
        /* force CP activities */
-       r = radeon_ring_lock(rdev, 2);
+       r = radeon_ring_lock(rdev, cp, 2);
        if (!r) {
                /* PACKET2 NOP */
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_unlock_commit(rdev);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_unlock_commit(rdev, cp);
        }
-       rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
-       return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
+       cp->rptr = RREG32(RADEON_CP_RB_RPTR);
+       return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, cp);
 }
 
 void r100_bm_disable(struct radeon_device *rdev)
@@ -2587,21 +2593,22 @@ static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
        struct drm_info_node *node = (struct drm_info_node *) m->private;
        struct drm_device *dev = node->minor->dev;
        struct radeon_device *rdev = dev->dev_private;
+       struct radeon_cp *cp = &rdev->cp;
        uint32_t rdp, wdp;
        unsigned count, i, j;
 
-       radeon_ring_free_size(rdev);
+       radeon_ring_free_size(rdev, cp);
        rdp = RREG32(RADEON_CP_RB_RPTR);
        wdp = RREG32(RADEON_CP_RB_WPTR);
-       count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
+       count = (rdp + cp->ring_size - wdp) & cp->ptr_mask;
        seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
        seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
        seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
-       seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
+       seq_printf(m, "%u free dwords in ring\n", cp->ring_free_dw);
        seq_printf(m, "%u dwords in ring\n", count);
        for (j = 0; j <= count; j++) {
-               i = (rdp + j) & rdev->cp.ptr_mask;
-               seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
+               i = (rdp + j) & cp->ptr_mask;
+               seq_printf(m, "r[%04d]=0x%08x\n", i, cp->ring[i]);
        }
        return 0;
 }
@@ -3643,7 +3650,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
        }
 }
 
-int r100_ring_test(struct radeon_device *rdev)
+int r100_ring_test(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        uint32_t scratch;
        uint32_t tmp = 0;
@@ -3656,15 +3663,15 @@ int r100_ring_test(struct radeon_device *rdev)
                return r;
        }
        WREG32(scratch, 0xCAFEDEAD);
-       r = radeon_ring_lock(rdev, 2);
+       r = radeon_ring_lock(rdev, cp, 2);
        if (r) {
                DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
                radeon_scratch_free(rdev, scratch);
                return r;
        }
-       radeon_ring_write(rdev, PACKET0(scratch, 0));
-       radeon_ring_write(rdev, 0xDEADBEEF);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_write(cp, PACKET0(scratch, 0));
+       radeon_ring_write(cp, 0xDEADBEEF);
+       radeon_ring_unlock_commit(rdev, cp);
        for (i = 0; i < rdev->usec_timeout; i++) {
                tmp = RREG32(scratch);
                if (tmp == 0xDEADBEEF) {
@@ -3685,9 +3692,11 @@ int r100_ring_test(struct radeon_device *rdev)
 
 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 {
-       radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
-       radeon_ring_write(rdev, ib->gpu_addr);
-       radeon_ring_write(rdev, ib->length_dw);
+       struct radeon_cp *cp = &rdev->cp;
+
+       radeon_ring_write(cp, PACKET0(RADEON_CP_IB_BASE, 1));
+       radeon_ring_write(cp, ib->gpu_addr);
+       radeon_ring_write(cp, ib->length_dw);
 }
 
 int r100_ib_test(struct radeon_device *rdev)
@@ -3704,7 +3713,7 @@ int r100_ib_test(struct radeon_device *rdev)
                return r;
        }
        WREG32(scratch, 0xCAFEDEAD);
-       r = radeon_ib_get(rdev, &ib);
+       r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib);
        if (r) {
                return r;
        }
index a1f3ba063c2dda0de972f363345f815ab76f84d8..d84e633f72fc7a5514bc65bfe13af31e178899fb 100644 (file)
@@ -87,6 +87,7 @@ int r200_copy_dma(struct radeon_device *rdev,
                  unsigned num_gpu_pages,
                  struct radeon_fence *fence)
 {
+       struct radeon_cp *cp = &rdev->cp;
        uint32_t size;
        uint32_t cur_size;
        int i, num_loops;
@@ -95,33 +96,33 @@ int r200_copy_dma(struct radeon_device *rdev,
        /* radeon pitch is /64 */
        size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
        num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
-       r = radeon_ring_lock(rdev, num_loops * 4 + 64);
+       r = radeon_ring_lock(rdev, cp, num_loops * 4 + 64);
        if (r) {
                DRM_ERROR("radeon: moving bo (%d).\n", r);
                return r;
        }
        /* Must wait for 2D idle & clean before DMA or hangs might happen */
-       radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
-       radeon_ring_write(rdev, (1 << 16));
+       radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
+       radeon_ring_write(cp, (1 << 16));
        for (i = 0; i < num_loops; i++) {
                cur_size = size;
                if (cur_size > 0x1FFFFF) {
                        cur_size = 0x1FFFFF;
                }
                size -= cur_size;
-               radeon_ring_write(rdev, PACKET0(0x720, 2));
-               radeon_ring_write(rdev, src_offset);
-               radeon_ring_write(rdev, dst_offset);
-               radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
+               radeon_ring_write(cp, PACKET0(0x720, 2));
+               radeon_ring_write(cp, src_offset);
+               radeon_ring_write(cp, dst_offset);
+               radeon_ring_write(cp, cur_size | (1 << 31) | (1 << 30));
                src_offset += cur_size;
                dst_offset += cur_size;
        }
-       radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
-       radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
+       radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
+       radeon_ring_write(cp, RADEON_WAIT_DMA_GUI_IDLE);
        if (fence) {
                r = radeon_fence_emit(rdev, fence);
        }
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_unlock_commit(rdev, cp);
        return r;
 }
 
index b04731206460bc54ba43c436e24b083822bb2eef..cbb62fc3f2e95454309099d844d72a58b526a314 100644 (file)
@@ -175,37 +175,40 @@ void rv370_pcie_gart_fini(struct radeon_device *rdev)
 void r300_fence_ring_emit(struct radeon_device *rdev,
                          struct radeon_fence *fence)
 {
+       struct radeon_cp *cp = &rdev->cp;
+
        /* Who ever call radeon_fence_emit should call ring_lock and ask
         * for enough space (today caller are ib schedule and buffer move) */
        /* Write SC register so SC & US assert idle */
-       radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET0(R300_RE_SCISSORS_TL, 0));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, PACKET0(R300_RE_SCISSORS_BR, 0));
+       radeon_ring_write(cp, 0);
        /* Flush 3D cache */
-       radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
-       radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, R300_ZC_FLUSH);
+       radeon_ring_write(cp, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, R300_RB3D_DC_FLUSH);
+       radeon_ring_write(cp, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, R300_ZC_FLUSH);
        /* Wait until IDLE & CLEAN */
-       radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
-       radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
+       radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
+       radeon_ring_write(cp, (RADEON_WAIT_3D_IDLECLEAN |
                                 RADEON_WAIT_2D_IDLECLEAN |
                                 RADEON_WAIT_DMA_GUI_IDLE));
-       radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
-       radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
+       radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+       radeon_ring_write(cp, rdev->config.r300.hdp_cntl |
                                RADEON_HDP_READ_BUFFER_INVALIDATE);
-       radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
-       radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
+       radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+       radeon_ring_write(cp, rdev->config.r300.hdp_cntl);
        /* Emit fence sequence & fire IRQ */
-       radeon_ring_write(rdev, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
-       radeon_ring_write(rdev, fence->seq);
-       radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
-       radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
+       radeon_ring_write(cp, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
+       radeon_ring_write(cp, fence->seq);
+       radeon_ring_write(cp, PACKET0(RADEON_GEN_INT_STATUS, 0));
+       radeon_ring_write(cp, RADEON_SW_INT_FIRE);
 }
 
 void r300_ring_start(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        unsigned gb_tile_config;
        int r;
 
@@ -227,44 +230,44 @@ void r300_ring_start(struct radeon_device *rdev)
                break;
        }
 
-       r = radeon_ring_lock(rdev, 64);
+       r = radeon_ring_lock(rdev, cp, 64);
        if (r) {
                return;
        }
-       radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(RADEON_ISYNC_CNTL, 0));
+       radeon_ring_write(cp,
                          RADEON_ISYNC_ANY2D_IDLE3D |
                          RADEON_ISYNC_ANY3D_IDLE2D |
                          RADEON_ISYNC_WAIT_IDLEGUI |
                          RADEON_ISYNC_CPSCRATCH_IDLEGUI);
-       radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
-       radeon_ring_write(rdev, gb_tile_config);
-       radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(R300_GB_TILE_CONFIG, 0));
+       radeon_ring_write(cp, gb_tile_config);
+       radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
+       radeon_ring_write(cp,
                          RADEON_WAIT_2D_IDLECLEAN |
                          RADEON_WAIT_3D_IDLECLEAN);
-       radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
-       radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
-       radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
-       radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
-       radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(R300_DST_PIPE_CONFIG, 0));
+       radeon_ring_write(cp, R300_PIPE_AUTO_CONFIG);
+       radeon_ring_write(cp, PACKET0(R300_GB_SELECT, 0));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, PACKET0(R300_GB_ENABLE, 0));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
+       radeon_ring_write(cp, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, R300_ZC_FLUSH | R300_ZC_FREE);
+       radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
+       radeon_ring_write(cp,
                          RADEON_WAIT_2D_IDLECLEAN |
                          RADEON_WAIT_3D_IDLECLEAN);
-       radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
-       radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
-       radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(R300_GB_AA_CONFIG, 0));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
+       radeon_ring_write(cp, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, R300_ZC_FLUSH | R300_ZC_FREE);
+       radeon_ring_write(cp, PACKET0(R300_GB_MSPOS0, 0));
+       radeon_ring_write(cp,
                          ((6 << R300_MS_X0_SHIFT) |
                           (6 << R300_MS_Y0_SHIFT) |
                           (6 << R300_MS_X1_SHIFT) |
@@ -273,8 +276,8 @@ void r300_ring_start(struct radeon_device *rdev)
                           (6 << R300_MS_Y2_SHIFT) |
                           (6 << R300_MSBD0_Y_SHIFT) |
                           (6 << R300_MSBD0_X_SHIFT)));
-       radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(R300_GB_MSPOS1, 0));
+       radeon_ring_write(cp,
                          ((6 << R300_MS_X3_SHIFT) |
                           (6 << R300_MS_Y3_SHIFT) |
                           (6 << R300_MS_X4_SHIFT) |
@@ -282,16 +285,16 @@ void r300_ring_start(struct radeon_device *rdev)
                           (6 << R300_MS_X5_SHIFT) |
                           (6 << R300_MS_Y5_SHIFT) |
                           (6 << R300_MSBD1_SHIFT)));
-       radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
-       radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
-       radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(R300_GA_ENHANCE, 0));
+       radeon_ring_write(cp, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
+       radeon_ring_write(cp, PACKET0(R300_GA_POLY_MODE, 0));
+       radeon_ring_write(cp,
                          R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
-       radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(R300_GA_ROUND_MODE, 0));
+       radeon_ring_write(cp,
                          R300_GEOMETRY_ROUND_NEAREST |
                          R300_COLOR_ROUND_NEAREST);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_unlock_commit(rdev, cp);
 }
 
 void r300_errata(struct radeon_device *rdev)
@@ -375,26 +378,26 @@ void r300_gpu_init(struct radeon_device *rdev)
                 rdev->num_gb_pipes, rdev->num_z_pipes);
 }
 
-bool r300_gpu_is_lockup(struct radeon_device *rdev)
+bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        u32 rbbm_status;
        int r;
 
        rbbm_status = RREG32(R_000E40_RBBM_STATUS);
        if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
-               r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
+               r100_gpu_lockup_update(&rdev->config.r300.lockup, cp);
                return false;
        }
        /* force CP activities */
-       r = radeon_ring_lock(rdev, 2);
+       r = radeon_ring_lock(rdev, cp, 2);
        if (!r) {
                /* PACKET2 NOP */
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_unlock_commit(rdev);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_unlock_commit(rdev, cp);
        }
-       rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
-       return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
+       cp->rptr = RREG32(RADEON_CP_RB_RPTR);
+       return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, cp);
 }
 
 int r300_asic_reset(struct radeon_device *rdev)
index 5dbc378d3c2e54029953de99af203889666f2349..4c0af4955f0852d54371a799f9c243ff57f42d0a 100644 (file)
@@ -199,6 +199,8 @@ static void r420_clock_resume(struct radeon_device *rdev)
 
 static void r420_cp_errata_init(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
+
        /* RV410 and R420 can lock up if CP DMA to host memory happens
         * while the 2D engine is busy.
         *
@@ -206,22 +208,24 @@ static void r420_cp_errata_init(struct radeon_device *rdev)
         * of the CP init, apparently.
         */
        radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
-       radeon_ring_lock(rdev, 8);
-       radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
-       radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
-       radeon_ring_write(rdev, 0xDEADBEEF);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_lock(rdev, cp, 8);
+       radeon_ring_write(cp, PACKET0(R300_CP_RESYNC_ADDR, 1));
+       radeon_ring_write(cp, rdev->config.r300.resync_scratch);
+       radeon_ring_write(cp, 0xDEADBEEF);
+       radeon_ring_unlock_commit(rdev, cp);
 }
 
 static void r420_cp_errata_fini(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
+
        /* Catch the RESYNC we dispatched all the way back,
         * at the very beginning of the CP init.
         */
-       radeon_ring_lock(rdev, 8);
-       radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_lock(rdev, cp, 8);
+       radeon_ring_write(cp, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, R300_RB3D_DC_FINISH);
+       radeon_ring_unlock_commit(rdev, cp);
        radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 }
 
index bd2b3d087b16cee2c818a53951c50358a57953aa..eaf57cc75828c220171418ef51ce70b6baa2b5a8 100644 (file)
@@ -1344,7 +1344,7 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
        return 0;
 }
 
-bool r600_gpu_is_lockup(struct radeon_device *rdev)
+bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        u32 srbm_status;
        u32 grbm_status;
@@ -1361,19 +1361,19 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
        grbm_status = RREG32(R_008010_GRBM_STATUS);
        grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
        if (!G_008010_GUI_ACTIVE(grbm_status)) {
-               r100_gpu_lockup_update(lockup, &rdev->cp);
+               r100_gpu_lockup_update(lockup, cp);
                return false;
        }
        /* force CP activities */
-       r = radeon_ring_lock(rdev, 2);
+       r = radeon_ring_lock(rdev, cp, 2);
        if (!r) {
                /* PACKET2 NOP */
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_write(rdev, 0x80000000);
-               radeon_ring_unlock_commit(rdev);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_write(cp, 0x80000000);
+               radeon_ring_unlock_commit(rdev, cp);
        }
-       rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
-       return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
+       cp->rptr = RREG32(R600_CP_RB_RPTR);
+       return r100_gpu_cp_is_lockup(rdev, lockup, cp);
 }
 
 int r600_asic_reset(struct radeon_device *rdev)
@@ -2144,27 +2144,28 @@ static int r600_cp_load_microcode(struct radeon_device *rdev)
 
 int r600_cp_start(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r;
        uint32_t cp_me;
 
-       r = radeon_ring_lock(rdev, 7);
+       r = radeon_ring_lock(rdev, cp, 7);
        if (r) {
                DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
                return r;
        }
-       radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
-       radeon_ring_write(rdev, 0x1);
+       radeon_ring_write(cp, PACKET3(PACKET3_ME_INITIALIZE, 5));
+       radeon_ring_write(cp, 0x1);
        if (rdev->family >= CHIP_RV770) {
-               radeon_ring_write(rdev, 0x0);
-               radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
+               radeon_ring_write(cp, 0x0);
+               radeon_ring_write(cp, rdev->config.rv770.max_hw_contexts - 1);
        } else {
-               radeon_ring_write(rdev, 0x3);
-               radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
+               radeon_ring_write(cp, 0x3);
+               radeon_ring_write(cp, rdev->config.r600.max_hw_contexts - 1);
        }
-       radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_write(cp, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_unlock_commit(rdev, cp);
 
        cp_me = 0xff;
        WREG32(R_0086D8_CP_ME_CNTL, cp_me);
@@ -2173,6 +2174,7 @@ int r600_cp_start(struct radeon_device *rdev)
 
 int r600_cp_resume(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 tmp;
        u32 rb_bufsz;
        int r;
@@ -2184,7 +2186,7 @@ int r600_cp_resume(struct radeon_device *rdev)
        WREG32(GRBM_SOFT_RESET, 0);
 
        /* Set ring buffer size */
-       rb_bufsz = drm_order(rdev->cp.ring_size / 8);
+       rb_bufsz = drm_order(cp->ring_size / 8);
        tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 #ifdef __BIG_ENDIAN
        tmp |= BUF_SWAP_32BIT;
@@ -2198,8 +2200,8 @@ int r600_cp_resume(struct radeon_device *rdev)
        /* Initialize the ring buffer's read and write pointers */
        WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
        WREG32(CP_RB_RPTR_WR, 0);
-       rdev->cp.wptr = 0;
-       WREG32(CP_RB_WPTR, rdev->cp.wptr);
+       cp->wptr = 0;
+       WREG32(CP_RB_WPTR, cp->wptr);
 
        /* set the wb address whether it's enabled or not */
        WREG32(CP_RB_RPTR_ADDR,
@@ -2217,42 +2219,42 @@ int r600_cp_resume(struct radeon_device *rdev)
        mdelay(1);
        WREG32(CP_RB_CNTL, tmp);
 
-       WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
+       WREG32(CP_RB_BASE, cp->gpu_addr >> 8);
        WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
 
-       rdev->cp.rptr = RREG32(CP_RB_RPTR);
+       cp->rptr = RREG32(CP_RB_RPTR);
 
        r600_cp_start(rdev);
-       rdev->cp.ready = true;
-       r = radeon_ring_test(rdev);
+       cp->ready = true;
+       r = radeon_ring_test(rdev, cp);
        if (r) {
-               rdev->cp.ready = false;
+               cp->ready = false;
                return r;
        }
        return 0;
 }
 
-void r600_cp_commit(struct radeon_device *rdev)
+void r600_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp)
 {
-       WREG32(CP_RB_WPTR, rdev->cp.wptr);
+       WREG32(CP_RB_WPTR, cp->wptr);
        (void)RREG32(CP_RB_WPTR);
 }
 
-void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
+void r600_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size)
 {
        u32 rb_bufsz;
 
        /* Align ring size */
        rb_bufsz = drm_order(ring_size / 8);
        ring_size = (1 << (rb_bufsz + 1)) * 4;
-       rdev->cp.ring_size = ring_size;
-       rdev->cp.align_mask = 16 - 1;
+       cp->ring_size = ring_size;
+       cp->align_mask = 16 - 1;
 }
 
 void r600_cp_fini(struct radeon_device *rdev)
 {
        r600_cp_stop(rdev);
-       radeon_ring_fini(rdev);
+       radeon_ring_fini(rdev, &rdev->cp);
 }
 
 
@@ -2271,7 +2273,7 @@ void r600_scratch_init(struct radeon_device *rdev)
        }
 }
 
-int r600_ring_test(struct radeon_device *rdev)
+int r600_ring_test(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        uint32_t scratch;
        uint32_t tmp = 0;
@@ -2284,16 +2286,16 @@ int r600_ring_test(struct radeon_device *rdev)
                return r;
        }
        WREG32(scratch, 0xCAFEDEAD);
-       r = radeon_ring_lock(rdev, 3);
+       r = radeon_ring_lock(rdev, cp, 3);
        if (r) {
-               DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+               DRM_ERROR("radeon: cp failed to lock ring %p (%d).\n", cp, r);
                radeon_scratch_free(rdev, scratch);
                return r;
        }
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-       radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
-       radeon_ring_write(rdev, 0xDEADBEEF);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+       radeon_ring_write(cp, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
+       radeon_ring_write(cp, 0xDEADBEEF);
+       radeon_ring_unlock_commit(rdev, cp);
        for (i = 0; i < rdev->usec_timeout; i++) {
                tmp = RREG32(scratch);
                if (tmp == 0xDEADBEEF)
@@ -2301,10 +2303,10 @@ int r600_ring_test(struct radeon_device *rdev)
                DRM_UDELAY(1);
        }
        if (i < rdev->usec_timeout) {
-               DRM_INFO("ring test succeeded in %d usecs\n", i);
+               DRM_INFO("ring test on %p succeeded in %d usecs\n", cp, i);
        } else {
-               DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
-                         scratch, tmp);
+               DRM_ERROR("radeon: ring %p test failed (scratch(0x%04X)=0x%08X)\n",
+                         cp, scratch, tmp);
                r = -EINVAL;
        }
        radeon_scratch_free(rdev, scratch);
@@ -2314,59 +2316,62 @@ int r600_ring_test(struct radeon_device *rdev)
 void r600_fence_ring_emit(struct radeon_device *rdev,
                          struct radeon_fence *fence)
 {
+       struct radeon_cp *cp = &rdev->cp;
+
        if (rdev->wb.use_event) {
                u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
                        (u64)(rdev->fence_drv[fence->ring].scratch_reg - rdev->scratch.reg_base);
                /* flush read cache over gart */
-               radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
-               radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
-                                       PACKET3_VC_ACTION_ENA |
-                                       PACKET3_SH_ACTION_ENA);
-               radeon_ring_write(rdev, 0xFFFFFFFF);
-               radeon_ring_write(rdev, 0);
-               radeon_ring_write(rdev, 10); /* poll interval */
+               radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
+               radeon_ring_write(cp, PACKET3_TC_ACTION_ENA |
+                                     PACKET3_VC_ACTION_ENA |
+                                     PACKET3_SH_ACTION_ENA);
+               radeon_ring_write(cp, 0xFFFFFFFF);
+               radeon_ring_write(cp, 0);
+               radeon_ring_write(cp, 10); /* poll interval */
                /* EVENT_WRITE_EOP - flush caches, send int */
-               radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
-               radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
-               radeon_ring_write(rdev, addr & 0xffffffff);
-               radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
-               radeon_ring_write(rdev, fence->seq);
-               radeon_ring_write(rdev, 0);
+               radeon_ring_write(cp, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+               radeon_ring_write(cp, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
+               radeon_ring_write(cp, addr & 0xffffffff);
+               radeon_ring_write(cp, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
+               radeon_ring_write(cp, fence->seq);
+               radeon_ring_write(cp, 0);
        } else {
                /* flush read cache over gart */
-               radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
-               radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
-                                       PACKET3_VC_ACTION_ENA |
-                                       PACKET3_SH_ACTION_ENA);
-               radeon_ring_write(rdev, 0xFFFFFFFF);
-               radeon_ring_write(rdev, 0);
-               radeon_ring_write(rdev, 10); /* poll interval */
-               radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
-               radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
+               radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
+               radeon_ring_write(cp, PACKET3_TC_ACTION_ENA |
+                                     PACKET3_VC_ACTION_ENA |
+                                     PACKET3_SH_ACTION_ENA);
+               radeon_ring_write(cp, 0xFFFFFFFF);
+               radeon_ring_write(cp, 0);
+               radeon_ring_write(cp, 10); /* poll interval */
+               radeon_ring_write(cp, PACKET3(PACKET3_EVENT_WRITE, 0));
+               radeon_ring_write(cp, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
                /* wait for 3D idle clean */
-               radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-               radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
-               radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
+               radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+               radeon_ring_write(cp, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+               radeon_ring_write(cp, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
                /* Emit fence sequence & fire IRQ */
-               radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-               radeon_ring_write(rdev, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
-               radeon_ring_write(rdev, fence->seq);
+               radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+               radeon_ring_write(cp, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
+               radeon_ring_write(cp, fence->seq);
                /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
-               radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
-               radeon_ring_write(rdev, RB_INT_STAT);
+               radeon_ring_write(cp, PACKET0(CP_INT_STATUS, 0));
+               radeon_ring_write(cp, RB_INT_STAT);
        }
 }
 
 void r600_semaphore_ring_emit(struct radeon_device *rdev,
+                             struct radeon_cp *cp,
                              struct radeon_semaphore *semaphore,
-                             unsigned ring, bool emit_wait)
+                             bool emit_wait)
 {
        uint64_t addr = semaphore->gpu_addr;
        unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
-       radeon_ring_write(rdev, addr & 0xffffffff);
-       radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | sel);
+       radeon_ring_write(cp, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
+       radeon_ring_write(cp, addr & 0xffffffff);
+       radeon_ring_write(cp, (upper_32_bits(addr) & 0xff) | sel);
 }
 
 int r600_copy_blit(struct radeon_device *rdev,
@@ -2421,6 +2426,7 @@ void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
 
 int r600_startup(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r;
 
        /* enable pcie gen2 link */
@@ -2468,7 +2474,7 @@ int r600_startup(struct radeon_device *rdev)
        }
        r600_irq_set(rdev);
 
-       r = radeon_ring_init(rdev, rdev->cp.ring_size);
+       r = radeon_ring_init(rdev, cp, cp->ring_size);
        if (r)
                return r;
        r = r600_cp_load_microcode(rdev);
@@ -2512,7 +2518,7 @@ int r600_resume(struct radeon_device *rdev)
                return r;
        }
 
-       r = r600_ib_test(rdev);
+       r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
        if (r) {
                DRM_ERROR("radeon: failed testing IB (%d).\n", r);
                return r;
@@ -2608,7 +2614,7 @@ int r600_init(struct radeon_device *rdev)
                return r;
 
        rdev->cp.ring_obj = NULL;
-       r600_ring_init(rdev, 1024 * 1024);
+       r600_ring_init(rdev, &rdev->cp, 1024 * 1024);
 
        rdev->ih.ring_obj = NULL;
        r600_ih_ring_init(rdev, 64 * 1024);
@@ -2634,7 +2640,7 @@ int r600_init(struct radeon_device *rdev)
                        dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
                        rdev->accel_working = false;
                } else {
-                       r = r600_ib_test(rdev);
+                       r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
                        if (r) {
                                dev_err(rdev->dev, "IB test failed (%d).\n", r);
                                rdev->accel_working = false;
@@ -2675,18 +2681,20 @@ void r600_fini(struct radeon_device *rdev)
  */
 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 {
+       struct radeon_cp *cp = &rdev->cp;
+
        /* FIXME: implement */
-       radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+       radeon_ring_write(cp,
 #ifdef __BIG_ENDIAN
                          (2 << 0) |
 #endif
                          (ib->gpu_addr & 0xFFFFFFFC));
-       radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
-       radeon_ring_write(rdev, ib->length_dw);
+       radeon_ring_write(cp, upper_32_bits(ib->gpu_addr) & 0xFF);
+       radeon_ring_write(cp, ib->length_dw);
 }
 
-int r600_ib_test(struct radeon_device *rdev)
+int r600_ib_test(struct radeon_device *rdev, int ring)
 {
        struct radeon_ib *ib;
        uint32_t scratch;
@@ -2700,7 +2708,7 @@ int r600_ib_test(struct radeon_device *rdev)
                return r;
        }
        WREG32(scratch, 0xCAFEDEAD);
-       r = radeon_ib_get(rdev, &ib);
+       r = radeon_ib_get(rdev, ring, &ib);
        if (r) {
                DRM_ERROR("radeon: failed to get ib (%d).\n", r);
                return r;
@@ -2741,7 +2749,7 @@ int r600_ib_test(struct radeon_device *rdev)
                DRM_UDELAY(1);
        }
        if (i < rdev->usec_timeout) {
-               DRM_INFO("ib test succeeded in %u usecs\n", i);
+               DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib->fence->ring, i);
        } else {
                DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
                          scratch, tmp);
@@ -3514,21 +3522,22 @@ static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
        struct drm_info_node *node = (struct drm_info_node *) m->private;
        struct drm_device *dev = node->minor->dev;
        struct radeon_device *rdev = dev->dev_private;
+       struct radeon_cp *cp = &rdev->cp;
        unsigned count, i, j;
 
-       radeon_ring_free_size(rdev);
-       count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
+       radeon_ring_free_size(rdev, cp);
+       count = (cp->ring_size / 4) - cp->ring_free_dw;
        seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
        seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
        seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
-       seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
-       seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
-       seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
+       seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", cp->wptr);
+       seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", cp->rptr);
+       seq_printf(m, "%u free dwords in ring\n", cp->ring_free_dw);
        seq_printf(m, "%u dwords in ring\n", count);
-       i = rdev->cp.rptr;
+       i = cp->rptr;
        for (j = 0; j <= count; j++) {
-               seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
-               i = (i + 1) & rdev->cp.ptr_mask;
+               seq_printf(m, "r[%04d]=0x%08x\n", i, cp->ring[i]);
+               i = (i + 1) & cp->ptr_mask;
        }
        return 0;
 }
index e09d2818f949f55615c8e33723f14d73bdb69660..39ae19d38c2f06e83a5d698fbfe7d630e77b36ae 100644 (file)
@@ -50,6 +50,7 @@ static void
 set_render_target(struct radeon_device *rdev, int format,
                  int w, int h, u64 gpu_addr)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 cb_color_info;
        int pitch, slice;
 
@@ -63,38 +64,38 @@ set_render_target(struct radeon_device *rdev, int format,
        pitch = (w / 8) - 1;
        slice = ((w * h) / 64) - 1;
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, gpu_addr >> 8);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, gpu_addr >> 8);
 
        if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
-               radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
-               radeon_ring_write(rdev, 2 << 0);
+               radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
+               radeon_ring_write(cp, 2 << 0);
        }
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, (pitch << 0) | (slice << 10));
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, 0);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, cb_color_info);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, cb_color_info);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, 0);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, 0);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, 0);
 }
 
 /* emits 5dw */
@@ -103,6 +104,7 @@ cp_set_surface_sync(struct radeon_device *rdev,
                    u32 sync_type, u32 size,
                    u64 mc_addr)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 cp_coher_size;
 
        if (size == 0xffffffff)
@@ -110,17 +112,18 @@ cp_set_surface_sync(struct radeon_device *rdev,
        else
                cp_coher_size = ((size + 255) >> 8);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
-       radeon_ring_write(rdev, sync_type);
-       radeon_ring_write(rdev, cp_coher_size);
-       radeon_ring_write(rdev, mc_addr >> 8);
-       radeon_ring_write(rdev, 10); /* poll interval */
+       radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
+       radeon_ring_write(cp, sync_type);
+       radeon_ring_write(cp, cp_coher_size);
+       radeon_ring_write(cp, mc_addr >> 8);
+       radeon_ring_write(cp, 10); /* poll interval */
 }
 
 /* emits 21dw + 1 surface sync = 26dw */
 static void
 set_shaders(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u64 gpu_addr;
        u32 sq_pgm_resources;
 
@@ -129,35 +132,35 @@ set_shaders(struct radeon_device *rdev)
 
        /* VS */
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, gpu_addr >> 8);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, gpu_addr >> 8);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, sq_pgm_resources);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, sq_pgm_resources);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, 0);
 
        /* PS */
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, gpu_addr >> 8);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, gpu_addr >> 8);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, sq_pgm_resources | (1 << 28));
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, 2);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, 2);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
-       radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, 0);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
+       radeon_ring_write(cp, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, 0);
 
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
        cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
@@ -167,6 +170,7 @@ set_shaders(struct radeon_device *rdev)
 static void
 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 sq_vtx_constant_word2;
 
        sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
@@ -175,15 +179,15 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
        sq_vtx_constant_word2 |=  SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
 #endif
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
-       radeon_ring_write(rdev, 0x460);
-       radeon_ring_write(rdev, gpu_addr & 0xffffffff);
-       radeon_ring_write(rdev, 48 - 1);
-       radeon_ring_write(rdev, sq_vtx_constant_word2);
-       radeon_ring_write(rdev, 1 << 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 7));
+       radeon_ring_write(cp, 0x460);
+       radeon_ring_write(cp, gpu_addr & 0xffffffff);
+       radeon_ring_write(cp, 48 - 1);
+       radeon_ring_write(cp, sq_vtx_constant_word2);
+       radeon_ring_write(cp, 1 << 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, SQ_TEX_VTX_VALID_BUFFER << 30);
 
        if ((rdev->family == CHIP_RV610) ||
            (rdev->family == CHIP_RV620) ||
@@ -203,6 +207,7 @@ set_tex_resource(struct radeon_device *rdev,
                 int format, int w, int h, int pitch,
                 u64 gpu_addr, u32 size)
 {
+       struct radeon_cp *cp = &rdev->cp;
        uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
 
        if (h < 1)
@@ -225,15 +230,15 @@ set_tex_resource(struct radeon_device *rdev,
        cp_set_surface_sync(rdev,
                            PACKET3_TC_ACTION_ENA, size, gpu_addr);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, sq_tex_resource_word0);
-       radeon_ring_write(rdev, sq_tex_resource_word1);
-       radeon_ring_write(rdev, gpu_addr >> 8);
-       radeon_ring_write(rdev, gpu_addr >> 8);
-       radeon_ring_write(rdev, sq_tex_resource_word4);
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 7));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, sq_tex_resource_word0);
+       radeon_ring_write(cp, sq_tex_resource_word1);
+       radeon_ring_write(cp, gpu_addr >> 8);
+       radeon_ring_write(cp, gpu_addr >> 8);
+       radeon_ring_write(cp, sq_tex_resource_word4);
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, SQ_TEX_VTX_VALID_TEXTURE << 30);
 }
 
 /* emits 12 */
@@ -241,43 +246,45 @@ static void
 set_scissors(struct radeon_device *rdev, int x1, int y1,
             int x2, int y2)
 {
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
-       radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
-       radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
-
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
-       radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
-       radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
-
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
-       radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
-       radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
+       struct radeon_cp *cp = &rdev->cp;
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+       radeon_ring_write(cp, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, (x1 << 0) | (y1 << 16));
+       radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
+
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+       radeon_ring_write(cp, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
+       radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
+
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+       radeon_ring_write(cp, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
+       radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
 }
 
 /* emits 10 */
 static void
 draw_auto(struct radeon_device *rdev)
 {
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-       radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, DI_PT_RECTLIST);
+       struct radeon_cp *cp = &rdev->cp;
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+       radeon_ring_write(cp, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, DI_PT_RECTLIST);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET3(PACKET3_INDEX_TYPE, 0));
+       radeon_ring_write(cp,
 #ifdef __BIG_ENDIAN
                          (2 << 2) |
 #endif
                          DI_INDEX_SIZE_16_BIT);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
-       radeon_ring_write(rdev, 1);
+       radeon_ring_write(cp, PACKET3(PACKET3_NUM_INSTANCES, 0));
+       radeon_ring_write(cp, 1);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
-       radeon_ring_write(rdev, 3);
-       radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
+       radeon_ring_write(cp, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
+       radeon_ring_write(cp, 3);
+       radeon_ring_write(cp, DI_SRC_SEL_AUTO_INDEX);
 
 }
 
@@ -285,6 +292,7 @@ draw_auto(struct radeon_device *rdev)
 static void
 set_default_state(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
        u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
        int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
@@ -440,24 +448,24 @@ set_default_state(struct radeon_device *rdev)
        /* emit an IB pointing at default state */
        dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
-       radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+       radeon_ring_write(cp,
 #ifdef __BIG_ENDIAN
                          (2 << 0) |
 #endif
                          (gpu_addr & 0xFFFFFFFC));
-       radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
-       radeon_ring_write(rdev, dwords);
+       radeon_ring_write(cp, upper_32_bits(gpu_addr) & 0xFF);
+       radeon_ring_write(cp, dwords);
 
        /* SQ config */
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
-       radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, sq_config);
-       radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
-       radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
-       radeon_ring_write(rdev, sq_thread_resource_mgmt);
-       radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
-       radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
+       radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 6));
+       radeon_ring_write(cp, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+       radeon_ring_write(cp, sq_config);
+       radeon_ring_write(cp, sq_gpr_resource_mgmt_1);
+       radeon_ring_write(cp, sq_gpr_resource_mgmt_2);
+       radeon_ring_write(cp, sq_thread_resource_mgmt);
+       radeon_ring_write(cp, sq_stack_resource_mgmt_1);
+       radeon_ring_write(cp, sq_stack_resource_mgmt_2);
 }
 
 static uint32_t i2f(uint32_t input)
@@ -614,7 +622,7 @@ void r600_blit_fini(struct radeon_device *rdev)
 static int r600_vb_ib_get(struct radeon_device *rdev)
 {
        int r;
-       r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
+       r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->r600_blit.vb_ib);
        if (r) {
                DRM_ERROR("failed to get IB for vertex buffer\n");
                return r;
@@ -679,6 +687,7 @@ static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
 
 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r;
        int ring_size;
        int num_loops = 0;
@@ -699,7 +708,7 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages)
        /* calculate number of loops correctly */
        ring_size = num_loops * dwords_per_loop;
        ring_size += rdev->r600_blit.ring_size_common;
-       r = radeon_ring_lock(rdev, ring_size);
+       r = radeon_ring_lock(rdev, cp, ring_size);
        if (r)
                return r;
 
@@ -718,7 +727,7 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
        if (fence)
                r = radeon_fence_emit(rdev, fence);
 
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_unlock_commit(rdev, &rdev->cp);
 }
 
 void r600_kms_blit_copy(struct radeon_device *rdev,
index 6d84c64759e9b6279026307dadb5db7373457c5f..5bf8603f3956fb97bb4dc6296ebb590e2a892b52 100644 (file)
@@ -230,6 +230,8 @@ void radeon_fence_unref(struct radeon_fence **fence);
 /*
  * Semaphores.
  */
+struct radeon_cp;
+
 struct radeon_semaphore_driver {
        rwlock_t                lock;
        struct list_head        free;
@@ -585,7 +587,7 @@ struct r600_blit {
 
 void r600_blit_suspend(struct radeon_device *rdev);
 
-int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
+int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib);
 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 int radeon_ib_pool_init(struct radeon_device *rdev);
@@ -593,15 +595,15 @@ void radeon_ib_pool_fini(struct radeon_device *rdev);
 int radeon_ib_test(struct radeon_device *rdev);
 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
 /* Ring access between begin & end cannot sleep */
-void radeon_ring_free_size(struct radeon_device *rdev);
-int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
-int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
-void radeon_ring_commit(struct radeon_device *rdev);
-void radeon_ring_unlock_commit(struct radeon_device *rdev);
-void radeon_ring_unlock_undo(struct radeon_device *rdev);
-int radeon_ring_test(struct radeon_device *rdev);
-int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
-void radeon_ring_fini(struct radeon_device *rdev);
+void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_cp *cp);
+int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw);
+int radeon_ring_lock(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw);
+void radeon_ring_commit(struct radeon_device *rdev, struct radeon_cp *cp);
+void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_cp *cp);
+void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_cp *cp);
+int radeon_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
+int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size);
+void radeon_ring_fini(struct radeon_device *rdev, struct radeon_cp *cp);
 
 
 /*
@@ -930,24 +932,25 @@ struct radeon_asic {
        int (*resume)(struct radeon_device *rdev);
        int (*suspend)(struct radeon_device *rdev);
        void (*vga_set_state)(struct radeon_device *rdev, bool state);
-       bool (*gpu_is_lockup)(struct radeon_device *rdev);
+       bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_cp *cp);
        int (*asic_reset)(struct radeon_device *rdev);
        void (*gart_tlb_flush)(struct radeon_device *rdev);
        int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
        int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
        void (*cp_fini)(struct radeon_device *rdev);
        void (*cp_disable)(struct radeon_device *rdev);
-       void (*cp_commit)(struct radeon_device *rdev);
+       void (*cp_commit)(struct radeon_device *rdev, struct radeon_cp *cp);
        void (*ring_start)(struct radeon_device *rdev);
-       int (*ring_test)(struct radeon_device *rdev);
+       int (*ring_test)(struct radeon_device *rdev, struct radeon_cp *cp);
        void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
        int (*irq_set)(struct radeon_device *rdev);
        int (*irq_process)(struct radeon_device *rdev);
        u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
        void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
        void (*semaphore_ring_emit)(struct radeon_device *rdev,
+                                   struct radeon_cp *cp,
                                    struct radeon_semaphore *semaphore,
-                                   unsigned ring, bool emit_wait);
+                                   bool emit_wait);
        int (*cs_parse)(struct radeon_cs_parser *p);
        int (*copy_blit)(struct radeon_device *rdev,
                         uint64_t src_offset,
@@ -1279,7 +1282,6 @@ struct radeon_device {
        struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
        struct radeon_semaphore_driver  semaphore_drv;
        struct radeon_cp                cp;
-       /* cayman compute rings */
        struct radeon_cp                cp1;
        struct radeon_cp                cp2;
        struct radeon_ib_pool           ib_pool;
@@ -1463,18 +1465,17 @@ void radeon_atombios_fini(struct radeon_device *rdev);
 /*
  * RING helpers.
  */
-
 #if DRM_DEBUG_CODE == 0
-static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
+static inline void radeon_ring_write(struct radeon_cp *cp, uint32_t v)
 {
-       rdev->cp.ring[rdev->cp.wptr++] = v;
-       rdev->cp.wptr &= rdev->cp.ptr_mask;
-       rdev->cp.count_dw--;
-       rdev->cp.ring_free_dw--;
+       cp->ring[cp->wptr++] = v;
+       cp->wptr &= cp->ptr_mask;
+       cp->count_dw--;
+       cp->ring_free_dw--;
 }
 #else
 /* With debugging this is just too big to inline */
-void radeon_ring_write(struct radeon_device *rdev, uint32_t v);
+void radeon_ring_write(struct radeon_cp *cp, uint32_t v);
 #endif
 
 /*
@@ -1486,19 +1487,19 @@ void radeon_ring_write(struct radeon_device *rdev, uint32_t v);
 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
-#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
+#define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
-#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
+#define radeon_cp_commit(rdev, cp) (rdev)->asic->cp_commit((rdev), (cp))
 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
-#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
+#define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
-#define radeon_semaphore_ring_emit(rdev, semaphore, ring, emit_wait) (rdev)->asic->semaphore_ring_emit((rdev), (semaphore), (ring), (emit_wait))
+#define radeon_semaphore_ring_emit(rdev, cp, semaphore, emit_wait) (rdev)->asic->semaphore_ring_emit((rdev), (cp), (semaphore), (emit_wait))
 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
index 6b589d5ae43650fdcabbc755658cbf06a4d387b2..4f8447557298ae3241716f03f4d94d6486965b7e 100644 (file)
@@ -58,20 +58,21 @@ void r100_fini(struct radeon_device *rdev);
 int r100_suspend(struct radeon_device *rdev);
 int r100_resume(struct radeon_device *rdev);
 void r100_vga_set_state(struct radeon_device *rdev, bool state);
-bool r100_gpu_is_lockup(struct radeon_device *rdev);
+bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
 int r100_asic_reset(struct radeon_device *rdev);
 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
-void r100_cp_commit(struct radeon_device *rdev);
+void r100_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp);
 void r100_ring_start(struct radeon_device *rdev);
 int r100_irq_set(struct radeon_device *rdev);
 int r100_irq_process(struct radeon_device *rdev);
 void r100_fence_ring_emit(struct radeon_device *rdev,
                          struct radeon_fence *fence);
 void r100_semaphore_ring_emit(struct radeon_device *rdev,
+                             struct radeon_cp *cp,
                              struct radeon_semaphore *semaphore,
-                             unsigned ring, bool emit_wait);
+                             bool emit_wait);
 int r100_cs_parse(struct radeon_cs_parser *p);
 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
@@ -86,7 +87,7 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
 void r100_bandwidth_update(struct radeon_device *rdev);
 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-int r100_ring_test(struct radeon_device *rdev);
+int r100_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
 void r100_hpd_init(struct radeon_device *rdev);
 void r100_hpd_fini(struct radeon_device *rdev);
 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
@@ -157,7 +158,7 @@ extern int r300_init(struct radeon_device *rdev);
 extern void r300_fini(struct radeon_device *rdev);
 extern int r300_suspend(struct radeon_device *rdev);
 extern int r300_resume(struct radeon_device *rdev);
-extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
+extern bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
 extern int r300_asic_reset(struct radeon_device *rdev);
 extern void r300_ring_start(struct radeon_device *rdev);
 extern void r300_fence_ring_emit(struct radeon_device *rdev,
@@ -296,7 +297,7 @@ int r600_resume(struct radeon_device *rdev);
 void r600_vga_set_state(struct radeon_device *rdev, bool state);
 int r600_wb_init(struct radeon_device *rdev);
 void r600_wb_fini(struct radeon_device *rdev);
-void r600_cp_commit(struct radeon_device *rdev);
+void r600_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp);
 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
@@ -304,17 +305,18 @@ int r600_cs_parse(struct radeon_cs_parser *p);
 void r600_fence_ring_emit(struct radeon_device *rdev,
                          struct radeon_fence *fence);
 void r600_semaphore_ring_emit(struct radeon_device *rdev,
+                             struct radeon_cp *cp,
                              struct radeon_semaphore *semaphore,
-                             unsigned ring, bool emit_wait);
-bool r600_gpu_is_lockup(struct radeon_device *rdev);
+                             bool emit_wait);
+bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
 int r600_asic_reset(struct radeon_device *rdev);
 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
                         uint32_t tiling_flags, uint32_t pitch,
                         uint32_t offset, uint32_t obj_size);
 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
-int r600_ib_test(struct radeon_device *rdev);
+int r600_ib_test(struct radeon_device *rdev, int ring);
 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-int r600_ring_test(struct radeon_device *rdev);
+int r600_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
 int r600_copy_blit(struct radeon_device *rdev,
                   uint64_t src_offset, uint64_t dst_offset,
                   unsigned num_gpu_pages, struct radeon_fence *fence);
@@ -334,7 +336,7 @@ extern int r600_get_pcie_lanes(struct radeon_device *rdev);
 bool r600_card_posted(struct radeon_device *rdev);
 void r600_cp_stop(struct radeon_device *rdev);
 int r600_cp_start(struct radeon_device *rdev);
-void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
+void r600_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size);
 int r600_cp_resume(struct radeon_device *rdev);
 void r600_cp_fini(struct radeon_device *rdev);
 int r600_count_pipe_bits(uint32_t val);
@@ -403,7 +405,7 @@ int evergreen_init(struct radeon_device *rdev);
 void evergreen_fini(struct radeon_device *rdev);
 int evergreen_suspend(struct radeon_device *rdev);
 int evergreen_resume(struct radeon_device *rdev);
-bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
+bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
 int evergreen_asic_reset(struct radeon_device *rdev);
 void evergreen_bandwidth_update(struct radeon_device *rdev);
 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
@@ -434,7 +436,7 @@ int cayman_init(struct radeon_device *rdev);
 void cayman_fini(struct radeon_device *rdev);
 int cayman_suspend(struct radeon_device *rdev);
 int cayman_resume(struct radeon_device *rdev);
-bool cayman_gpu_is_lockup(struct radeon_device *rdev);
+bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
 int cayman_asic_reset(struct radeon_device *rdev);
 
 #endif
index aaacadc86ae7a1b39d5dd290b01fbaa1f5aa8c1f..09ef48636e53878e5f4241971bee8d26c1cae37e 100644 (file)
@@ -246,7 +246,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                radeon_mutex_unlock(&rdev->cs_mutex);
                return r;
        }
-       r =  radeon_ib_get(rdev, &parser.ib);
+       r =  radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &parser.ib);
        if (r) {
                DRM_ERROR("Failed to get ib !\n");
                radeon_cs_parser_fini(&parser, r);
index 086b8a399118390b2f7a9a915499194fffe57b1b..9ed0bb100bcbf8112fdd7317c41b80c6e038ac2b 100644 (file)
@@ -269,7 +269,7 @@ retry:
                 * if we experiencing a lockup the value doesn't change
                 */
                if (seq == rdev->fence_drv[fence->ring].last_seq &&
-                   radeon_gpu_is_lockup(rdev)) {
+                   radeon_gpu_is_lockup(rdev, &rdev->cp)) {
                        /* good news we believe it's a lockup */
                        printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
                             fence->seq, seq);
index aa1ca2dea42f1623f09c062e4c9171e220c75c0d..136772ccfe728ae5aba012aaa70c76f36fdc2bf6 100644 (file)
@@ -160,8 +160,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
        if (rdev->stollen_vga_memory)
                args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory);
        args->vram_visible -= radeon_fbdev_total_size(rdev);
-       args->gart_size = rdev->mc.gtt_size - rdev->cp.ring_size - 4096 -
-               RADEON_IB_POOL_SIZE*64*1024;
+       args->gart_size = rdev->mc.gtt_size - 4096 - RADEON_IB_POOL_SIZE*64*1024;
+       args->gart_size -= rdev->cp.ring_size;
        return 0;
 }
 
index 19ed2c6c424aa75252651a4e5dd683a0a9712c53..73b6714d615bb669ea6ba235457d925fa2ed26c6 100644 (file)
@@ -252,7 +252,8 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
 
        mutex_lock(&rdev->ddev->struct_mutex);
        mutex_lock(&rdev->vram_mutex);
-       mutex_lock(&rdev->cp.mutex);
+       if (rdev->cp.ring_obj)
+               mutex_lock(&rdev->cp.mutex);
 
        /* gui idle int has issues on older chips it seems */
        if (rdev->family >= CHIP_R600) {
@@ -268,12 +269,13 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
                        radeon_irq_set(rdev);
                }
        } else {
-               if (rdev->cp.ready) {
+               struct radeon_cp *cp = &rdev->cp;
+               if (cp->ready) {
                        struct radeon_fence *fence;
-                       radeon_ring_alloc(rdev, 64);
+                       radeon_ring_alloc(rdev, cp, 64);
                        radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
                        radeon_fence_emit(rdev, fence);
-                       radeon_ring_commit(rdev);
+                       radeon_ring_commit(rdev, cp);
                        radeon_fence_wait(fence, false);
                        radeon_fence_unref(&fence);
                }
@@ -307,7 +309,8 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
 
        rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 
-       mutex_unlock(&rdev->cp.mutex);
+       if (rdev->cp.ring_obj)
+               mutex_unlock(&rdev->cp.mutex);
        mutex_unlock(&rdev->vram_mutex);
        mutex_unlock(&rdev->ddev->struct_mutex);
 }
index c232317b1dd21d568d24c149027b5c34509f4f73..bc8a5807f1a4694f5e9af0fce73858b6960fe898 100644 (file)
@@ -60,17 +60,17 @@ u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
        return idx_value;
 }
 
-void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
+void radeon_ring_write(struct radeon_cp *cp, uint32_t v)
 {
 #if DRM_DEBUG_CODE
-       if (rdev->cp.count_dw <= 0) {
+       if (cp->count_dw <= 0) {
                DRM_ERROR("radeon: writting more dword to ring than expected !\n");
        }
 #endif
-       rdev->cp.ring[rdev->cp.wptr++] = v;
-       rdev->cp.wptr &= rdev->cp.ptr_mask;
-       rdev->cp.count_dw--;
-       rdev->cp.ring_free_dw--;
+       cp->ring[cp->wptr++] = v;
+       cp->wptr &= cp->ptr_mask;
+       cp->count_dw--;
+       cp->ring_free_dw--;
 }
 
 void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
@@ -106,14 +106,14 @@ void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
 /*
  * IB.
  */
-int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
+int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib)
 {
        struct radeon_fence *fence;
        struct radeon_ib *nib;
        int r = 0, i, c;
 
        *ib = NULL;
-       r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
+       r = radeon_fence_create(rdev, &fence, ring);
        if (r) {
                dev_err(rdev->dev, "failed to create fence for new IB\n");
                return r;
@@ -178,16 +178,17 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
 
 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r = 0;
 
-       if (!ib->length_dw || !rdev->cp.ready) {
+       if (!ib->length_dw || !cp->ready) {
                /* TODO: Nothings in the ib we should report. */
                DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
                return -EINVAL;
        }
 
        /* 64 dwords should be enough for fence too */
-       r = radeon_ring_lock(rdev, 64);
+       r = radeon_ring_lock(rdev, cp, 64);
        if (r) {
                DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
                return r;
@@ -198,7 +199,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
        /* once scheduled IB is considered free and protected by the fence */
        ib->free = true;
        mutex_unlock(&rdev->ib_pool.mutex);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_unlock_commit(rdev, cp);
        return 0;
 }
 
@@ -283,7 +284,7 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
 /*
  * Ring.
  */
-void radeon_ring_free_size(struct radeon_device *rdev)
+void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        if (rdev->wb.enabled)
                rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]);
@@ -294,122 +295,123 @@ void radeon_ring_free_size(struct radeon_device *rdev)
                        rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
        }
        /* This works because ring_size is a power of 2 */
-       rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
-       rdev->cp.ring_free_dw -= rdev->cp.wptr;
-       rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
-       if (!rdev->cp.ring_free_dw) {
-               rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
+       cp->ring_free_dw = (cp->rptr + (cp->ring_size / 4));
+       cp->ring_free_dw -= cp->wptr;
+       cp->ring_free_dw &= cp->ptr_mask;
+       if (!cp->ring_free_dw) {
+               cp->ring_free_dw = cp->ring_size / 4;
        }
 }
 
-int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw)
+
+int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw)
 {
        int r;
 
        /* Align requested size with padding so unlock_commit can
         * pad safely */
-       ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
-       while (ndw > (rdev->cp.ring_free_dw - 1)) {
-               radeon_ring_free_size(rdev);
-               if (ndw < rdev->cp.ring_free_dw) {
+       ndw = (ndw + cp->align_mask) & ~cp->align_mask;
+       while (ndw > (cp->ring_free_dw - 1)) {
+               radeon_ring_free_size(rdev, cp);
+               if (ndw < cp->ring_free_dw) {
                        break;
                }
                r = radeon_fence_wait_next(rdev, RADEON_RING_TYPE_GFX_INDEX);
                if (r)
                        return r;
        }
-       rdev->cp.count_dw = ndw;
-       rdev->cp.wptr_old = rdev->cp.wptr;
+       cp->count_dw = ndw;
+       cp->wptr_old = cp->wptr;
        return 0;
 }
 
-int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
+int radeon_ring_lock(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw)
 {
        int r;
 
-       mutex_lock(&rdev->cp.mutex);
-       r = radeon_ring_alloc(rdev, ndw);
+       mutex_lock(&cp->mutex);
+       r = radeon_ring_alloc(rdev, cp, ndw);
        if (r) {
-               mutex_unlock(&rdev->cp.mutex);
+               mutex_unlock(&cp->mutex);
                return r;
        }
        return 0;
 }
 
-void radeon_ring_commit(struct radeon_device *rdev)
+void radeon_ring_commit(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        unsigned count_dw_pad;
        unsigned i;
 
        /* We pad to match fetch size */
-       count_dw_pad = (rdev->cp.align_mask + 1) -
-                      (rdev->cp.wptr & rdev->cp.align_mask);
+       count_dw_pad = (cp->align_mask + 1) -
+                      (cp->wptr & cp->align_mask);
        for (i = 0; i < count_dw_pad; i++) {
-               radeon_ring_write(rdev, 2 << 30);
+               radeon_ring_write(cp, 2 << 30);
        }
        DRM_MEMORYBARRIER();
-       radeon_cp_commit(rdev);
+       radeon_cp_commit(rdev, cp);
 }
 
-void radeon_ring_unlock_commit(struct radeon_device *rdev)
+void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_cp *cp)
 {
-       radeon_ring_commit(rdev);
-       mutex_unlock(&rdev->cp.mutex);
+       radeon_ring_commit(rdev, cp);
+       mutex_unlock(&cp->mutex);
 }
 
-void radeon_ring_unlock_undo(struct radeon_device *rdev)
+void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_cp *cp)
 {
-       rdev->cp.wptr = rdev->cp.wptr_old;
-       mutex_unlock(&rdev->cp.mutex);
+       cp->wptr = cp->wptr_old;
+       mutex_unlock(&cp->mutex);
 }
 
-int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
+int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size)
 {
        int r;
 
-       rdev->cp.ring_size = ring_size;
+       cp->ring_size = ring_size;
        /* Allocate ring buffer */
-       if (rdev->cp.ring_obj == NULL) {
-               r = radeon_bo_create(rdev, rdev->cp.ring_size, PAGE_SIZE, true,
+       if (cp->ring_obj == NULL) {
+               r = radeon_bo_create(rdev, cp->ring_size, PAGE_SIZE, true,
                                        RADEON_GEM_DOMAIN_GTT,
-                                       &rdev->cp.ring_obj);
+                                       &cp->ring_obj);
                if (r) {
                        dev_err(rdev->dev, "(%d) ring create failed\n", r);
                        return r;
                }
-               r = radeon_bo_reserve(rdev->cp.ring_obj, false);
+               r = radeon_bo_reserve(cp->ring_obj, false);
                if (unlikely(r != 0))
                        return r;
-               r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
-                                       &rdev->cp.gpu_addr);
+               r = radeon_bo_pin(cp->ring_obj, RADEON_GEM_DOMAIN_GTT,
+                                       &cp->gpu_addr);
                if (r) {
-                       radeon_bo_unreserve(rdev->cp.ring_obj);
+                       radeon_bo_unreserve(cp->ring_obj);
                        dev_err(rdev->dev, "(%d) ring pin failed\n", r);
                        return r;
                }
-               r = radeon_bo_kmap(rdev->cp.ring_obj,
-                                      (void **)&rdev->cp.ring);
-               radeon_bo_unreserve(rdev->cp.ring_obj);
+               r = radeon_bo_kmap(cp->ring_obj,
+                                      (void **)&cp->ring);
+               radeon_bo_unreserve(cp->ring_obj);
                if (r) {
                        dev_err(rdev->dev, "(%d) ring map failed\n", r);
                        return r;
                }
        }
-       rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
-       rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
+       cp->ptr_mask = (cp->ring_size / 4) - 1;
+       cp->ring_free_dw = cp->ring_size / 4;
        return 0;
 }
 
-void radeon_ring_fini(struct radeon_device *rdev)
+void radeon_ring_fini(struct radeon_device *rdev, struct radeon_cp *cp)
 {
        int r;
        struct radeon_bo *ring_obj;
 
-       mutex_lock(&rdev->cp.mutex);
-       ring_obj = rdev->cp.ring_obj;
-       rdev->cp.ring = NULL;
-       rdev->cp.ring_obj = NULL;
-       mutex_unlock(&rdev->cp.mutex);
+       mutex_lock(&cp->mutex);
+       ring_obj = cp->ring_obj;
+       cp->ring = NULL;
+       cp->ring_obj = NULL;
+       mutex_unlock(&cp->mutex);
 
        if (ring_obj) {
                r = radeon_bo_reserve(ring_obj, false);
@@ -422,7 +424,6 @@ void radeon_ring_fini(struct radeon_device *rdev)
        }
 }
 
-
 /*
  * Debugfs info
  */
index f7d3104de6d410db1675ecaa41d6546457999381..064694a67824cfa9078bffe29b736fc4b7a2f09c 100644 (file)
@@ -121,13 +121,13 @@ int radeon_semaphore_create(struct radeon_device *rdev,
 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
                                  struct radeon_semaphore *semaphore)
 {
-       radeon_semaphore_ring_emit(rdev, semaphore, ring, false);
+       radeon_semaphore_ring_emit(rdev, &rdev->cp, semaphore, false);
 }
 
 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
                                struct radeon_semaphore *semaphore)
 {
-       radeon_semaphore_ring_emit(rdev, semaphore, ring, true);
+       radeon_semaphore_ring_emit(rdev, &rdev->cp, semaphore, true);
 }
 
 void radeon_semaphore_free(struct radeon_device *rdev,
index 37f7acb6d5f7866a32c6192b65a0e800f45bcf62..ee6c160ffae97b06a842d9a65f6a0a1a2c1a54e1 100644 (file)
@@ -42,7 +42,8 @@ void radeon_test_moves(struct radeon_device *rdev)
        /* Number of tests =
         * (Total GTT - IB pool - writeback page - ring buffers) / test size
         */
-       n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - rdev->cp.ring_size;
+       n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024;
+       n -= rdev->cp.ring_size;
        if (rdev->wb.wb_obj)
                n -= RADEON_GPU_PAGE_SIZE;
        if (rdev->ih.ring_obj)
index fd8da02e1ca5f19758f6d569b14ee10bcceec91f..8fe13ba8143a8499d2719fd6764848b9f5d5b550 100644 (file)
@@ -55,44 +55,45 @@ void rv515_debugfs(struct radeon_device *rdev)
 
 void rv515_ring_start(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r;
 
-       r = radeon_ring_lock(rdev, 64);
+       r = radeon_ring_lock(rdev, cp, 64);
        if (r) {
                return;
        }
-       radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(ISYNC_CNTL, 0));
+       radeon_ring_write(cp,
                          ISYNC_ANY2D_IDLE3D |
                          ISYNC_ANY3D_IDLE2D |
                          ISYNC_WAIT_IDLEGUI |
                          ISYNC_CPSCRATCH_IDLEGUI);
-       radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
-       radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
-       radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
-       radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
-       radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, PACKET0(R500_SU_REG_DEST, 0));
-       radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
-       radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
-       radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
-       radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
-       radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
-       radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
-       radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
-       radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
-       radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(WAIT_UNTIL, 0));
+       radeon_ring_write(cp, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
+       radeon_ring_write(cp, PACKET0(R300_DST_PIPE_CONFIG, 0));
+       radeon_ring_write(cp, R300_PIPE_AUTO_CONFIG);
+       radeon_ring_write(cp, PACKET0(GB_SELECT, 0));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, PACKET0(GB_ENABLE, 0));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, PACKET0(R500_SU_REG_DEST, 0));
+       radeon_ring_write(cp, (1 << rdev->num_gb_pipes) - 1);
+       radeon_ring_write(cp, PACKET0(VAP_INDEX_OFFSET, 0));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, RB3D_DC_FLUSH | RB3D_DC_FREE);
+       radeon_ring_write(cp, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, ZC_FLUSH | ZC_FREE);
+       radeon_ring_write(cp, PACKET0(WAIT_UNTIL, 0));
+       radeon_ring_write(cp, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
+       radeon_ring_write(cp, PACKET0(GB_AA_CONFIG, 0));
+       radeon_ring_write(cp, 0);
+       radeon_ring_write(cp, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, RB3D_DC_FLUSH | RB3D_DC_FREE);
+       radeon_ring_write(cp, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
+       radeon_ring_write(cp, ZC_FLUSH | ZC_FREE);
+       radeon_ring_write(cp, PACKET0(GB_MSPOS0, 0));
+       radeon_ring_write(cp,
                          ((6 << MS_X0_SHIFT) |
                           (6 << MS_Y0_SHIFT) |
                           (6 << MS_X1_SHIFT) |
@@ -101,8 +102,8 @@ void rv515_ring_start(struct radeon_device *rdev)
                           (6 << MS_Y2_SHIFT) |
                           (6 << MSBD0_Y_SHIFT) |
                           (6 << MSBD0_X_SHIFT)));
-       radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
-       radeon_ring_write(rdev,
+       radeon_ring_write(cp, PACKET0(GB_MSPOS1, 0));
+       radeon_ring_write(cp,
                          ((6 << MS_X3_SHIFT) |
                           (6 << MS_Y3_SHIFT) |
                           (6 << MS_X4_SHIFT) |
@@ -110,15 +111,15 @@ void rv515_ring_start(struct radeon_device *rdev)
                           (6 << MS_X5_SHIFT) |
                           (6 << MS_Y5_SHIFT) |
                           (6 << MSBD1_SHIFT)));
-       radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
-       radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
-       radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
-       radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
-       radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
-       radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
-       radeon_ring_write(rdev, PACKET0(0x20C8, 0));
-       radeon_ring_write(rdev, 0);
-       radeon_ring_unlock_commit(rdev);
+       radeon_ring_write(cp, PACKET0(GA_ENHANCE, 0));
+       radeon_ring_write(cp, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
+       radeon_ring_write(cp, PACKET0(GA_POLY_MODE, 0));
+       radeon_ring_write(cp, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
+       radeon_ring_write(cp, PACKET0(GA_ROUND_MODE, 0));
+       radeon_ring_write(cp, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
+       radeon_ring_write(cp, PACKET0(0x20C8, 0));
+       radeon_ring_write(cp, 0);
+       radeon_ring_unlock_commit(rdev, cp);
 }
 
 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
index be02bee41213ae50b62067cc5b34835559d80be6..0d0d811fc80b31dc8ddc1e8aa9b7c351242fbc1c 100644 (file)
@@ -357,7 +357,7 @@ static int rv770_cp_load_microcode(struct radeon_device *rdev)
 void r700_cp_fini(struct radeon_device *rdev)
 {
        r700_cp_stop(rdev);
-       radeon_ring_fini(rdev);
+       radeon_ring_fini(rdev, &rdev->cp);
 }
 
 /*
@@ -1043,6 +1043,7 @@ int rv770_mc_init(struct radeon_device *rdev)
 
 static int rv770_startup(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp;
        int r;
 
        /* enable pcie gen2 link */
@@ -1091,7 +1092,7 @@ static int rv770_startup(struct radeon_device *rdev)
        }
        r600_irq_set(rdev);
 
-       r = radeon_ring_init(rdev, rdev->cp.ring_size);
+       r = radeon_ring_init(rdev, cp, cp->ring_size);
        if (r)
                return r;
        r = rv770_cp_load_microcode(rdev);
@@ -1121,7 +1122,7 @@ int rv770_resume(struct radeon_device *rdev)
                return r;
        }
 
-       r = r600_ib_test(rdev);
+       r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
        if (r) {
                DRM_ERROR("radeon: failed testing IB (%d).\n", r);
                return r;
@@ -1216,7 +1217,7 @@ int rv770_init(struct radeon_device *rdev)
                return r;
 
        rdev->cp.ring_obj = NULL;
-       r600_ring_init(rdev, 1024 * 1024);
+       r600_ring_init(rdev, &rdev->cp, 1024 * 1024);
 
        rdev->ih.ring_obj = NULL;
        r600_ih_ring_init(rdev, 64 * 1024);
@@ -1242,7 +1243,7 @@ int rv770_init(struct radeon_device *rdev)
                        dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
                        rdev->accel_working = false;
                } else {
-                       r = r600_ib_test(rdev);
+                       r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
                        if (r) {
                                dev_err(rdev->dev, "IB test failed (%d).\n", r);
                                rdev->accel_working = false;