MIPS: asm: cpu: Add cpu flag for Enhanced Virtual Addressing

The MIPS *Aptiv family uses bit 28 in Config5 CP0 register to
indicate whether the core supports EVA or not.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 390795dfa2e9ae578c6918de03a7ca29958bc631..f56cc975b92f8522ca37e344a9e0146ba6f80bf1 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -26,7 +26,9 @@
 #ifndef cpu_has_segments
 #define cpu_has_segments       (cpu_data[0].options & MIPS_CPU_SEGMENTS)
 #endif
-
+#ifndef cpu_has_eva
+#define cpu_has_eva            (cpu_data[0].options & MIPS_CPU_EVA)
+#endif
 
 /*
  * For the moment we don't consider R6000 and R8000 so we can assume that

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 93c2a0e4424e6af7521050d53ac1e0d275e8442b..c12d99780204f2f5eafe82885ce2ac545964824b 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -359,6 +359,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_MICROMIPS     0x01000000 /* CPU has microMIPS capability */
 #define MIPS_CPU_TLBINV                0x02000000 /* CPU supports TLBINV/F */
 #define MIPS_CPU_SEGMENTS      0x04000000 /* CPU supports Segmentation Control registers */
+#define MIPS_CPU_EVA           0x80000000 /* CPU supports Enhanced Virtual Addressing */
 
 /*
  * CPU ASE encodings