blackfin: cplb: add support for bf60x

Bf60x support big CPLB pages, this commit enable it.

Signed-off-by: Bob Liu <lliubbo@gmail.com>

diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index fda96261ed6239997bc69d94b7bd6f3ef4be42b2..5c37f620c4b3bb6ac6efc395e44d187b669d11ed 100644 (file)
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -62,6 +62,10 @@
 #define SIZE_4K 0x00001000      /* 4K */
 #define SIZE_1M 0x00100000      /* 1M */
 #define SIZE_4M 0x00400000      /* 4M */
+#define SIZE_16K 0x00004000      /* 16K */
+#define SIZE_64K 0x00010000      /* 64K */
+#define SIZE_16M 0x01000000      /* 16M */
+#define SIZE_64M 0x04000000      /* 64M */
 
 #define MAX_CPLBS 16
 

diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 8236790114575eb9e2dc4df8e21c3cbf0413376c..dfcc7e5fdfb39306dc4e3eb01c13dfc7e087d3a4 100644 (file)
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -622,6 +622,10 @@ do { \
 #define PAGE_SIZE_4KB      0x00010000  /* 4 KB page size */
 #define PAGE_SIZE_1MB      0x00020000  /* 1 MB page size */
 #define PAGE_SIZE_4MB      0x00030000  /* 4 MB page size */
+#define PAGE_SIZE_16KB     0x00040000  /* 16 KB page size */
+#define PAGE_SIZE_64KB     0x00050000  /* 64 KB page size */
+#define PAGE_SIZE_16MB     0x00060000  /* 16 MB page size */
+#define PAGE_SIZE_64MB     0x00070000  /* 64 MB page size */
 #define CPLB_L1SRAM        0x00000020  /* 0=SRAM mapped in L1, 0=SRAM not
                                         * mapped to L1
                                         */

diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 886e00014d7514a5a83fa3f5b31c064f53ba12f8..3e366dc2d6e11593fc9a0b986ae3550cf162ec91 100644 (file)
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -139,7 +139,7 @@ void __init generate_cplb_tables_all(void)
        dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
        dcplb_bounds[i_d++].data = 0;
        /* BootROM -- largest one should be less than 1 meg.  */
-       dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+       dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
        dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
        if (L2_LENGTH) {
                /* Addressing hole up to L2 SRAM.  */
@@ -178,7 +178,7 @@ void __init generate_cplb_tables_all(void)
        icplb_bounds[i_i].eaddr = BOOT_ROM_START;
        icplb_bounds[i_i++].data = 0;
        /* BootROM -- largest one should be less than 1 meg.  */
-       icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+       icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
        icplb_bounds[i_i++].data = SDRAM_IGENERIC;
 
        if (L2_LENGTH) {

diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
index 5b88861d6183fbb40653d85a5dfbf11c52145508..e854f9066cbde005413bf0659e59fbed6a3b0423 100644 (file)
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
@@ -179,6 +179,12 @@ MGR_ATTR static int dcplb_miss(int cpu)
                addr = addr1;
        }
 
+#ifdef CONFIG_BF60x
+       if ((addr >= ASYNC_BANK0_BASE)
+               && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
+               d_data |= PAGE_SIZE_64MB;
+#endif
+
        /* Pick entry to evict */
        idx = evict_one_dcplb(cpu);