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ARM: tegra: fix overflow in tegra20_pll_clk_round_rate()
author
Stephen Warren
<swarren@nvidia.com>
Mon, 10 Sep 2012 23:02:45 +0000
(17:02 -0600)
committer
Stephen Warren
<swarren@nvidia.com>
Tue, 11 Sep 2012 16:05:55 +0000
(10:05 -0600)
32-bit math isn't enough when e.g. *prate=
12000000
, and sel->n=1000.
Use 64-bit math to prevent this.
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/mach-tegra/tegra20_clocks.c
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diff --git
a/arch/arm/mach-tegra/tegra20_clocks.c
b/arch/arm/mach-tegra/tegra20_clocks.c
index b9124afcca11336ac50d0b3a6382facb10f0fc19..d9ce0087f6a6f186e03287952d8b21ac0b082020 100644
(file)
--- a/
arch/arm/mach-tegra/tegra20_clocks.c
+++ b/
arch/arm/mach-tegra/tegra20_clocks.c
@@
-789,7
+789,7
@@
static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
struct clk_tegra *c = to_clk_tegra(hw);
const struct clk_pll_freq_table *sel;
unsigned long input_rate = *prate;
- u
nsigned long
output_rate = *prate;
+ u
64
output_rate = *prate;
int mul;
int div;