dt-bindings: PCI: rockchip: Convert to per-lane PHY model

Deprecate legacy PHY model and encourage per-lane PHY model.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>

diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
index 9b889590c0614c1fb66a01c7abea8fec3d3dc621..5678be82530d80fa647eb16317ac94e34366c0e2 100644 (file)
--- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt
@@ -19,8 +19,6 @@ Required properties:
        - "pm"
 - msi-map: Maps a Requester ID to an MSI controller and associated
        msi-specifier data. See ./pci-msi.txt
-- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
-- phy-names:  MUST be "pcie-phy".
 - interrupts: Three interrupt entries must be specified.
 - interrupt-names: Must include the following names
        - "sys"
@@ -42,6 +40,18 @@ Required properties:
        interrupt source. The value must be 1.
 - interrupt-map-mask and interrupt-map: standard PCI properties
 
+Required properties for legacy PHY model (deprecated):
+- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
+- phy-names:  MUST be "pcie-phy".
+
+Required properties for per-lane PHY model (preferred):
+- phys: Must contain an phandle to a PHY for each entry in phy-names.
+- phy-names: Must include 4 entries for all 4 lanes even if some of
+  them won't be used for your cases. Entries are of the form "pcie-phy-N":
+  where N ranges from 0 to 3.
+  (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+  for changing the #phy-cells of phy node to support it)
+
 Optional Property:
 - aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
        using 24MHz OSC for RC's PHY.
@@ -96,6 +106,7 @@ pcie0: pcie@f8000000 {
                 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
        reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
                      "pm", "pclk", "aclk";
+       /* deprecated legacy PHY model */
        phys = <&pcie_phy>;
        phy-names = "pcie-phy";
        pinctrl-names = "default";
@@ -112,3 +123,13 @@ pcie0: pcie@f8000000 {
                #interrupt-cells = <1>;
        };
 };
+
+pcie0: pcie@f8000000 {
+       ...
+
+       /* preferred per-lane PHY model */
+       phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
+       phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
+
+       ...
+};