spi: fsl-espi: Fix an error that can cause fsl espi task blocked

Incorrect condition is used in spin_event_timeout().  When the TX is
done, the SPIE_NF bit in ESPI_SPIE register is set to 1 to indicate the
Tx FIFO is not full.  If the bit is 0, it indicates the Tx FIFO is full.

Due to this error, if the Tx FIFO is full at the beginning, but becomes
not full after handling the Rx FIFO (the SPIE_NF bit is set), the
spin_event_timeout() returns with timeout occurred.  It causes the
interrupt handler not to send completion notification to the thread that
called wait_for_complete() waiting for the notification.

Signed-off-by: Jane Wan <Jane.Wan@gainspeed.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index d0a73a09a9bd3e02371a30bc4b5ceb34f6b52e4e..a0dbb51630d9e0d5efa3699b28584dddf0d3ca2e 100644 (file)
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -544,9 +544,13 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 
                /* spin until TX is done */
                ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
-                               &reg_base->event)) & SPIE_NF) == 0, 1000, 0);
+                               &reg_base->event)) & SPIE_NF), 1000, 0);
                if (!ret) {
                        dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
+
+                       /* Clear the SPIE bits */
+                       mpc8xxx_spi_write_reg(&reg_base->event, events);
+                       complete(&mspi->done);
                        return;
                }
        }