drm/nvc0/ltcg: mask off intr 0x10
authorBen Skeggs <bskeggs@redhat.com>
Wed, 26 Sep 2012 02:43:10 +0000 (12:43 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 26 Sep 2012 02:43:10 +0000 (12:43 +1000)
NVIDIA do that at startup too on Fermi, so perhaps the heap of 0x10
intrs we receive are normal and we can ignore them.

On Kepler NVIDIA *don't* do this, but the hardware appears to come up
with the bit masked off by default - so that's probably why :)

This should silence some interrupt spam seen on Fermi+ boards.

Backported patch from reworked nouveau kernel tree.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvc0_fb.c

index f704e942372e75b291cc505536a197c4c464a537..f376c39310dfb11e00a944577aba9209e4481451 100644 (file)
@@ -124,6 +124,7 @@ nvc0_fb_init(struct drm_device *dev)
        priv = dev_priv->engine.fb.priv;
 
        nv_wr32(dev, 0x100c10, priv->r100c10 >> 8);
+       nv_mask(dev, 0x17e820, 0x00100000, 0x00000000); /* NV_PLTCG_INTR_EN */
        return 0;
 }