drm/i915: Enable HPLL watermarks on g4x

I don't see why we couldn't use the HPLL watermarks on g4x. So let's
enable them. Let's assume a 35 usec memory latency for the HPLL mode.
That's roughly what PNV uses.

Based on the behaviour of the ELK box I have 35 usec is probably
overkill. Actually all the current latency values used seem overkill as
I can reduce them pretty drastically before I start to see underruns.
But let's play things a bit safe for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170421181432.15216-14-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9b0a6a4572cefc60e2aa00ecaf8d4c0763debada..957ef10b156918e1874ec03ed1fa132115ec5495 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1020,8 +1020,9 @@ static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
        /* all latencies in usec */
        dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
        dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
+       dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
 
-       dev_priv->wm.max_level = G4X_WM_LEVEL_SR;
+       dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
 }
 
 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)