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perf/x86: Fix P6 FP_ASSIST event constraint
author
Vince Weaver
<vincent.weaver@maine.edu>
Fri, 19 Oct 2012 21:30:01 +0000
(17:30 -0400)
committer
Ingo Molnar
<mingo@kernel.org>
Wed, 24 Oct 2012 08:31:57 +0000
(10:31 +0200)
According to Intel SDM Volume 3B, FP_ASSIST is limited to Counter 1 only,
not Counter 0.
Tested on a Pentium II.
Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link:
http://lkml.kernel.org/r/alpine.DEB.2.02.1210191728570.14552@vincent-weaver-1.um.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event_p6.c
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diff --git
a/arch/x86/kernel/cpu/perf_event_p6.c
b/arch/x86/kernel/cpu/perf_event_p6.c
index e4dd0f7a04535f09b83d47d95868bcc1c152dff3..0ff5f7fb64cd1e1161b21a18fa1a5f950620f04d 100644
(file)
--- a/
arch/x86/kernel/cpu/perf_event_p6.c
+++ b/
arch/x86/kernel/cpu/perf_event_p6.c
@@
-34,7
+34,7
@@
static struct event_constraint p6_event_constraints[] =
{
INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
- INTEL_EVENT_CONSTRAINT(0x11, 0x
1
), /* FP_ASSIST */
+ INTEL_EVENT_CONSTRAINT(0x11, 0x
2
), /* FP_ASSIST */
INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */