clk: samsung: register clk_div_tables for divider clocks
authorHeiko Stuebner <heiko@sntech.de>
Mon, 18 Mar 2013 04:43:52 +0000 (13:43 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Thu, 28 Mar 2013 05:46:03 +0000 (14:46 +0900)
On some Samsung platforms divider clocks only use specific divider
combinations like the armdiv on s3c2443 and s3c2416. For these
usecases the generic divider clock already provides the option of
providing a lookup table mapping register values to divider values.

Therefore add a new field to samsung_div_clock and if filled with a
table, use clk_register_divider_table instead of clk_register_divider
to register a divider clock

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
drivers/clk/samsung/clk.c
drivers/clk/samsung/clk.h

index 91d12f397f5d70e8bfee251fb32d609c199f809e..d36cdd511761952b66dc06147abe95857e5f600e 100644 (file)
@@ -183,9 +183,17 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list,
        unsigned int idx, ret;
 
        for (idx = 0; idx < nr_clk; idx++, list++) {
-               clk = clk_register_divider(NULL, list->name, list->parent_name,
-                       list->flags, reg_base + list->offset, list->shift,
-                       list->width, list->div_flags, &lock);
+               if (list->table)
+                       clk = clk_register_divider_table(NULL, list->name,
+                                       list->parent_name, list->flags,
+                                       reg_base + list->offset, list->shift,
+                                       list->width, list->div_flags,
+                                       list->table, &lock);
+               else
+                       clk = clk_register_divider(NULL, list->name,
+                                       list->parent_name, list->flags,
+                                       reg_base + list->offset, list->shift,
+                                       list->width, list->div_flags, &lock);
                if (IS_ERR(clk)) {
                        pr_err("%s: failed to register clock %s\n", __func__,
                                list->name);
index 961192ffd69636a1d5f4ded0fd9740f0fb02dbf2..26a752b18f88c27092ceced42f3ee70b58dd67b8 100644 (file)
@@ -150,9 +150,10 @@ struct samsung_div_clock {
        u8                      width;
        u8                      div_flags;
        const char              *alias;
+       struct clk_div_table    *table;
 };
 
-#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a)     \
+#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t)  \
        {                                                       \
                .id             = _id,                          \
                .dev_name       = dname,                        \
@@ -164,16 +165,20 @@ struct samsung_div_clock {
                .width          = w,                            \
                .div_flags      = df,                           \
                .alias          = a,                            \
+               .table          = t,                            \
        }
 
 #define DIV(_id, cname, pname, o, s, w)                                \
-       __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL)
+       __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
 
 #define DIV_A(_id, cname, pname, o, s, w, a)                   \
-       __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a)
+       __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
 
 #define DIV_F(_id, cname, pname, o, s, w, f, df)               \
-       __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL)
+       __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
+
+#define DIV_T(_id, cname, pname, o, s, w, t)                   \
+       __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
 
 /**
  * struct samsung_gate_clock: information about gate clock