drm/i915: enable display messages to GT on ValleyView

Enable the on-chip messaging between the display engine and the GT.

v2: use bit definitions for DPFLIPSTAT reg

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f075139ed9b8fcccab0b01c5e5e59cd3ce511bff..0a61481cd2c2ad3396aec8ec3ac3a98a888173a4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2653,13 +2653,13 @@
 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
 
 #define VLV_DPFLIPSTAT                         0x70028
-#define   PIPEB_LINE_COMPARE_STATUS            (1<<29)
+#define   PIPEB_LINE_COMPARE_INT_EN            (1<<29)
 #define   PIPEB_HLINE_INT_EN                   (1<<28)
 #define   PIPEB_VBLANK_INT_EN                  (1<<27)
 #define   SPRITED_FLIPDONE_INT_EN              (1<<26)
 #define   SPRITEC_FLIPDONE_INT_EN              (1<<25)
 #define   PLANEB_FLIPDONE_INT_EN               (1<<24)
-#define   PIPEA_LINE_COMPARE_STATUS            (1<<21)
+#define   PIPEA_LINE_COMPARE_INT_EN            (1<<21)
 #define   PIPEA_HLINE_INT_EN                   (1<<20)
 #define   PIPEA_VBLANK_INT_EN                  (1<<19)
 #define   SPRITEB_FLIPDONE_INT_EN              (1<<18)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 17c16f0262442b46bc863c4b4a691c2b46f026d8..7504fbce05cc1e0e49288c0d9031ee8b944a8c9d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3528,6 +3528,19 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 
        I915_WRITE(CACHE_MODE_1,
                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+
+       /*
+        * On ValleyView, the GUnit needs to signal the GT
+        * when flip and other events complete.  So enable
+        * all the GUnit->GT interrupts here
+        */
+       I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
+                  PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
+                  SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
+                  PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
+                  PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
+                  SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
+                  PLANEA_FLIPDONE_INT_EN);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)