IB/mlx5: Allow posting multi packet send WQEs if hardware supports
authorBodong Wang <bodong@mellanox.com>
Thu, 17 Aug 2017 12:52:34 +0000 (15:52 +0300)
committerDoug Ledford <dledford@redhat.com>
Thu, 24 Aug 2017 21:47:35 +0000 (17:47 -0400)
Set the field to allow posting multi packet send WQEs if hardware
supports this feature. This doesn't mean the send WQEs will be for
multi packet unless the send WQE was prepared according to multi
packet send WQE format.

User space shall use flag MLX5_IB_ALLOW_MPW to check if hardware
supports MPW and allows MPW in SQ context.

Signed-off-by: Bodong Wang <bodong@mellanox.com>
Reviewed-by: Daniel Jurgens <danielj@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>
drivers/infiniband/hw/mlx5/main.c
drivers/infiniband/hw/mlx5/qp.c
include/linux/mlx5/mlx5_ifc.h
include/uapi/rdma/mlx5-abi.h

index 8f7e46090f9a5b3f5303b597184b192ef86eeb78..ba0a97d6f6772a71bfa0a3585b1268172a27caaa 100644 (file)
@@ -802,8 +802,9 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
 
        if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
                        uhw->outlen)) {
-               resp.mlx5_ib_support_multi_pkt_send_wqes =
-                       MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
+               if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
+                       resp.mlx5_ib_support_multi_pkt_send_wqes =
+                               MLX5_IB_ALLOW_MPW;
                resp.response_length +=
                        sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
        }
index 656773196f275b677877475ed671a86d5a5ba6ee..d6df88a78d5e12edd6f461eae9f8d766e2c1931c 100644 (file)
@@ -1083,6 +1083,8 @@ static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
 
        sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
        MLX5_SET(sqc, sqc, flush_in_error_en, 1);
+       if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
+               MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
        MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
        MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
        MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
index 6563500c85dee6e9571db7ef29956cde31f01a91..6865e60ba4733c695921d5931d327494a84f04dc 100644 (file)
@@ -2445,7 +2445,7 @@ struct mlx5_ifc_sqc_bits {
        u8         cd_master[0x1];
        u8         fre[0x1];
        u8         flush_in_error_en[0x1];
-       u8         reserved_at_4[0x1];
+       u8         allow_multi_pkt_send_wqe[0x1];
        u8         min_wqe_inline_mode[0x3];
        u8         state[0x4];
        u8         reg_umr[0x1];
index 64d398e662cd32034a7f790c02cbbff223b326eb..a61a512e57479a964983790bf9851c6ba97cac9f 100644 (file)
@@ -168,6 +168,11 @@ struct mlx5_packet_pacing_caps {
        __u32 reserved;
 };
 
+enum mlx5_ib_mpw_caps {
+       MPW_RESERVED            = 1 << 0,
+       MLX5_IB_ALLOW_MPW       = 1 << 1,
+};
+
 enum mlx5_ib_sw_parsing_offloads {
        MLX5_IB_SW_PARSING = 1 << 0,
        MLX5_IB_SW_PARSING_CSUM = 1 << 1,