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arm64: dts: rockchip: add reset saradc node for rk3368 SoCs
authorCaesar Wang <wxt@rock-chips.com>
Wed, 27 Jul 2016 14:24:06 +0000 (22:24 +0800)
committerJonathan Cameron <jic23@kernel.org>
Tue, 23 Aug 2016 18:08:21 +0000 (19:08 +0100)
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
arch/arm64/boot/dts/rockchip/rk3368.dtsi patch | blob | blame | history

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index d02a900378e1037f8750ac3f993dc6be58c61aeb..4f44d1191bfd348f2969339d557141d43da278cf 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -270,6 +270,8 @@
                #io-channel-cells = <1>;
                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
                clock-names = "saradc", "apb_pclk";
+               resets = <&cru SRST_SARADC>;
+               reset-names = "saradc-apb";
                status = "disabled";
        };