drm/nouveau/pm: some more delays for ddr3 reclocking

These numbers from the binary driver's daemon scripts, and fix the transition
to perflvl 3 on my T510.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index ec4c53f411717e62ce27b67e1c467ce7e5212971..585dcbeafcdafdcfdbda9e51dd1bcb29e01dc1e9 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -978,6 +978,8 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
                break;
        case NV_MEM_TYPE_DDR3:
                tDLLK = 12000;
+               tCKSRE = 2000;
+               tXS = 1000;
                mr1_dlloff = 0x00000001;
                break;
        case NV_MEM_TYPE_GDDR3:
@@ -1024,6 +1026,7 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
        exec->refresh_self(exec, false);
        exec->refresh_auto(exec, true);
        exec->wait(exec, tXS);
+       exec->wait(exec, tXS);
 
        /* update MRs */
        if (mr[2] != info->mr[2]) {

diff --git a/drivers/gpu/drm/nouveau/nva3_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c
index d51e8f86b4d5bdd783993a9658d02075b7fca0eb..798829353fb6b14e2d17decc1c88054cb4fb10f7 100644 (file)
--- a/drivers/gpu/drm/nouveau/nva3_pm.c
+++ b/drivers/gpu/drm/nouveau/nva3_pm.c
@@ -344,6 +344,7 @@ mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
 static void
 mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
 {
+       volatile u32 post = nv_rd32(exec->dev, 0); (void)post;
        udelay((nsec + 500) / 1000);
 }