break;
}
if (!tries)
- printk(KERN_WARNING "Timeout waiting for end of frame "
- "-- LCD may not be available\n");
+ pr_err("Timeout waiting for end of frame -- LCD may not be available\n");
/* turn off DMA */
reg = omap_readw(OMAP_DMA_LCD_CCR);
/* Clocks in the DSP domain need api_ck. Just assume bootloader
* has not enabled any DSP clocks */
if (clk->enable_reg == DSP_IDLECT2) {
- printk(KERN_INFO "Skipping reset check for DSP domain "
- "clock \"%s\"\n", clk->name);
+ pr_info("Skipping reset check for DSP domain clock \"%s\"\n",
+ clk->name);
return;
}
static void __init omap1_show_rates(void)
{
- pr_notice("Clocking rate (xtal/DPLL1/MPU): "
- "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
- ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
- ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
- arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
+ pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
+ ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+ ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+ arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
}
u32 cpu_mask;
if (cpu_is_omap16xx() && crystal_type == 2)
ck_ref.rate = 19200000;
- pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
- "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+ pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
+ omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
omap_readw(ARM_CKCTL));
/* We want to be in syncronous scalable mode */
d->chan = kzalloc(sizeof(struct omap_dma_lch) *
(d->lch_count), GFP_KERNEL);
if (!d->chan) {
- dev_err(&pdev->dev, "%s: Memory allocation failed"
- "for d->chan!!!\n", __func__);
+ dev_err(&pdev->dev,
+ "%s: Memory allocation failed for d->chan!\n",
+ __func__);
goto exit_release_d;
}
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
if (cpu_is_omap15xx()) {
- printk(KERN_ERR "DMA virtual resolution is not supported "
- "in 1510 mode\n");
+ pr_err("DMA virtual resolution is not supported in 1510 mode\n");
BUG();
}
lcd_dma.vxres = vxres;
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0)
- printk(KERN_ERR "unable to request IRQ for LCD DMA "
- "(error %d)\n", r);
+ pr_err("unable to request IRQ for LCD DMA (error %d)\n", r);
return r;
}
ret = menelaus_set_regulator_sleep(1, val);
if (ret < 0) {
- printk(KERN_ERR "Could not set regulators to sleep on "
- "menelaus: %u\n", ret);
+ pr_err("Could not set regulators to sleep on menelaus: %u\n",
+ ret);
return ret;
}
return 0;
ret = menelaus_set_vcore_hw(1400, 1050);
if (ret < 0) {
- printk(KERN_ERR "Could not set VCORE voltage on "
- "menelaus: %u\n", ret);
+ pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
return ret;
}
return 0;
udelay(10);
gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
} else {
- printk(KERN_ERR "could not obtain gpio for "
- "OVERO_GPIO_W2W_NRESET\n");
+ pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n");
}
ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
if (ret == 0)
gpio_export(OVERO_GPIO_USBH_CPEN, 0);
else
- printk(KERN_ERR "could not obtain gpio for "
- "OVERO_GPIO_USBH_CPEN\n");
+ pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n");
}
MACHINE_START(OVERO, "Gumstix Overo")
quart_cs = ZOOM_QUADUART_CS;
if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
- printk(KERN_ERR "Failed to request GPMC mem"
- "for Quad UART(TL16CP754C)\n");
+ pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n");
return;
}
if (gpio_request_one(debug_board_detect, GPIOF_IN,
"Zoom debug board detect") < 0) {
- printk(KERN_ERR "Failed to request GPIO%d for Zoom debug"
- "board detect\n", debug_board_detect);
+ pr_err("Failed to request GPIO%d for Zoom debug board detect\n",
+ debug_board_detect);
return 0;
}
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
validrate);
- pr_debug("clock: SDRC CS0 timing params used:"
- " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+ pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
if (sdrc_cs1)
- pr_debug("clock: SDRC CS1 timing params used: "
- " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
- sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
- sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+ pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+ sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+ sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
if (sdrc_cs1)
omap3_configure_core_dpll(
if (!clks->parent) {
/* This indicates a data problem */
- WARN(1, "clock: Could not find parent clock %s in clksel array "
- "of clock %s\n", src_clk->name, clk->name);
+ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
+ clk->name, src_clk->name);
return NULL;
}
if (max_div == 0) {
/* This indicates an error in the clksel data */
- WARN(1, "clock: Could not find divisor for clock %s parent %s"
- "\n", clk->name, src_clk->parent->name);
+ WARN(1, "clock: %s: could not find divisor for parent %s\n",
+ clk->name, src_clk->parent->name);
return 0;
}
if (!clkr->div) {
/* This indicates a data error */
- WARN(1, "clock: Could not find fieldval %d for clock %s parent "
- "%s\n", field_val, clk->name, clk->parent->name);
+ WARN(1, "clock: %s: could not find fieldval %d parent %s\n",
+ clk->name, field_val, clk->parent->name);
return 0;
}
}
if (!clkr->div) {
- pr_err("clock: Could not find divisor %d for clock %s parent "
- "%s\n", div, clk->name, clk->parent->name);
+ pr_err("clock: %s: could not find divisor %d parent %s\n",
+ clk->name, div, clk->parent->name);
return ~0;
}
/* Sanity check */
if (clkr->div <= last_div)
- pr_err("clock: clksel_rate table not sorted "
- "for clock %s", clk->name);
+ pr_err("clock: %s: clksel_rate table not sorted",
+ clk->name);
last_div = clkr->div;
}
if (!clkr->div) {
- pr_err("clock: Could not find divisor for target "
- "rate %ld for clock %s parent %s\n", target_rate,
- clk->name, clk->parent->name);
+ pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n",
+ clk->name, target_rate, clk->parent->name);
return ~0;
}
if (clkr->val == r) {
if (clk->parent != clks->parent) {
- pr_debug("clock: inited %s parent "
- "to %s (was %s)\n",
+ pr_debug("clock: %s: inited parent to %s (was %s)\n",
clk->name, clks->parent->name,
((clk->parent) ?
clk->parent->name : "NULL"));
}
if (fint < fint_min) {
- pr_debug("rejecting n=%d due to Fint failure, "
- "lowering max_divider\n", n);
+ pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
+ n);
dd->max_divider = n;
ret = DPLL_FINT_UNDERFLOW;
} else if (fint > fint_max) {
- pr_debug("rejecting n=%d due to Fint failure, "
- "boosting min_divider\n", n);
+ pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
+ n);
dd->min_divider = n;
ret = DPLL_FINT_INVALID;
} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
clk->name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
- pr_debug("clock: could not associate clk %s to "
- "clkdm %s\n", clk->name, clk->clkdm_name);
+ pr_debug("clock: could not associate clk %s to clkdm %s\n",
+ clk->name, clk->clkdm_name);
}
}
* 'Independent' here refers to a clock which is not
* controlled by its parent.
*/
- printk(KERN_ERR "clock: clk_disable called on independent "
- "clock %s which has no enable_reg\n", clk->name);
+ pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
return;
}
void omap2_clk_disable(struct clk *clk)
{
if (clk->usecount == 0) {
- WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
- "already 0?", clk->name);
+ WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
return;
}
if (clkdm_control && clk->clkdm) {
ret = clkdm_clk_enable(clk->clkdm, clk);
if (ret) {
- WARN(1, "clock: %s: could not enable clockdomain %s: "
- "%d\n", clk->name, clk->clkdm->name, ret);
+ WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
+ clk->name, clk->clkdm->name, ret);
goto oce_err2;
}
}
hfclkin_rate = clk_get_rate(hfclkin_ck);
- pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
- "%ld.%01ld/%ld/%ld MHz\n",
- (hfclkin_rate / 1000000),
- ((hfclkin_rate / 100000) % 10),
+ pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
(clk_get_rate(core_ck) / 1000000),
(clk_get_rate(mpu_ck) / 1000000));
}
* on DPLL4.
*/
if (omap_rev() == OMAP3430_REV_ES1_0) {
- pr_err("clock: DPLL4 cannot change rate due to "
- "silicon 'Limitation 2.5' on 3430ES1.\n");
+ pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
return -EINVAL;
}
if (IS_ERR(autodep->clkdm.ptr))
continue;
- pr_debug("clockdomain: adding %s sleepdep/wkdep for "
- "clkdm %s\n", autodep->clkdm.ptr->name,
- clkdm->name);
+ pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
+ clkdm->name, autodep->clkdm.ptr->name);
clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
if (IS_ERR(autodep->clkdm.ptr))
continue;
- pr_debug("clockdomain: removing %s sleepdep/wkdep for "
- "clkdm %s\n", autodep->clkdm.ptr->name,
- clkdm->name);
+ pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
+ clkdm->name, autodep->clkdm.ptr->name);
clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear wake up of "
- "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
- pr_debug("clockdomain: hardware will wake up %s when %s wakes "
- "up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
+ clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
}
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear wake up of "
- "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
- pr_debug("clockdomain: hardware will no longer wake up %s "
- "after %s wakes up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
+ clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
}
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear wake up of "
- "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear sleep "
- "dependency affecting %s from %s\n", clkdm1->name,
- clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
- pr_debug("clockdomain: will prevent %s from sleeping if %s "
- "is active\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
+ clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
}
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear sleep "
- "dependency affecting %s from %s\n", clkdm1->name,
- clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
- pr_debug("clockdomain: will no longer prevent %s from "
- "sleeping if %s is active\n", clkdm1->name,
- clkdm2->name);
+ pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
+ clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
}
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear sleep "
- "dependency affecting %s from %s\n", clkdm1->name,
- clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
return -EINVAL;
if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
- pr_debug("clockdomain: %s does not support forcing "
- "sleep via software\n", clkdm->name);
+ pr_debug("clockdomain: %s does not support forcing sleep via software\n",
+ clkdm->name);
return -EINVAL;
}
return -EINVAL;
if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
- pr_debug("clockdomain: %s does not support forcing "
- "wakeup via software\n", clkdm->name);
+ pr_debug("clockdomain: %s does not support forcing wakeup via software\n",
+ clkdm->name);
return -EINVAL;
}
return;
if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
- pr_debug("clock: automatic idle transitions cannot be enabled "
- "on clockdomain %s\n", clkdm->name);
+ pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
+ clkdm->name);
return;
}
return;
if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
- pr_debug("clockdomain: automatic idle transitions cannot be "
- "disabled on %s\n", clkdm->name);
+ pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
+ clkdm->name);
return;
}
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
- pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+ pr_debug("clockdomain: %s: enabled\n", clkdm->name);
return 0;
}
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
- pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+ pr_debug("clockdomain: %s: disabled\n", clkdm->name);
return 0;
}
}
if (nandcs > GPMC_CS_NUM) {
- printk(KERN_INFO "NAND: Unable to find configuration "
- "in GPMC\n ");
+ pr_info("NAND: Unable to find configuration in GPMC\n");
return;
}
}
if (j == ARRAY_SIZE(omap_ids)) {
- printk(KERN_ERR "Unknown OMAP device type. "
- "Handling it as OMAP%04x\n",
- omap_ids[i].type >> 16);
+ pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
+ omap_ids[i].type >> 16);
j = i;
}
unsigned long tmp;
tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
- printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
- "(revision %ld.%ld) with %d interrupts\n",
- bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
+ pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
+ bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
tmp |= 1 << 1; /* soft reset */
/* clocks must be on for this operation */
if (oh->_state != _HWMOD_STATE_ENABLED) {
- pr_warning("omap_hwmod: %s: reset can only be entered from "
- "enabled state\n", oh->name);
+ pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
+ oh->name);
return -EINVAL;
}
}
oh = omap_hwmod_lookup(opp_def->hwmod_name);
if (!oh || !oh->od) {
- pr_debug("%s: no hwmod or odev for %s, [%d] "
- "cannot add OPPs.\n", __func__,
- opp_def->hwmod_name, i);
+ pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n",
+ __func__, opp_def->hwmod_name, i);
continue;
}
dev = &oh->od->pdev->dev;
r = opp_add(dev, opp_def->freq, opp_def->u_volt);
if (r) {
- dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
- "result=%d\n",
- __func__, opp_def->freq,
- opp_def->hwmod_name, i, r);
+ dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n",
+ __func__, opp_def->freq,
+ opp_def->hwmod_name, i, r);
} else {
if (!opp_def->default_available)
r = opp_disable(dev, opp_def->freq);
if (r)
- dev_err(dev, "%s: disable %ld failed for %s "
- "[%d] result=%d\n",
+ dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n",
__func__, opp_def->freq,
opp_def->hwmod_name, i, r);
}
bootup_volt = opp_get_voltage(opp);
rcu_read_unlock();
if (!bootup_volt) {
- pr_err("%s: unable to find voltage corresponding "
- "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+ pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
+ __func__, vdd_name);
goto exit;
}
list_for_each_entry(pwrst, &pwrst_list, node) {
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
if (state > pwrst->next_state) {
- pr_info("Powerdomain (%s) didn't enter "
- "target state %d\n",
- pwrst->pwrdm->name, pwrst->next_state);
+ pr_info("Powerdomain (%s) didn't enter target state %d\n",
+ pwrst->pwrdm->name, pwrst->next_state);
ret = -1;
}
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
omap3_secure_ram_storage =
kmalloc(0x803F, GFP_KERNEL);
if (!omap3_secure_ram_storage)
- pr_err("Memory allocation failed when "
- "allocating for secure sram context\n");
+ pr_err("Memory allocation failed when allocating for secure sram context\n");
local_irq_disable();
local_fiq_disable();
list_for_each_entry(pwrst, &pwrst_list, node) {
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
if (state > pwrst->next_state) {
- pr_info("Powerdomain (%s) didn't enter "
- "target state %d\n",
- pwrst->pwrdm->name, pwrst->next_state);
+ pr_info("Powerdomain (%s) didn't enter target state %d\n",
+ pwrst->pwrdm->name, pwrst->next_state);
ret = -1;
}
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
if (ret) {
- pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
- "wakeup dependency\n");
+ pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
goto err2;
}
if (!pwrdm || !clkdm)
return -EINVAL;
- pr_debug("powerdomain: associating clockdomain %s with powerdomain "
- "%s\n", clkdm->name, pwrdm->name);
+ pr_debug("powerdomain: %s: associating clockdomain %s\n",
+ pwrdm->name, clkdm->name);
for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
if (!pwrdm->pwrdm_clkdms[i])
}
if (i == PWRDM_MAX_CLKDMS) {
- pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
- "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
+ pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS for clkdm %s\n",
+ pwrdm->name, clkdm->name);
WARN_ON(1);
ret = -ENOMEM;
goto pac_exit;
if (!pwrdm || !clkdm)
return -EINVAL;
- pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
- "%s\n", clkdm->name, pwrdm->name);
+ pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
+ pwrdm->name, clkdm->name);
for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
if (pwrdm->pwrdm_clkdms[i] == clkdm)
break;
if (i == PWRDM_MAX_CLKDMS) {
- pr_debug("powerdomain: clkdm %s not associated with pwrdm "
- "%s ?!\n", clkdm->name, pwrdm->name);
+ pr_debug("powerdomain: %s: clkdm %s not associated?!\n",
+ pwrdm->name, clkdm->name);
ret = -ENOENT;
goto pdc_exit;
}
if (!(pwrdm->pwrsts & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
+ pr_debug("powerdomain: %s: setting next powerstate to %0x\n",
pwrdm->name, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
+ pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n",
pwrdm->name, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next memory powerstate for domain %s "
- "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
+ pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-ON to %0x\n",
+ pwrdm->name, bank, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next memory powerstate for domain %s "
- "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
+ pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-RET to %0x\n",
+ pwrdm->name, bank, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
* warn & fail if it is not ON.
*/
- pr_debug("powerdomain: clearing previous power state reg for %s\n",
+ pr_debug("powerdomain: %s: clearing previous power state reg\n",
pwrdm->name);
if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
return ret;
- pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
- pwrdm->name);
+ pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name);
if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
return ret;
- pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
- pwrdm->name);
+ pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name);
if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
udelay(1);
if (c > PWRDM_TRANSITION_BAILOUT) {
- printk(KERN_ERR "powerdomain: waited too long for "
- "powerdomain %s to complete transition\n", pwrdm->name);
+ pr_err("powerdomain: %s: waited too long to complete transition\n",
+ pwrdm->name);
return -EAGAIN;
}
udelay(1);
if (c > PWRDM_TRANSITION_BAILOUT) {
- printk(KERN_ERR "powerdomain: waited too long for "
- "powerdomain %s to complete transition\n", pwrdm->name);
+ pr_err("powerdomain: %s: waited too long to complete transition\n",
+ pwrdm->name);
return -EAGAIN;
}
MAX_MODULE_ENABLE_WAIT, i);
if (i < MAX_MODULE_ENABLE_WAIT)
- pr_debug("cm: Module associated with clock %s ready after %d "
- "loops\n", name, i);
+ pr_debug("cm: Module associated with clock %s ready after %d loops\n",
+ name, i);
else
- pr_err("cm: Module associated with clock %s didn't enable in "
- "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+ pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
+ name, MAX_MODULE_ENABLE_WAIT);
return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
};
if (console_loglevel >= 10) {
uart_debug = true;
- pr_info("%s used as console in debug mode"
- " uart%d clocks will not be"
- " gated", uart_name, uart->num);
+ pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
+ uart_name, uart->num);
}
if (cmdline_find_option("no_console_suspend"))
sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL);
if (!sr_data) {
- pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n",
- __func__, oh->name);
+ pr_err("%s: Unable to allocate memory for %s sr_data\n",
+ __func__, oh->name);
return -ENOMEM;
}
sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
- pr_err("%s: No voltage domain specified for %s."
- "Cannot initialize\n", __func__,
- oh->name);
+ pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
+ __func__, oh->name);
goto exit;
}
omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
if (!volt_data) {
- pr_warning("%s: No Voltage table registered fo VDD%d."
- "Something really wrong\n\n", __func__, i + 1);
+ pr_err("%s: No Voltage table registered for VDD%d\n",
+ __func__, i + 1);
goto exit;
}
}
if (!voltdm->pmic->uv_to_vsel) {
- pr_err("%s: PMIC function to convert voltage in uV to"
- "vsel not registered. Hence unable to scale voltage"
- "for vdd_%s\n", __func__, voltdm->name);
+ pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
+ __func__, voltdm->name);
return -ENODATA;
}
return &voltdm->volt_data[i];
}
- pr_notice("%s: Unable to match the current voltage with the voltage"
- "table for vdd_%s\n", __func__, voltdm->name);
+ pr_notice("%s: Unable to match the current voltage with the voltage table for vdd_%s\n",
+ __func__, voltdm->name);
return ERR_PTR(-ENODATA);
}
voltdm->scale = omap_vc_bypass_scale;
return;
default:
- pr_warning("%s: Trying to change the method of voltage scaling"
- "to an unsupported one!\n", __func__);
+ pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n",
+ __func__);
}
}
if (!voltdm || !pwrdm)
return -EINVAL;
- pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
- "%s\n", pwrdm->name, voltdm->name);
+ pr_debug("voltagedomain: %s: associating powerdomain %s\n",
+ voltdm->name, pwrdm->name);
list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
udelay(1);
}
if (timeout >= VP_TRANXDONE_TIMEOUT) {
- pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
- "Voltage change aborted", __func__, voltdm->name);
+ pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted",
+ __func__, voltdm->name);
return -ETIMEDOUT;
}
omap_test_timeout(vp->common->ops->check_txdone(vp->id),
VP_TRANXDONE_TIMEOUT, timeout);
if (timeout >= VP_TRANXDONE_TIMEOUT)
- pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
- "TRANXDONE never got set after the voltage update\n",
- __func__, voltdm->name);
+ pr_err("%s: vdd_%s TRANXDONE timeout exceeded. TRANXDONE never got set after the voltage update\n",
+ __func__, voltdm->name);
omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
}
if (timeout >= VP_TRANXDONE_TIMEOUT)
- pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
- "to clear the TRANXDONE status\n",
+ pr_warn("%s: vdd_%s TRANXDONE timeout exceeded while trying to clear the TRANXDONE status\n",
__func__, voltdm->name);
/* Clear force bit */
/* If VP is already disabled, do nothing. Return */
if (!vp->enabled) {
- pr_warning("%s: Trying to disable VP for vdd_%s when"
- "it is already disabled\n", __func__, voltdm->name);
+ pr_warn("%s: Trying to disable VP for vdd_%s when it is already disabled\n",
+ __func__, voltdm->name);
return;
}
l = p->dma_read(CCR, lch);
}
if (i >= 100)
- printk(KERN_ERR "DMA drain did not complete on "
- "lch %d\n", lch);
+ pr_err("DMA drain did not complete on lch %d\n", lch);
/* Restore OCP_SYSCONFIG */
p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
} else {
if ((dma_chan[lch_head].dev_id == -1) ||
(dma_chan[lch_queue].dev_id == -1)) {
- printk(KERN_ERR "omap_dma: trying to link "
- "non requested channels\n");
+ pr_err("omap_dma: trying to link non requested channels\n");
dump_stack();
}
if (dma_chan[lch_head].next_lch != lch_queue ||
dma_chan[lch_head].next_lch == -1) {
- printk(KERN_ERR "omap_dma: trying to unlink "
- "non linked channels\n");
+ pr_err("omap_dma: trying to unlink non linked channels\n");
dump_stack();
}
if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
(dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
- printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
- "before unlinking\n");
+ pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
dump_stack();
}
if ((csr & 0x3f) == 0)
return 0;
if (unlikely(dma_chan[ch].dev_id == -1)) {
- printk(KERN_WARNING "Spurious interrupt from DMA channel "
- "%d (CSR %04x)\n", ch, csr);
+ pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
+ ch, csr);
return 0;
}
if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
- printk(KERN_WARNING "DMA timeout with device %d\n",
- dma_chan[ch].dev_id);
+ pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
if (unlikely(csr & OMAP_DMA_DROP_IRQ))
- printk(KERN_WARNING "DMA synchronization event drop occurred "
- "with device %d\n", dma_chan[ch].dev_id);
+ pr_warn("DMA synchronization event drop occurred with device %d\n",
+ dma_chan[ch].dev_id);
if (likely(csr & OMAP_DMA_BLOCK_IRQ))
dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
if (likely(dma_chan[ch].callback != NULL))
if (!status) {
if (printk_ratelimit())
- printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
- ch);
+ pr_warn("Spurious DMA IRQ for lch %d\n", ch);
p->dma_write(1 << ch, IRQSTATUS_L0, ch);
return 0;
}
if (unlikely(dma_chan[ch].dev_id == -1)) {
if (printk_ratelimit())
- printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
- "channel %d\n", status, ch);
+ pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
+ status, ch);
return 0;
}
if (unlikely(status & OMAP_DMA_DROP_IRQ))
- printk(KERN_INFO
- "DMA synchronization event drop occurred with device "
- "%d\n", dma_chan[ch].dev_id);
+ pr_info("DMA synchronization event drop occurred with device %d\n",
+ dma_chan[ch].dev_id);
if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
printk(KERN_INFO "DMA transaction error with device %d\n",
dma_chan[ch].dev_id);
p = pdev->dev.platform_data;
if (!p) {
- dev_err(&pdev->dev, "%s: System DMA initialized without"
- "platform data\n", __func__);
+ dev_err(&pdev->dev,
+ "%s: System DMA initialized without platform data\n",
+ __func__);
return -EINVAL;
}
}
ret = setup_irq(dma_irq, &omap24xx_dma_irq);
if (ret) {
- dev_err(&pdev->dev, "set_up failed for IRQ %d"
- "for DMA (error %d)\n", dma_irq, ret);
+ dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
+ dma_irq, ret);
goto exit_dma_lch_fail;
}
}
/* reserve dma channels 0 and 1 in high security devices */
if (cpu_is_omap34xx() &&
(omap_type() != OMAP2_DEVICE_TYPE_GP)) {
- printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
- "HS ROM code\n");
+ pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
dma_chan[0].dev_id = 0;
dma_chan[1].dev_id = 1;
}
return 0;
exit_dma_irq_fail:
- dev_err(&pdev->dev, "unable to request IRQ %d"
- "for DMA (error %d)\n", dma_irq, ret);
+ dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
+ dma_irq, ret);
for (irq_rel = 0; irq_rel < ch; irq_rel++) {
dma_irq = platform_get_irq(pdev, irq_rel);
free_irq(dma_irq, (void *)(irq_rel + 1));
};
if (t == -1)
- pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
- "dev %s, t = %ld usec\n", dev_name(dev), t);
+ pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n",
+ dev_name(dev), t);
/*
* For current Linux, this needs to map the MPU to a
};
if (r == 0)
- pr_debug("OMAP PM: remove min bus tput constraint: "
- "dev %s for agent_id %d\n", dev_name(dev), agent_id);
+ pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n",
+ dev_name(dev), agent_id);
else
- pr_debug("OMAP PM: add min bus tput constraint: "
- "dev %s for agent_id %d: rate %ld KiB\n",
+ pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n",
dev_name(dev), agent_id, r);
/*
};
if (t == -1)
- pr_debug("OMAP PM: remove max device latency constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add max device latency constraint: "
- "dev %s, t = %ld usec\n", dev_name(dev), t);
+ pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
+ dev_name(dev), t);
/*
* For current Linux, this needs to map the device to a
};
if (t == -1)
- pr_debug("OMAP PM: remove max DMA latency constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add max DMA latency constraint: "
- "dev %s, t = %ld usec\n", dev_name(dev), t);
+ pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
+ dev_name(dev), t);
/*
* For current Linux PM QOS params, this code should scan the
}
if (r == 0)
- pr_debug("OMAP PM: remove min clk rate constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add min clk rate constraint: "
- "dev %s, rate = %ld Hz\n", dev_name(dev), r);
+ pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
+ dev_name(dev), r);
/*
* Code in a real implementation should keep track of these
-
/*
* omap_device implementation
*
act_lat = timespec_to_ns(&c);
dev_dbg(&od->pdev->dev,
- "omap_device: pm_lat %d: activate: elapsed time "
- "%llu nsec\n", od->pm_lat_level, act_lat);
+ "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
+ od->pm_lat_level, act_lat);
if (act_lat > odpl->activate_lat) {
odpl->activate_lat_worst = act_lat;
if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
odpl->activate_lat = act_lat;
dev_dbg(&od->pdev->dev,
- "new worst case activate latency "
- "%d: %llu\n",
+ "new worst case activate latency %d: %llu\n",
od->pm_lat_level, act_lat);
} else
dev_warn(&od->pdev->dev,
- "activate latency %d "
- "higher than exptected. (%llu > %d)\n",
+ "activate latency %d higher than expected. (%llu > %d)\n",
od->pm_lat_level, act_lat,
odpl->activate_lat);
}
deact_lat = timespec_to_ns(&c);
dev_dbg(&od->pdev->dev,
- "omap_device: pm_lat %d: deactivate: elapsed time "
- "%llu nsec\n", od->pm_lat_level, deact_lat);
+ "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
+ od->pm_lat_level, deact_lat);
if (deact_lat > odpl->deactivate_lat) {
odpl->deactivate_lat_worst = deact_lat;
if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
odpl->deactivate_lat = deact_lat;
dev_dbg(&od->pdev->dev,
- "new worst case deactivate latency "
- "%d: %llu\n",
+ "new worst case deactivate latency %d: %llu\n",
od->pm_lat_level, deact_lat);
} else
dev_warn(&od->pdev->dev,
- "deactivate latency %d "
- "higher than exptected. (%llu > %d)\n",
+ "deactivate latency %d higher than expected. (%llu > %d)\n",
od->pm_lat_level, deact_lat,
odpl->deactivate_lat);
}
for (i = 0; i < od->hwmods_cnt; i++)
c += omap_hwmod_count_resources(od->hwmods[i]);
- pr_debug("omap_device: %s: counted %d total resources across %d "
- "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
+ pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
+ od->pdev->name, c, od->hwmods_cnt);
return c;
}
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff