ARM i.MX: Merge i.MX5 support into mach-imx
authorSascha Hauer <s.hauer@pengutronix.de>
Mon, 7 Nov 2011 11:36:48 +0000 (12:36 +0100)
committerSascha Hauer <s.hauer@pengutronix.de>
Wed, 16 Nov 2011 07:37:37 +0000 (08:37 +0100)
This patch moves the contents of arch/arm/mach-mx5 to arch/arm/mach-imx
and adjusts the Makefile/Kconfig entries in a way that it's possible
to compile i.MX5 together with i.MX3/6.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
65 files changed:
arch/arm/Makefile
arch/arm/mach-imx/Kconfig
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/Makefile.boot
arch/arm/mach-imx/clock-mx51-mx53.c [new file with mode: 0644]
arch/arm/mach-imx/cpu-imx5.c [new file with mode: 0644]
arch/arm/mach-imx/cpu_op-mx51.c [new file with mode: 0644]
arch/arm/mach-imx/cpu_op-mx51.h [new file with mode: 0644]
arch/arm/mach-imx/crm-regs-imx5.h [new file with mode: 0644]
arch/arm/mach-imx/devices-imx50.h [new file with mode: 0644]
arch/arm/mach-imx/devices-imx51.h [new file with mode: 0644]
arch/arm/mach-imx/devices-imx53.h [new file with mode: 0644]
arch/arm/mach-imx/efika.h [new file with mode: 0644]
arch/arm/mach-imx/ehci-imx5.c [new file with mode: 0644]
arch/arm/mach-imx/eukrea_mbimx51-baseboard.c [new file with mode: 0644]
arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c [new file with mode: 0644]
arch/arm/mach-imx/imx51-dt.c [new file with mode: 0644]
arch/arm/mach-imx/imx53-dt.c [new file with mode: 0644]
arch/arm/mach-imx/mach-cpuimx51.c [new file with mode: 0644]
arch/arm/mach-imx/mach-cpuimx51sd.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx50_rdp.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx51_3ds.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx51_babbage.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx51_efikamx.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx51_efikasb.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx53_ard.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx53_evk.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx53_loco.c [new file with mode: 0644]
arch/arm/mach-imx/mach-mx53_smd.c [new file with mode: 0644]
arch/arm/mach-imx/mm-imx5.c [new file with mode: 0644]
arch/arm/mach-imx/mx51_efika.c [new file with mode: 0644]
arch/arm/mach-imx/pm-imx5.c [new file with mode: 0644]
arch/arm/mach-mx5/Kconfig [deleted file]
arch/arm/mach-mx5/Makefile [deleted file]
arch/arm/mach-mx5/Makefile.boot [deleted file]
arch/arm/mach-mx5/board-cpuimx51.c [deleted file]
arch/arm/mach-mx5/board-cpuimx51sd.c [deleted file]
arch/arm/mach-mx5/board-mx50_rdp.c [deleted file]
arch/arm/mach-mx5/board-mx51_3ds.c [deleted file]
arch/arm/mach-mx5/board-mx51_babbage.c [deleted file]
arch/arm/mach-mx5/board-mx51_efikamx.c [deleted file]
arch/arm/mach-mx5/board-mx51_efikasb.c [deleted file]
arch/arm/mach-mx5/board-mx53_ard.c [deleted file]
arch/arm/mach-mx5/board-mx53_evk.c [deleted file]
arch/arm/mach-mx5/board-mx53_loco.c [deleted file]
arch/arm/mach-mx5/board-mx53_smd.c [deleted file]
arch/arm/mach-mx5/clock-mx51-mx53.c [deleted file]
arch/arm/mach-mx5/cpu.c [deleted file]
arch/arm/mach-mx5/cpu_op-mx51.c [deleted file]
arch/arm/mach-mx5/cpu_op-mx51.h [deleted file]
arch/arm/mach-mx5/crm_regs.h [deleted file]
arch/arm/mach-mx5/devices-imx50.h [deleted file]
arch/arm/mach-mx5/devices-imx51.h [deleted file]
arch/arm/mach-mx5/devices-imx53.h [deleted file]
arch/arm/mach-mx5/efika.h [deleted file]
arch/arm/mach-mx5/ehci.c [deleted file]
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c [deleted file]
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c [deleted file]
arch/arm/mach-mx5/imx51-dt.c [deleted file]
arch/arm/mach-mx5/imx53-dt.c [deleted file]
arch/arm/mach-mx5/mm.c [deleted file]
arch/arm/mach-mx5/mx51_efika.c [deleted file]
arch/arm/mach-mx5/pm-imx5.c [deleted file]
arch/arm/mach-mx5/system.c [deleted file]
arch/arm/plat-mxc/Kconfig

index dfcf3b033e10b465ff44107c43cfa1141fd989f4..cf7d467267ad8beadaae5092b190074f6f8395ab 100644 (file)
@@ -160,7 +160,6 @@ machine-$(CONFIG_ARCH_MSM)          := msm
 machine-$(CONFIG_ARCH_MV78XX0)         := mv78xx0
 machine-$(CONFIG_ARCH_IMX_V4_V5)       := imx
 machine-$(CONFIG_ARCH_IMX_V6_V7)       := imx
-machine-$(CONFIG_ARCH_MX5)             := mx5
 machine-$(CONFIG_ARCH_MXS)             := mxs
 machine-$(CONFIG_ARCH_NETX)            := netx
 machine-$(CONFIG_ARCH_NOMADIK)         := nomadik
index 5f7f9c2a34aec39cdd4f312c326cd0005d5ea027..ef6a6b8f01cae9b94cf3e03b600ed26b0950d394 100644 (file)
@@ -33,6 +33,18 @@ config ARCH_MX31
 config ARCH_MX35
        bool
 
+config ARCH_MX5
+       bool
+
+config ARCH_MX50
+       bool
+
+config ARCH_MX51
+       bool
+
+config ARCH_MX53
+       bool
+
 config SOC_IMX1
        bool
        select ARCH_MX1
@@ -86,6 +98,32 @@ config SOC_IMX35
        select MXC_AVIC
        select SMP_ON_UP if SMP
 
+config SOC_IMX5
+       select CPU_V7
+       select ARM_L1_CACHE_SHIFT_6
+       select MXC_TZIC
+       select ARCH_MXC_IOMUX_V3
+       select ARCH_MXC_AUDMUX_V2
+       select ARCH_HAS_CPUFREQ
+       select ARCH_MX5
+       bool
+
+config SOC_IMX50
+       bool
+       select SOC_IMX5
+       select ARCH_MX50
+
+config SOC_IMX51
+       bool
+       select SOC_IMX5
+       select ARCH_MX5
+       select ARCH_MX51
+
+config SOC_IMX53
+       bool
+       select SOC_IMX5
+       select ARCH_MX5
+       select ARCH_MX53
 
 if ARCH_IMX_V4_V5
 
@@ -604,6 +642,207 @@ config MACH_VPR200
          Include support for VPR200 platform. This includes specific
          configurations for the board and its peripherals.
 
+comment "i.MX5 platforms:"
+
+config MACH_MX50_RDP
+       bool "Support MX50 reference design platform"
+       depends on BROKEN
+       select SOC_IMX50
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       help
+         Include support for MX50 reference design platform (RDP) board. This
+         includes specific configurations for the board and its peripherals.
+
+comment "i.MX51 machines:"
+
+config MACH_IMX51_DT
+       bool "Support i.MX51 platforms from device tree"
+       select SOC_IMX51
+       select USE_OF
+       select MACH_MX51_BABBAGE
+       help
+         Include support for Freescale i.MX51 based platforms
+         using the device tree for discovery
+
+config MACH_MX51_BABBAGE
+       bool "Support MX51 BABBAGE platforms"
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_EHCI
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       help
+         Include support for MX51 Babbage platform, also known as MX51EVK in
+         u-boot. This includes specific configurations for the board and its
+         peripherals.
+
+config MACH_MX51_3DS
+       bool "Support MX51PDK (3DS)"
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_KEYPAD
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       select MXC_DEBUG_BOARD
+       help
+         Include support for MX51PDK (3DS) platform. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_EUKREA_CPUIMX51
+       bool "Support Eukrea CPUIMX51 module"
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_EHCI
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       help
+         Include support for Eukrea CPUIMX51 platform. This includes
+         specific configurations for the module and its peripherals.
+
+choice
+       prompt "Baseboard"
+       depends on MACH_EUKREA_CPUIMX51
+       default MACH_EUKREA_MBIMX51_BASEBOARD
+
+config MACH_EUKREA_MBIMX51_BASEBOARD
+       prompt "Eukrea MBIMX51 development board"
+       bool
+       select IMX_HAVE_PLATFORM_IMX_KEYPAD
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select LEDS_GPIO_REGISTER
+       help
+         This adds board specific devices that can be found on Eukrea's
+         MBIMX51 evaluation board.
+
+endchoice
+
+config MACH_EUKREA_CPUIMX51SD
+       bool "Support Eukrea CPUIMX51SD module"
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_EHCI
+       select IMX_HAVE_PLATFORM_MXC_NAND
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       help
+         Include support for Eukrea CPUIMX51SD platform. This includes
+         specific configurations for the module and its peripherals.
+
+choice
+       prompt "Baseboard"
+       depends on MACH_EUKREA_CPUIMX51SD
+       default MACH_EUKREA_MBIMXSD51_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD51_BASEBOARD
+       prompt "Eukrea MBIMXSD development board"
+       bool
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select LEDS_GPIO_REGISTER
+       help
+         This adds board specific devices that can be found on Eukrea's
+         MBIMXSD evaluation board.
+
+endchoice
+
+config MX51_EFIKA_COMMON
+       bool
+       select SOC_IMX51
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_MXC_EHCI
+       select IMX_HAVE_PLATFORM_PATA_IMX
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       select MXC_ULPI if USB_ULPI
+
+config MACH_MX51_EFIKAMX
+       bool "Support MX51 Genesi Efika MX nettop"
+       select LEDS_GPIO_REGISTER
+       select MX51_EFIKA_COMMON
+       help
+         Include support for Genesi Efika MX nettop. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_MX51_EFIKASB
+       bool "Support MX51 Genesi Efika Smartbook"
+       select LEDS_GPIO_REGISTER
+       select MX51_EFIKA_COMMON
+       help
+         Include support for Genesi Efika Smartbook. This includes specific
+         configurations for the board and its peripherals.
+
+comment "i.MX53 machines:"
+
+config MACH_IMX53_DT
+       bool "Support i.MX53 platforms from device tree"
+       select SOC_IMX53
+       select USE_OF
+       select MACH_MX53_ARD
+       select MACH_MX53_EVK
+       select MACH_MX53_LOCO
+       select MACH_MX53_SMD
+       help
+         Include support for Freescale i.MX53 based platforms
+         using the device tree for discovery
+
+config MACH_MX53_EVK
+       bool "Support MX53 EVK platforms"
+       select SOC_IMX53
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_SPI_IMX
+       select LEDS_GPIO_REGISTER
+       help
+         Include support for MX53 EVK platform. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_MX53_SMD
+       bool "Support MX53 SMD platforms"
+       select SOC_IMX53
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       help
+         Include support for MX53 SMD platform. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_MX53_LOCO
+       bool "Support MX53 LOCO platforms"
+       select SOC_IMX53
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_GPIO_KEYS
+       select LEDS_GPIO_REGISTER
+       help
+         Include support for MX53 LOCO platform. This includes specific
+         configurations for the board and its peripherals.
+
+config MACH_MX53_ARD
+       bool "Support MX53 ARD platforms"
+       select SOC_IMX53
+       select IMX_HAVE_PLATFORM_IMX2_WDT
+       select IMX_HAVE_PLATFORM_IMX_I2C
+       select IMX_HAVE_PLATFORM_IMX_UART
+       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+       select IMX_HAVE_PLATFORM_GPIO_KEYS
+       help
+         Include support for MX53 ARD platform. This includes specific
+         configurations for the board and its peripherals.
+
 comment "i.MX6 family:"
 
 config SOC_IMX6Q
index aba73214c2a8cd640e0f4371caf4ce99ac53dc0f..9cf630a341e18bd9579686ae80af497c558f2df9 100644 (file)
@@ -11,6 +11,8 @@ obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
 
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
+
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
 
@@ -71,3 +73,22 @@ obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
+
+# i.MX5 based machines
+obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
+obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
+obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
+obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
+obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
+obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += mach-cpuimx51.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
+obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
+obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
+obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
+
+obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
+obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
index 22d85889f622917ece0fe5310751bf4ab488fed3..2c12b7889e97acc44b6af29771362972d355ef6f 100644 (file)
@@ -18,6 +18,18 @@ zreladdr-$(CONFIG_ARCH_MX3)  += 0x80008000
 params_phys-$(CONFIG_ARCH_MX3) := 0x80000100
 initrd_phys-$(CONFIG_ARCH_MX3) := 0x80800000
 
+zreladdr-$(CONFIG_SOC_IMX50)   += 0x70008000
+params_phys-$(CONFIG_SOC_IMX50)        := 0x70000100
+initrd_phys-$(CONFIG_SOC_IMX50)        := 0x70800000
+
+zreladdr-$(CONFIG_SOC_IMX51)   += 0x90008000
+params_phys-$(CONFIG_SOC_IMX51)        := 0x90000100
+initrd_phys-$(CONFIG_SOC_IMX51)        := 0x90800000
+
+zreladdr-$(CONFIG_SOC_IMX53)   += 0x70008000
+params_phys-$(CONFIG_SOC_IMX53)        := 0x70000100
+initrd_phys-$(CONFIG_SOC_IMX53)        := 0x70800000
+
 zreladdr-$(CONFIG_SOC_IMX6Q)   += 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q)        := 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q)        := 0x10800000
diff --git a/arch/arm/mach-imx/clock-mx51-mx53.c b/arch/arm/mach-imx/clock-mx51-mx53.c
new file mode 100644 (file)
index 0000000..a2c654d
--- /dev/null
@@ -0,0 +1,1673 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+
+#include <asm/div64.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+
+#include "crm-regs-imx5.h"
+
+/* External clock values passed-in by the board code */
+static unsigned long external_high_reference, external_low_reference;
+static unsigned long oscillator_reference, ckih2_reference;
+
+static struct clk osc_clk;
+static struct clk pll1_main_clk;
+static struct clk pll1_sw_clk;
+static struct clk pll2_sw_clk;
+static struct clk pll3_sw_clk;
+static struct clk mx53_pll4_sw_clk;
+static struct clk lp_apm_clk;
+static struct clk periph_apm_clk;
+static struct clk ahb_clk;
+static struct clk ipg_clk;
+static struct clk usboh3_clk;
+static struct clk emi_fast_clk;
+static struct clk ipu_clk;
+static struct clk mipi_hsc1_clk;
+static struct clk esdhc1_clk;
+static struct clk esdhc2_clk;
+static struct clk esdhc3_mx53_clk;
+
+#define MAX_DPLL_WAIT_TRIES    1000 /* 1000 * udelay(1) = 1ms */
+
+/* calculate best pre and post dividers to get the required divider */
+static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
+       u32 max_pre, u32 max_post)
+{
+       if (div >= max_pre * max_post) {
+               *pre = max_pre;
+               *post = max_post;
+       } else if (div >= max_pre) {
+               u32 min_pre, temp_pre, old_err, err;
+               min_pre = DIV_ROUND_UP(div, max_post);
+               old_err = max_pre;
+               for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
+                       err = div % temp_pre;
+                       if (err == 0) {
+                               *pre = temp_pre;
+                               break;
+                       }
+                       err = temp_pre - err;
+                       if (err < old_err) {
+                               old_err = err;
+                               *pre = temp_pre;
+                       }
+               }
+               *post = DIV_ROUND_UP(div, *pre);
+       } else {
+               *pre = div;
+               *post = 1;
+       }
+}
+
+static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
+{
+       u32 reg = __raw_readl(clk->enable_reg);
+
+       reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+       reg |= mode << clk->enable_shift;
+
+       __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_ccgr_enable(struct clk *clk)
+{
+       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
+       return 0;
+}
+
+static void _clk_ccgr_disable(struct clk *clk)
+{
+       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
+}
+
+static int _clk_ccgr_enable_inrun(struct clk *clk)
+{
+       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
+       return 0;
+}
+
+static void _clk_ccgr_disable_inwait(struct clk *clk)
+{
+       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
+}
+
+/*
+ * For the 4-to-1 muxed input clock
+ */
+static inline u32 _get_mux(struct clk *parent, struct clk *m0,
+                          struct clk *m1, struct clk *m2, struct clk *m3)
+{
+       if (parent == m0)
+               return 0;
+       else if (parent == m1)
+               return 1;
+       else if (parent == m2)
+               return 2;
+       else if (parent == m3)
+               return 3;
+       else
+               BUG();
+
+       return -EINVAL;
+}
+
+static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
+{
+       if (pll == &pll1_main_clk)
+               return MX51_DPLL1_BASE;
+       else if (pll == &pll2_sw_clk)
+               return MX51_DPLL2_BASE;
+       else if (pll == &pll3_sw_clk)
+               return MX51_DPLL3_BASE;
+       else
+               BUG();
+
+       return NULL;
+}
+
+static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
+{
+       if (pll == &pll1_main_clk)
+               return MX53_DPLL1_BASE;
+       else if (pll == &pll2_sw_clk)
+               return MX53_DPLL2_BASE;
+       else if (pll == &pll3_sw_clk)
+               return MX53_DPLL3_BASE;
+       else if (pll == &mx53_pll4_sw_clk)
+               return MX53_DPLL4_BASE;
+       else
+               BUG();
+
+       return NULL;
+}
+
+static inline void __iomem *_get_pll_base(struct clk *pll)
+{
+       if (cpu_is_mx51())
+               return _mx51_get_pll_base(pll);
+       else
+               return _mx53_get_pll_base(pll);
+}
+
+static unsigned long clk_pll_get_rate(struct clk *clk)
+{
+       long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+       unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
+       void __iomem *pllbase;
+       s64 temp;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       pllbase = _get_pll_base(clk);
+
+       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+       dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
+
+       if (pll_hfsm == 0) {
+               dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+       } else {
+               dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+       }
+       pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+       mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
+       mfi = (mfi <= 5) ? 5 : mfi;
+       mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+       mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
+       /* Sign extend to 32-bits */
+       if (mfn >= 0x04000000) {
+               mfn |= 0xFC000000;
+               mfn_abs = -mfn;
+       }
+
+       ref_clk = 2 * parent_rate;
+       if (dbl != 0)
+               ref_clk *= 2;
+
+       ref_clk /= (pdf + 1);
+       temp = (u64) ref_clk * mfn_abs;
+       do_div(temp, mfd + 1);
+       if (mfn < 0)
+               temp = -temp;
+       temp = (ref_clk * mfi) + temp;
+
+       return temp;
+}
+
+static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 reg;
+       void __iomem *pllbase;
+
+       long mfi, pdf, mfn, mfd = 999999;
+       s64 temp64;
+       unsigned long quad_parent_rate;
+       unsigned long pll_hfsm, dp_ctl;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       pllbase = _get_pll_base(clk);
+
+       quad_parent_rate = 4 * parent_rate;
+       pdf = mfi = -1;
+       while (++pdf < 16 && mfi < 5)
+               mfi = rate * (pdf+1) / quad_parent_rate;
+       if (mfi > 15)
+               return -EINVAL;
+       pdf--;
+
+       temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
+       do_div(temp64, quad_parent_rate/1000000);
+       mfn = (long)temp64;
+
+       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+       /* use dpdck0_2 */
+       __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
+       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+       if (pll_hfsm == 0) {
+               reg = mfi << 4 | pdf;
+               __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
+               __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
+               __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
+       } else {
+               reg = mfi << 4 | pdf;
+               __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
+               __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
+               __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
+       }
+
+       return 0;
+}
+
+static int _clk_pll_enable(struct clk *clk)
+{
+       u32 reg;
+       void __iomem *pllbase;
+       int i = 0;
+
+       pllbase = _get_pll_base(clk);
+       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+       if (reg & MXC_PLL_DP_CTL_UPEN)
+               return 0;
+
+       reg |= MXC_PLL_DP_CTL_UPEN;
+       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+
+       /* Wait for lock */
+       do {
+               reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+               if (reg & MXC_PLL_DP_CTL_LRF)
+                       break;
+
+               udelay(1);
+       } while (++i < MAX_DPLL_WAIT_TRIES);
+
+       if (i == MAX_DPLL_WAIT_TRIES) {
+               pr_err("MX5: pll locking failed\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static void _clk_pll_disable(struct clk *clk)
+{
+       u32 reg;
+       void __iomem *pllbase;
+
+       pllbase = _get_pll_base(clk);
+       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
+       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+}
+
+static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg, step;
+
+       reg = __raw_readl(MXC_CCM_CCSR);
+
+       /* When switching from pll_main_clk to a bypass clock, first select a
+        * multiplexed clock in 'step_sel', then shift the glitchless mux
+        * 'pll1_sw_clk_sel'.
+        *
+        * When switching back, do it in reverse order
+        */
+       if (parent == &pll1_main_clk) {
+               /* Switch to pll1_main_clk */
+               reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+               __raw_writel(reg, MXC_CCM_CCSR);
+               /* step_clk mux switched to lp_apm, to save power. */
+               reg = __raw_readl(MXC_CCM_CCSR);
+               reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
+               reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
+                               MXC_CCM_CCSR_STEP_SEL_OFFSET);
+       } else {
+               if (parent == &lp_apm_clk) {
+                       step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
+               } else  if (parent == &pll2_sw_clk) {
+                       step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
+               } else  if (parent == &pll3_sw_clk) {
+                       step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
+               } else
+                       return -EINVAL;
+
+               reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
+               reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
+
+               __raw_writel(reg, MXC_CCM_CCSR);
+               /* Switch to step_clk */
+               reg = __raw_readl(MXC_CCM_CCSR);
+               reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+       }
+       __raw_writel(reg, MXC_CCM_CCSR);
+       return 0;
+}
+
+static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
+{
+       u32 reg, div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       reg = __raw_readl(MXC_CCM_CCSR);
+
+       if (clk->parent == &pll2_sw_clk) {
+               div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
+                      MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
+       } else if (clk->parent == &pll3_sw_clk) {
+               div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
+                      MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
+       } else
+               div = 1;
+       return parent_rate / div;
+}
+
+static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CCSR);
+
+       if (parent == &pll2_sw_clk)
+               reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
+       else
+               reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
+
+       __raw_writel(reg, MXC_CCM_CCSR);
+       return 0;
+}
+
+static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       if (parent == &osc_clk)
+               reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
+       else
+               return -EINVAL;
+
+       __raw_writel(reg, MXC_CCM_CCSR);
+
+       return 0;
+}
+
+static unsigned long clk_cpu_get_rate(struct clk *clk)
+{
+       u32 cacrr, div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+       cacrr = __raw_readl(MXC_CCM_CACRR);
+       div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
+
+       return parent_rate / div;
+}
+
+static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 reg, cpu_podf;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+       cpu_podf = parent_rate / rate - 1;
+       /* use post divider to change freq */
+       reg = __raw_readl(MXC_CCM_CACRR);
+       reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
+       reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
+       __raw_writel(reg, MXC_CCM_CACRR);
+
+       return 0;
+}
+
+static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg, mux;
+       int i = 0;
+
+       mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
+
+       reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
+       reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
+       __raw_writel(reg, MXC_CCM_CBCMR);
+
+       /* Wait for lock */
+       do {
+               reg = __raw_readl(MXC_CCM_CDHIPR);
+               if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
+                       break;
+
+               udelay(1);
+       } while (++i < MAX_DPLL_WAIT_TRIES);
+
+       if (i == MAX_DPLL_WAIT_TRIES) {
+               pr_err("MX5: Set parent for periph_apm clock failed\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+
+       if (parent == &pll2_sw_clk)
+               reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+       else if (parent == &periph_apm_clk)
+               reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+       else
+               return -EINVAL;
+
+       __raw_writel(reg, MXC_CCM_CBCDR);
+
+       return 0;
+}
+
+static struct clk main_bus_clk = {
+       .parent = &pll2_sw_clk,
+       .set_parent = _clk_main_bus_set_parent,
+};
+
+static unsigned long clk_ahb_get_rate(struct clk *clk)
+{
+       u32 reg, div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+              MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
+       return parent_rate / div;
+}
+
+
+static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 reg, div;
+       unsigned long parent_rate;
+       int i = 0;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       div = parent_rate / rate;
+       if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+               return -EINVAL;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
+       reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+       __raw_writel(reg, MXC_CCM_CBCDR);
+
+       /* Wait for lock */
+       do {
+               reg = __raw_readl(MXC_CCM_CDHIPR);
+               if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
+                       break;
+
+               udelay(1);
+       } while (++i < MAX_DPLL_WAIT_TRIES);
+
+       if (i == MAX_DPLL_WAIT_TRIES) {
+               pr_err("MX5: clk_ahb_set_rate failed\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static unsigned long _clk_ahb_round_rate(struct clk *clk,
+                                               unsigned long rate)
+{
+       u32 div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       div = parent_rate / rate;
+       if (div > 8)
+               div = 8;
+       else if (div == 0)
+               div++;
+       return parent_rate / div;
+}
+
+
+static int _clk_max_enable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_enable(clk);
+
+       /* Handshake with MAX when LPM is entered. */
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       if (cpu_is_mx51())
+               reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+       else if (cpu_is_mx53())
+               reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+
+       return 0;
+}
+
+static void _clk_max_disable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_disable_inwait(clk);
+
+       /* No Handshake with MAX when LPM is entered as its disabled. */
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       if (cpu_is_mx51())
+               reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+       else if (cpu_is_mx53())
+               reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static unsigned long clk_ipg_get_rate(struct clk *clk)
+{
+       u32 reg, div;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+              MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+
+       return parent_rate / div;
+}
+
+static unsigned long clk_ipg_per_get_rate(struct clk *clk)
+{
+       u32 reg, prediv1, prediv2, podf;
+       unsigned long parent_rate;
+
+       parent_rate = clk_get_rate(clk->parent);
+
+       if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
+               /* the main_bus_clk is the one before the DVFS engine */
+               reg = __raw_readl(MXC_CCM_CBCDR);
+               prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
+                          MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
+               prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
+                          MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
+               podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
+                       MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
+               return parent_rate / (prediv1 * prediv2 * podf);
+       } else if (clk->parent == &ipg_clk)
+               return parent_rate;
+       else
+               BUG();
+}
+
+static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CBCMR);
+
+       reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
+       reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
+
+       if (parent == &ipg_clk)
+               reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
+       else if (parent == &lp_apm_clk)
+               reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
+       else if (parent != &main_bus_clk)
+               return -EINVAL;
+
+       __raw_writel(reg, MXC_CCM_CBCMR);
+
+       return 0;
+}
+
+#define clk_nfc_set_parent     NULL
+
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+       unsigned long rate;
+       u32 reg, div;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
+              MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
+       rate = clk_get_rate(clk->parent) / div;
+       WARN_ON(rate == 0);
+       return rate;
+}
+
+static unsigned long clk_nfc_round_rate(struct clk *clk,
+                                               unsigned long rate)
+{
+       u32 div;
+       unsigned long parent_rate = clk_get_rate(clk->parent);
+
+       if (!rate)
+               return -EINVAL;
+
+       div = parent_rate / rate;
+
+       if (parent_rate % rate)
+               div++;
+
+       if (div > 8)
+               return -EINVAL;
+
+       return parent_rate / div;
+
+}
+
+static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
+{
+       u32 reg, div;
+
+       div = clk_get_rate(clk->parent) / rate;
+       if (div == 0)
+               div++;
+       if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
+               return -EINVAL;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+       reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+       __raw_writel(reg, MXC_CCM_CBCDR);
+
+       while (__raw_readl(MXC_CCM_CDHIPR) &
+                       MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
+       }
+
+       return 0;
+}
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+       return external_high_reference;
+}
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+       return external_low_reference;
+}
+
+static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
+{
+       return oscillator_reference;
+}
+
+static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
+{
+       return ckih2_reference;
+}
+
+static unsigned long clk_emi_slow_get_rate(struct clk *clk)
+{
+       u32 reg, div;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
+              MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
+
+       return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
+{
+       unsigned long rate;
+       u32 reg, div;
+
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
+               MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
+       rate = clk_get_rate(clk->parent) / div;
+
+       return rate;
+}
+
+/* External high frequency clock */
+static struct clk ckih_clk = {
+       .get_rate = get_high_reference_clock_rate,
+};
+
+static struct clk ckih2_clk = {
+       .get_rate = get_ckih2_reference_clock_rate,
+};
+
+static struct clk osc_clk = {
+       .get_rate = get_oscillator_reference_clock_rate,
+};
+
+/* External low frequency (32kHz) clock */
+static struct clk ckil_clk = {
+       .get_rate = get_low_reference_clock_rate,
+};
+
+static struct clk pll1_main_clk = {
+       .parent = &osc_clk,
+       .get_rate = clk_pll_get_rate,
+       .enable = _clk_pll_enable,
+       .disable = _clk_pll_disable,
+};
+
+/* Clock tree block diagram (WIP):
+ *     CCM: Clock Controller Module
+ *
+ * PLL output -> |
+ *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
+ * PLL bypass -> |
+ *
+ */
+
+/* PLL1 SW supplies to ARM core */
+static struct clk pll1_sw_clk = {
+       .parent = &pll1_main_clk,
+       .set_parent = _clk_pll1_sw_set_parent,
+       .get_rate = clk_pll1_sw_get_rate,
+};
+
+/* PLL2 SW supplies to AXI/AHB/IP buses */
+static struct clk pll2_sw_clk = {
+       .parent = &osc_clk,
+       .get_rate = clk_pll_get_rate,
+       .set_rate = _clk_pll_set_rate,
+       .set_parent = _clk_pll2_sw_set_parent,
+       .enable = _clk_pll_enable,
+       .disable = _clk_pll_disable,
+};
+
+/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
+static struct clk pll3_sw_clk = {
+       .parent = &osc_clk,
+       .set_rate = _clk_pll_set_rate,
+       .get_rate = clk_pll_get_rate,
+       .enable = _clk_pll_enable,
+       .disable = _clk_pll_disable,
+};
+
+/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
+static struct clk mx53_pll4_sw_clk = {
+       .parent = &osc_clk,
+       .set_rate = _clk_pll_set_rate,
+       .enable = _clk_pll_enable,
+       .disable = _clk_pll_disable,
+};
+
+/* Low-power Audio Playback Mode clock */
+static struct clk lp_apm_clk = {
+       .parent = &osc_clk,
+       .set_parent = _clk_lp_apm_set_parent,
+};
+
+static struct clk periph_apm_clk = {
+       .parent = &pll1_sw_clk,
+       .set_parent = _clk_periph_apm_set_parent,
+};
+
+static struct clk cpu_clk = {
+       .parent = &pll1_sw_clk,
+       .get_rate = clk_cpu_get_rate,
+       .set_rate = clk_cpu_set_rate,
+};
+
+static struct clk ahb_clk = {
+       .parent = &main_bus_clk,
+       .get_rate = clk_ahb_get_rate,
+       .set_rate = _clk_ahb_set_rate,
+       .round_rate = _clk_ahb_round_rate,
+};
+
+static struct clk iim_clk = {
+       .parent = &ipg_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+};
+
+/* Main IP interface clock for access to registers */
+static struct clk ipg_clk = {
+       .parent = &ahb_clk,
+       .get_rate = clk_ipg_get_rate,
+};
+
+static struct clk ipg_perclk = {
+       .parent = &lp_apm_clk,
+       .get_rate = clk_ipg_per_get_rate,
+       .set_parent = _clk_ipg_per_set_parent,
+};
+
+static struct clk ahb_max_clk = {
+       .parent = &ahb_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+       .enable = _clk_max_enable,
+       .disable = _clk_max_disable,
+};
+
+static struct clk aips_tz1_clk = {
+       .parent = &ahb_clk,
+       .secondary = &ahb_max_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable_inwait,
+};
+
+static struct clk aips_tz2_clk = {
+       .parent = &ahb_clk,
+       .secondary = &ahb_max_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable_inwait,
+};
+
+static struct clk gpc_dvfs_clk = {
+       .enable_reg = MXC_CCM_CCGR5,
+       .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable,
+};
+
+static struct clk gpt_32k_clk = {
+       .id = 0,
+       .parent = &ckil_clk,
+};
+
+static struct clk dummy_clk = {
+       .id = 0,
+};
+
+static struct clk emi_slow_clk = {
+       .parent = &pll2_sw_clk,
+       .enable_reg = MXC_CCM_CCGR5,
+       .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable_inwait,
+       .get_rate = clk_emi_slow_get_rate,
+};
+
+static int clk_ipu_enable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_enable(clk);
+
+       /* Enable handshake with IPU when certain clock rates are changed */
+       reg = __raw_readl(MXC_CCM_CCDR);
+       reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
+       __raw_writel(reg, MXC_CCM_CCDR);
+
+       /* Enable handshake with IPU when LPM is entered */
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+
+       return 0;
+}
+
+static void clk_ipu_disable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_disable(clk);
+
+       /* Disable handshake with IPU whe dividers are changed */
+       reg = __raw_readl(MXC_CCM_CCDR);
+       reg |= MXC_CCM_CCDR_IPU_HS_MASK;
+       __raw_writel(reg, MXC_CCM_CCDR);
+
+       /* Disable handshake with IPU when LPM is entered */
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static struct clk ahbmux1_clk = {
+       .parent = &ahb_clk,
+       .secondary = &ahb_max_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable_inwait,
+};
+
+static struct clk ipu_sec_clk = {
+       .parent = &emi_fast_clk,
+       .secondary = &ahbmux1_clk,
+};
+
+static struct clk ddr_hf_clk = {
+       .parent = &pll1_sw_clk,
+       .get_rate = _clk_ddr_hf_get_rate,
+};
+
+static struct clk ddr_clk = {
+       .parent = &ddr_hf_clk,
+};
+
+/* clock definitions for MIPI HSC unit which has been removed
+ * from documentation, but not from hardware
+ */
+static int _clk_hsc_enable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_enable(clk);
+       /* Handshake with IPU when certain clock rates are changed. */
+       reg = __raw_readl(MXC_CCM_CCDR);
+       reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
+       __raw_writel(reg, MXC_CCM_CCDR);
+
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+
+       return 0;
+}
+
+static void _clk_hsc_disable(struct clk *clk)
+{
+       u32 reg;
+
+       _clk_ccgr_disable(clk);
+       /* No handshake with HSC as its not enabled. */
+       reg = __raw_readl(MXC_CCM_CCDR);
+       reg |= MXC_CCM_CCDR_HSC_HS_MASK;
+       __raw_writel(reg, MXC_CCM_CCDR);
+
+       reg = __raw_readl(MXC_CCM_CLPCR);
+       reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+       __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static struct clk mipi_hsp_clk = {
+       .parent = &ipu_clk,
+       .enable_reg = MXC_CCM_CCGR4,
+       .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+       .enable = _clk_hsc_enable,
+       .disable = _clk_hsc_disable,
+       .secondary = &mipi_hsc1_clk,
+};
+
+#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)  \
+       static struct clk name = {                      \
+               .id             = i,                    \
+               .enable_reg     = er,                   \
+               .enable_shift   = es,                   \
+               .get_rate       = pfx##_get_rate,       \
+               .set_rate       = pfx##_set_rate,       \
+               .round_rate     = pfx##_round_rate,     \
+               .set_parent     = pfx##_set_parent,     \
+               .enable         = _clk_ccgr_enable,     \
+               .disable        = _clk_ccgr_disable,    \
+               .parent         = p,                    \
+               .secondary      = s,                    \
+       }
+
+#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s)   \
+       static struct clk name = {                      \
+               .id             = i,                    \
+               .enable_reg     = er,                   \
+               .enable_shift   = es,                   \
+               .get_rate       = pfx##_get_rate,       \
+               .set_rate       = pfx##_set_rate,       \
+               .set_parent     = pfx##_set_parent,     \
+               .enable         = _clk_max_enable,      \
+               .disable        = _clk_max_disable,     \
+               .parent         = p,                    \
+               .secondary      = s,                    \
+       }
+
+#define CLK_GET_RATE(name, nr, bitsname)                               \
+static unsigned long clk_##name##_get_rate(struct clk *clk)            \
+{                                                                      \
+       u32 reg, pred, podf;                                            \
+                                                                       \
+       reg = __raw_readl(MXC_CCM_CSCDR##nr);                           \
+       pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK)   \
+               >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;    \
+       podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK)   \
+               >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;    \
+                                                                       \
+       return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),             \
+                       (pred + 1) * (podf + 1));                       \
+}
+
+#define CLK_SET_PARENT(name, nr, bitsname)                             \
+static int clk_##name##_set_parent(struct clk *clk, struct clk *parent)        \
+{                                                                      \
+       u32 reg, mux;                                                   \
+                                                                       \
+       mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,              \
+                       &pll3_sw_clk, &lp_apm_clk);                     \
+       reg = __raw_readl(MXC_CCM_CSCMR##nr) &                          \
+               ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK;         \
+       reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET;  \
+       __raw_writel(reg, MXC_CCM_CSCMR##nr);                           \
+                                                                       \
+       return 0;                                                       \
+}
+
+#define CLK_SET_RATE(name, nr, bitsname)                               \
+static int clk_##name##_set_rate(struct clk *clk, unsigned long rate)  \
+{                                                                      \
+       u32 reg, div, parent_rate;                                      \
+       u32 pre = 0, post = 0;                                          \
+                                                                       \
+       parent_rate = clk_get_rate(clk->parent);                        \
+       div = parent_rate / rate;                                       \
+                                                                       \
+       if ((parent_rate / div) != rate)                                \
+               return -EINVAL;                                         \
+                                                                       \
+       __calc_pre_post_dividers(div, &pre, &post,                      \
+               (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >>      \
+               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1,  \
+               (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >>      \
+               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
+                                                                       \
+       /* Set sdhc1 clock divider */                                   \
+       reg = __raw_readl(MXC_CCM_CSCDR##nr) &                          \
+               ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK        \
+               | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK);      \
+       reg |= (post - 1) <<                                            \
+               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;       \
+       reg |= (pre - 1) <<                                             \
+               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;       \
+       __raw_writel(reg, MXC_CCM_CSCDR##nr);                           \
+                                                                       \
+       return 0;                                                       \
+}
+
+/* UART */
+CLK_GET_RATE(uart, 1, UART)
+CLK_SET_PARENT(uart, 1, UART)
+
+static struct clk uart_root_clk = {
+       .parent = &pll2_sw_clk,
+       .get_rate = clk_uart_get_rate,
+       .set_parent = clk_uart_set_parent,
+};
+
+/* USBOH3 */
+CLK_GET_RATE(usboh3, 1, USBOH3)
+CLK_SET_PARENT(usboh3, 1, USBOH3)
+
+static struct clk usboh3_clk = {
+       .parent = &pll2_sw_clk,
+       .get_rate = clk_usboh3_get_rate,
+       .set_parent = clk_usboh3_set_parent,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable,
+       .enable_reg = MXC_CCM_CCGR2,
+       .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+};
+
+static struct clk usb_ahb_clk = {
+       .parent = &ipg_clk,
+       .enable = _clk_ccgr_enable,
+       .disable = _clk_ccgr_disable,
+       .enable_reg = MXC_CCM_CCGR2,
+       .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+};
+
+static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+
+       if (parent == &pll3_sw_clk)
+               reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
+
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+static struct clk usb_phy1_clk = {
+       .parent = &pll3_sw_clk,
+       .set_parent = clk_usb_phy1_set_parent,
+       .enable = _clk_ccgr_enable,
+       .enable_reg = MXC_CCM_CCGR2,
+       .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+       .disable = _clk_ccgr_disable,
+};
+
+/* eCSPI */
+CLK_GET_RATE(ecspi, 2, CSPI)
+CLK_SET_PARENT(ecspi, 1, CSPI)
+
+static struct clk ecspi_main_clk = {
+       .parent = &pll3_sw_clk,
+       .get_rate = clk_ecspi_get_rate,
+       .set_parent = clk_ecspi_set_parent,
+};
+
+/* eSDHC */
+CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
+CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
+CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
+
+/* mx51 specific */
+CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
+CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
+CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
+
+static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1);
+       if (parent == &esdhc1_clk)
+               reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+       else if (parent == &esdhc2_clk)
+               reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+       else
+               return -EINVAL;
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1);
+       if (parent == &esdhc1_clk)
+               reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+       else if (parent == &esdhc2_clk)
+               reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+       else
+               return -EINVAL;
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+/* mx53 specific */
+static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1);
+       if (parent == &esdhc1_clk)
+               reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+       else if (parent == &esdhc3_mx53_clk)
+               reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+       else
+               return -EINVAL;
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+
+static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 reg;
+
+       reg = __raw_readl(MXC_CCM_CSCMR1);
+       if (parent == &esdhc1_clk)
+               reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+       else if (parent == &esdhc3_mx53_clk)
+               reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+       else
+               return -EINVAL;
+       __raw_writel(reg, MXC_CCM_CSCMR1);
+
+       return 0;
+}
+
+#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)         \
+       static struct clk name = {                                      \
+               .id             = i,                                    \
+               .enable_reg     = er,                                   \
+               .enable_shift   = es,                                   \
+               .get_rate       = gr,                                   \
+               .set_rate       = sr,                                   \
+               .enable         = e,                                    \
+               .disable        = d,                                    \
+               .parent         = p,                                    \
+               .secondary      = s,                                    \
+       }
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                    \
+       DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
+
+/* Shared peripheral bus arbiter */
+DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
+       NULL,  NULL, &ipg_clk, NULL);
+
+/* UART */
+DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
+       NULL,  NULL, &ipg_clk, &aips_tz1_clk);
+DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
+       NULL,  NULL, &ipg_clk, &aips_tz1_clk);
+DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
+       NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
+       NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
+       NULL,  NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
+DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
+DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
+DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart4_ipg_clk);
+DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
+       NULL,  NULL, &uart_root_clk, &uart5_ipg_clk);
+
+/* GPT */
+DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
+       NULL,  NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
+       NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
+
+DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+
+/* I2C */
+DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
+       NULL, NULL, &ipg_perclk, NULL);
+DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
+       NULL, NULL, &ipg_perclk, NULL);
+DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
+       NULL, NULL, &ipg_perclk, NULL);
+
+/* FEC */
+DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
+       NULL,  NULL, &ipg_clk, NULL);
+
+/* NFC */
+DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
+       clk_nfc, &emi_slow_clk, NULL);
+
+/* SSI */
+DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
+       NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
+DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
+       NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
+DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
+       NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
+       NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
+
+/* eCSPI */
+DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+               NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+               &ipg_clk, &spba_clk);
+DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
+               NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
+DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
+               NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+               &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
+               NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
+
+/* CSPI */
+DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+               NULL, NULL, &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
+               NULL, NULL, &ipg_clk, &cspi_ipg_clk);
+
+/* SDMA */
+DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
+               NULL, NULL, &ahb_clk, NULL);
+
+/* eSDHC */
+DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
+       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
+       clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
+DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
+       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
+       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
+       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+
+/* mx51 specific */
+DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
+       clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
+
+static struct clk esdhc3_clk = {
+       .id = 2,
+       .parent = &esdhc1_clk,
+       .set_parent = clk_esdhc3_set_parent,
+       .enable_reg = MXC_CCM_CCGR3,
+       .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+       .enable  = _clk_max_enable,
+       .disable = _clk_max_disable,
+       .secondary = &esdhc3_ipg_clk,
+};
+static struct clk esdhc4_clk = {
+       .id = 3,
+       .parent = &esdhc1_clk,
+       .set_parent = clk_esdhc4_set_parent,
+       .enable_reg = MXC_CCM_CCGR3,
+       .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+       .enable  = _clk_max_enable,
+       .disable = _clk_max_disable,
+       .secondary = &esdhc4_ipg_clk,
+};
+
+/* mx53 specific */
+static struct clk esdhc2_mx53_clk = {
+       .id = 2,
+       .parent = &esdhc1_clk,
+       .set_parent = clk_esdhc2_mx53_set_parent,
+       .enable_reg = MXC_CCM_CCGR3,
+       .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+       .enable  = _clk_max_enable,
+       .disable = _clk_max_disable,
+       .secondary = &esdhc3_ipg_clk,
+};
+
+DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
+       clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
+
+static struct clk esdhc4_mx53_clk = {
+       .id = 3,
+       .parent = &esdhc1_clk,
+       .set_parent = clk_esdhc4_mx53_set_parent,
+       .enable_reg = MXC_CCM_CCGR3,
+       .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+       .enable  = _clk_max_enable,
+       .disable = _clk_max_disable,
+       .secondary = &esdhc4_ipg_clk,
+};
+
+static struct clk sata_clk = {
+       .parent = &ipg_clk,
+       .enable = _clk_max_enable,
+       .enable_reg = MXC_CCM_CCGR4,
+       .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+       .disable = _clk_max_disable,
+};
+
+static struct clk ahci_phy_clk = {
+       .parent = &usb_phy1_clk,
+};
+
+static struct clk ahci_dma_clk = {
+       .parent = &ahb_clk,
+};
+
+DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
+DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
+DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
+
+/* IPU */
+DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
+       NULL,  NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
+
+DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
+               NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
+               &ddr_clk, NULL);
+
+DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
+               NULL, NULL, &pll3_sw_clk, NULL);
+DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
+               NULL, NULL, &pll3_sw_clk, NULL);
+
+/* PATA */
+DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
+               NULL, NULL, &ipg_clk, &spba_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+       { \
+               .dev_id = d, \
+               .con_id = n, \
+               .clk = &c,   \
+       },
+
+static struct clk_lookup mx51_lookups[] = {
+       /* i.mx51 has the i.mx21 type uart */
+       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+       /* i.mx51 has the i.mx27 type fec */
+       _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
+       _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
+       _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
+       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+       _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
+       _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
+       _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
+       _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
+       _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
+       _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
+       _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
+       _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
+       _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
+       _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+       _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
+       _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
+       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+       _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
+       /* i.mx51 has the i.mx35 type sdma */
+       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
+       _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
+       _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
+       _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
+       _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
+       _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
+       /* i.mx51 has the i.mx35 type cspi */
+       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk)
+       _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
+       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
+       _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
+       _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
+       _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
+       _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
+       _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
+       _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
+       _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
+       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
+};
+
+static struct clk_lookup mx53_lookups[] = {
+       /* i.mx53 has the i.mx21 type uart */
+       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+       _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
+       _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
+       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+       /* i.mx53 has the i.mx25 type fec */
+       _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
+       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
+       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+       _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
+       /* i.mx53 has the i.mx51 type ecspi */
+       _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
+       _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
+       /* i.mx53 has the i.mx25 type cspi */
+       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk)
+       _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk)
+       _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
+       _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
+       /* i.mx53 has the i.mx35 type sdma */
+       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
+       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+       _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
+       _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
+       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
+       _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
+       _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
+       _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
+};
+
+static void clk_tree_init(void)
+{
+       u32 reg;
+
+       ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
+
+       /*
+        * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
+        * 8MHz, its derived from lp_apm.
+        *
+        * FIXME: Verify if true for all boards
+        */
+       reg = __raw_readl(MXC_CCM_CBCDR);
+       reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
+       reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
+       reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
+       reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
+       __raw_writel(reg, MXC_CCM_CBCDR);
+}
+
+int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
+                       unsigned long ckih1, unsigned long ckih2)
+{
+       int i;
+
+       external_low_reference = ckil;
+       external_high_reference = ckih1;
+       ckih2_reference = ckih2;
+       oscillator_reference = osc;
+
+       for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
+               clkdev_add(&mx51_lookups[i]);
+
+       clk_tree_init();
+
+       clk_enable(&cpu_clk);
+       clk_enable(&main_bus_clk);
+
+       clk_enable(&iim_clk);
+       imx_print_silicon_rev("i.MX51", mx51_revision());
+       clk_disable(&iim_clk);
+
+       /* move usb_phy_clk to 24MHz */
+       clk_set_parent(&usb_phy1_clk, &osc_clk);
+
+       /* set the usboh3_clk parent to pll2_sw_clk */
+       clk_set_parent(&usboh3_clk, &pll2_sw_clk);
+
+       /* Set SDHC parents to be PLL2 */
+       clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+       clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
+
+       /* set SDHC root clock as 166.25MHZ*/
+       clk_set_rate(&esdhc1_clk, 166250000);
+       clk_set_rate(&esdhc2_clk, 166250000);
+
+       /* System timer */
+       mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
+               MX51_INT_GPT);
+       return 0;
+}
+
+int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
+                       unsigned long ckih1, unsigned long ckih2)
+{
+       int i;
+
+       external_low_reference = ckil;
+       external_high_reference = ckih1;
+       ckih2_reference = ckih2;
+       oscillator_reference = osc;
+
+       for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
+               clkdev_add(&mx53_lookups[i]);
+
+       clk_tree_init();
+
+       clk_set_parent(&uart_root_clk, &pll3_sw_clk);
+       clk_enable(&cpu_clk);
+       clk_enable(&main_bus_clk);
+
+       clk_enable(&iim_clk);
+       imx_print_silicon_rev("i.MX53", mx53_revision());
+       clk_disable(&iim_clk);
+
+       /* Set SDHC parents to be PLL2 */
+       clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+       clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
+
+       /* set SDHC root clock as 200MHZ*/
+       clk_set_rate(&esdhc1_clk, 200000000);
+       clk_set_rate(&esdhc3_mx53_clk, 200000000);
+
+       /* System timer */
+       mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
+               MX53_INT_GPT);
+       return 0;
+}
+
+static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
+                                  unsigned long *ckih1, unsigned long *ckih2)
+{
+       struct device_node *np;
+
+       /* retrieve the freqency of fixed clocks from device tree */
+       for_each_compatible_node(np, NULL, "fixed-clock") {
+               u32 rate;
+               if (of_property_read_u32(np, "clock-frequency", &rate))
+                       continue;
+
+               if (of_device_is_compatible(np, "fsl,imx-ckil"))
+                       *ckil = rate;
+               else if (of_device_is_compatible(np, "fsl,imx-osc"))
+                       *osc = rate;
+               else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+                       *ckih1 = rate;
+               else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
+                       *ckih2 = rate;
+       }
+}
+
+int __init mx51_clocks_init_dt(void)
+{
+       unsigned long ckil, osc, ckih1, ckih2;
+
+       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+       return mx51_clocks_init(ckil, osc, ckih1, ckih2);
+}
+
+int __init mx53_clocks_init_dt(void)
+{
+       unsigned long ckil, osc, ckih1, ckih2;
+
+       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+       return mx53_clocks_init(ckil, osc, ckih1, ckih2);
+}
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
new file mode 100644 (file)
index 0000000..5c53282
--- /dev/null
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ *
+ * This file contains the CPU initialization code.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+static int mx5_cpu_rev = -1;
+
+#define IIM_SREV 0x24
+#define MX50_HW_ADADIG_DIGPROG 0xB0
+
+static int get_mx51_srev(void)
+{
+       void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
+       u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+
+       switch (rev) {
+       case 0x0:
+               return IMX_CHIP_REVISION_2_0;
+       case 0x10:
+               return IMX_CHIP_REVISION_3_0;
+       default:
+               return IMX_CHIP_REVISION_UNKNOWN;
+       }
+}
+
+/*
+ * Returns:
+ *     the silicon revision of the cpu
+ *     -EINVAL - not a mx51
+ */
+int mx51_revision(void)
+{
+       if (!cpu_is_mx51())
+               return -EINVAL;
+
+       if (mx5_cpu_rev == -1)
+               mx5_cpu_rev = get_mx51_srev();
+
+       return mx5_cpu_rev;
+}
+EXPORT_SYMBOL(mx51_revision);
+
+#ifdef CONFIG_NEON
+
+/*
+ * All versions of the silicon before Rev. 3 have broken NEON implementations.
+ * Dependent on link order - so the assumption is that vfp_init is called
+ * before us.
+ */
+static int __init mx51_neon_fixup(void)
+{
+       if (!cpu_is_mx51())
+               return 0;
+
+       if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
+               elf_hwcap &= ~HWCAP_NEON;
+               pr_info("Turning off NEON support, detected broken NEON implementation\n");
+       }
+       return 0;
+}
+
+late_initcall(mx51_neon_fixup);
+#endif
+
+static int get_mx53_srev(void)
+{
+       void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
+       u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+
+       switch (rev) {
+       case 0x0:
+               return IMX_CHIP_REVISION_1_0;
+       case 0x2:
+               return IMX_CHIP_REVISION_2_0;
+       case 0x3:
+               return IMX_CHIP_REVISION_2_1;
+       default:
+               return IMX_CHIP_REVISION_UNKNOWN;
+       }
+}
+
+/*
+ * Returns:
+ *     the silicon revision of the cpu
+ *     -EINVAL - not a mx53
+ */
+int mx53_revision(void)
+{
+       if (!cpu_is_mx53())
+               return -EINVAL;
+
+       if (mx5_cpu_rev == -1)
+               mx5_cpu_rev = get_mx53_srev();
+
+       return mx5_cpu_rev;
+}
+EXPORT_SYMBOL(mx53_revision);
+
+static int get_mx50_srev(void)
+{
+       void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
+       u32 rev;
+
+       if (!anatop) {
+               mx5_cpu_rev = -EINVAL;
+               return 0;
+       }
+
+       rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
+       rev &= 0xff;
+
+       iounmap(anatop);
+       if (rev == 0x0)
+               return IMX_CHIP_REVISION_1_0;
+       else if (rev == 0x1)
+               return IMX_CHIP_REVISION_1_1;
+       return 0;
+}
+
+/*
+ * Returns:
+ *     the silicon revision of the cpu
+ *     -EINVAL - not a mx50
+ */
+int mx50_revision(void)
+{
+       if (!cpu_is_mx50())
+               return -EINVAL;
+
+       if (mx5_cpu_rev == -1)
+               mx5_cpu_rev = get_mx50_srev();
+
+       return mx5_cpu_rev;
+}
+EXPORT_SYMBOL(mx50_revision);
+
+static int __init post_cpu_init(void)
+{
+       unsigned int reg;
+       void __iomem *base;
+
+       if (cpu_is_mx51() || cpu_is_mx53()) {
+               if (cpu_is_mx51())
+                       base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
+               else
+                       base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
+
+               __raw_writel(0x0, base + 0x40);
+               __raw_writel(0x0, base + 0x44);
+               __raw_writel(0x0, base + 0x48);
+               __raw_writel(0x0, base + 0x4C);
+               reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+               __raw_writel(reg, base + 0x50);
+
+               if (cpu_is_mx51())
+                       base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
+               else
+                       base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
+
+               __raw_writel(0x0, base + 0x40);
+               __raw_writel(0x0, base + 0x44);
+               __raw_writel(0x0, base + 0x48);
+               __raw_writel(0x0, base + 0x4C);
+               reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+               __raw_writel(reg, base + 0x50);
+       }
+
+       return 0;
+}
+
+postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
new file mode 100644 (file)
index 0000000..9d34c3d
--- /dev/null
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/types.h>
+#include <mach/hardware.h>
+#include <linux/kernel.h>
+
+static struct cpu_op mx51_cpu_op[] = {
+       {
+       .cpu_rate = 160000000,},
+       {
+       .cpu_rate = 800000000,},
+};
+
+struct cpu_op *mx51_get_cpu_op(int *op)
+{
+       *op = ARRAY_SIZE(mx51_cpu_op);
+       return mx51_cpu_op;
+}
diff --git a/arch/arm/mach-imx/cpu_op-mx51.h b/arch/arm/mach-imx/cpu_op-mx51.h
new file mode 100644 (file)
index 0000000..97477fe
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-imx/crm-regs-imx5.h b/arch/arm/mach-imx/crm-regs-imx5.h
new file mode 100644 (file)
index 0000000..5e11ba7
--- /dev/null
@@ -0,0 +1,600 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MX51_CCM_BASE          MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
+#define MX51_DPLL1_BASE                MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
+#define MX51_DPLL2_BASE                MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
+#define MX51_DPLL3_BASE                MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
+#define MX51_CORTEXA8_BASE     MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
+#define MX51_GPC_BASE          MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
+
+/*MX53*/
+#define MX53_CCM_BASE          MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
+#define MX53_DPLL1_BASE                MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
+#define MX53_DPLL2_BASE                MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
+#define MX53_DPLL3_BASE                MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+#define MX53_DPLL4_BASE                MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL                 0x00
+#define MXC_PLL_DP_CONFIG              0x04
+#define MXC_PLL_DP_OP                  0x08
+#define MXC_PLL_DP_MFD                 0x0C
+#define MXC_PLL_DP_MFN                 0x10
+#define MXC_PLL_DP_MFNMINUS            0x14
+#define MXC_PLL_DP_MFNPLUS             0x18
+#define MXC_PLL_DP_HFS_OP              0x1C
+#define MXC_PLL_DP_HFS_MFD             0x20
+#define MXC_PLL_DP_HFS_MFN             0x24
+#define MXC_PLL_DP_MFN_TOGC            0x28
+#define MXC_PLL_DP_DESTAT              0x2c
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_MUL_CTRL                0x2000
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN     0x1000
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
+#define MXC_PLL_DP_CTL_ADE             0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV     0x400
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK        (3 << 8)
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET      8
+#define MXC_PLL_DP_CTL_HFSM            0x80
+#define MXC_PLL_DP_CTL_PRE             0x40
+#define MXC_PLL_DP_CTL_UPEN            0x20
+#define MXC_PLL_DP_CTL_RST             0x10
+#define MXC_PLL_DP_CTL_RCP             0x8
+#define MXC_PLL_DP_CTL_PLM             0x4
+#define MXC_PLL_DP_CTL_BRM0            0x2
+#define MXC_PLL_DP_CTL_LRF             0x1
+
+#define MXC_PLL_DP_CONFIG_BIST         0x8
+#define MXC_PLL_DP_CONFIG_SJC_CE       0x4
+#define MXC_PLL_DP_CONFIG_AREN         0x2
+#define MXC_PLL_DP_CONFIG_LDREQ                0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET       4
+#define MXC_PLL_DP_OP_MFI_MASK         (0xF << 4)
+#define MXC_PLL_DP_OP_PDF_OFFSET       0
+#define MXC_PLL_DP_OP_PDF_MASK         0xF
+
+#define MXC_PLL_DP_MFD_OFFSET          0
+#define MXC_PLL_DP_MFD_MASK            0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET          0x0
+#define MXC_PLL_DP_MFN_MASK            0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS    (1 << 17)
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN     (1 << 16)
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK   0xFFFF
+
+#define MXC_PLL_DP_DESTAT_TOG_SEL      (1 << 31)
+#define MXC_PLL_DP_DESTAT_MFN          0x07FFFFFF
+
+/* Register addresses of CCM*/
+#define MXC_CCM_CCR            (MX51_CCM_BASE + 0x00)
+#define MXC_CCM_CCDR           (MX51_CCM_BASE + 0x04)
+#define MXC_CCM_CSR            (MX51_CCM_BASE + 0x08)
+#define MXC_CCM_CCSR           (MX51_CCM_BASE + 0x0C)
+#define MXC_CCM_CACRR          (MX51_CCM_BASE + 0x10)
+#define MXC_CCM_CBCDR          (MX51_CCM_BASE + 0x14)
+#define MXC_CCM_CBCMR          (MX51_CCM_BASE + 0x18)
+#define MXC_CCM_CSCMR1         (MX51_CCM_BASE + 0x1C)
+#define MXC_CCM_CSCMR2         (MX51_CCM_BASE + 0x20)
+#define MXC_CCM_CSCDR1         (MX51_CCM_BASE + 0x24)
+#define MXC_CCM_CS1CDR         (MX51_CCM_BASE + 0x28)
+#define MXC_CCM_CS2CDR         (MX51_CCM_BASE + 0x2C)
+#define MXC_CCM_CDCDR          (MX51_CCM_BASE + 0x30)
+#define MXC_CCM_CHSCDR         (MX51_CCM_BASE + 0x34)
+#define MXC_CCM_CSCDR2         (MX51_CCM_BASE + 0x38)
+#define MXC_CCM_CSCDR3         (MX51_CCM_BASE + 0x3C)
+#define MXC_CCM_CSCDR4         (MX51_CCM_BASE + 0x40)
+#define MXC_CCM_CWDR           (MX51_CCM_BASE + 0x44)
+#define MXC_CCM_CDHIPR         (MX51_CCM_BASE + 0x48)
+#define MXC_CCM_CDCR           (MX51_CCM_BASE + 0x4C)
+#define MXC_CCM_CTOR           (MX51_CCM_BASE + 0x50)
+#define MXC_CCM_CLPCR          (MX51_CCM_BASE + 0x54)
+#define MXC_CCM_CISR           (MX51_CCM_BASE + 0x58)
+#define MXC_CCM_CIMR           (MX51_CCM_BASE + 0x5C)
+#define MXC_CCM_CCOSR          (MX51_CCM_BASE + 0x60)
+#define MXC_CCM_CGPR           (MX51_CCM_BASE + 0x64)
+#define MXC_CCM_CCGR0          (MX51_CCM_BASE + 0x68)
+#define MXC_CCM_CCGR1          (MX51_CCM_BASE + 0x6C)
+#define MXC_CCM_CCGR2          (MX51_CCM_BASE + 0x70)
+#define MXC_CCM_CCGR3          (MX51_CCM_BASE + 0x74)
+#define MXC_CCM_CCGR4          (MX51_CCM_BASE + 0x78)
+#define MXC_CCM_CCGR5          (MX51_CCM_BASE + 0x7C)
+#define MXC_CCM_CCGR6          (MX51_CCM_BASE + 0x80)
+#define MXC_CCM_CCGR7          (MX51_CCM_BASE + 0x84)
+
+#define MXC_CCM_CMEOR          (MX51_CCM_BASE + 0x84)
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN            (1 << 12)
+#define MXC_CCM_CCR_FPM_MULT_MASK      (1 << 11)
+#define MXC_CCM_CCR_CAMP2_EN           (1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN           (1 << 9)
+#define MXC_CCM_CCR_FPM_EN             (1 << 8)
+#define MXC_CCM_CCR_OSCNT_OFFSET       (0)
+#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_HSC_HS_MASK       (0x1 << 18)
+#define MXC_CCM_CCDR_IPU_HS_MASK       (0x1 << 17)
+#define MXC_CCM_CCDR_EMI_HS_MASK       (0x1 << 16)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSR_READY (1 << 5)
+#define MXC_CCM_CSR_LVS_VALUE  (1 << 4)
+#define MXC_CCM_CSR_CAMP2_READY        (1 << 3)
+#define MXC_CCM_CSR_CAMP1_READY        (1 << 2)
+#define MXC_CCM_CSR_FPM_READY  (1 << 1)
+#define MXC_CCM_CSR_REF_EN_B   (1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_LP_APM_SEL                (0x1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET   (7)
+#define MXC_CCM_CCSR_STEP_SEL_MASK     (0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL_LP_APM      0
+#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
+#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
+#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
+#define MXC_CCM_CCSR_PLL2_PODF_OFFSET  (5)
+#define MXC_CCM_CCSR_PLL2_PODF_MASK    (0x3 << 5)
+#define MXC_CCM_CCSR_PLL3_PODF_OFFSET  (3)
+#define MXC_CCM_CCSR_PLL3_PODF_MASK    (0x3 << 3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL   (1 << 2) /* 0: pll1_main_clk,
+                                                   1: step_clk */
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL   (1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL   (1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET  (0)
+#define MXC_CCM_CACRR_ARM_PODF_MASK    (0x7)
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_EMI_CLK_SEL              (0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL           (0x1 << 25)
+#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET                (30)
+#define MXC_CCM_CBCDR_DDR_HF_SEL               (0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET          (27)
+#define MXC_CCM_CBCDR_DDR_PODF_MASK            (0x7 << 27)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET          (22)
+#define MXC_CCM_CBCDR_EMI_PODF_MASK            (0x7 << 22)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET                (19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK          (0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET                (16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK          (0x7 << 16)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET          (13)
+#define MXC_CCM_CBCDR_NFC_PODF_MASK            (0x7 << 13)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET          (10)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK            (0x7 << 10)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET          (8)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK            (0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET      (6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK                (0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET      (3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK                (0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET       (0)
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK         (0x7)
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET   (14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK     (0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET    (12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK      (0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET       (10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK         (0x3 << 10)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET   (8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK     (0x3 << 8)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET   (6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK     (0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET       (4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK         (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET     (14)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK       (0x3 << 14)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL    (0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL       (0x1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET         (30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK           (0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET         (28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK           (0x3 << 28)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET          (26)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL                 (0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET             (24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK               (0x3 << 24)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET           (22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK             (0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET     (20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK       (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL                  (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL       (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL                  (0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET     (16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK       (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET      (16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK                (0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             (14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK               (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             (12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK               (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL                    (0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL                    (0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET          (8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK            (0x3 << 8)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL                     (0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL                 (0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET             (4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK               (0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET            (2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK              (0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL            (0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL            (0x1)
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)            (26+n*3)
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n)              (0x7 << (26+n*3))
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET                (24)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK          (0x3 << 24)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET                (22)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK          (0x3 << 22)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET              (20)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK                        (0x3 << 20)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET             (18)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK               (0x3 << 18)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET             (16)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK               (0x3 << 16)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET            (14)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK              (0x3 << 14)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET             (12)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK               (0x3 << 12)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET              (10)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK                        (0x3 << 10)
+#define MXC_CCM_CSCMR2_SLIMBUS_COM                     (0x1 << 9)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET          (6)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK            (0x7 << 6)
+#define MXC_CCM_CSCMR2_SPDIF1_COM                      (1 << 5)
+#define MXC_CCM_CSCMR2_SPDIF0_COM                      (1 << 4)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET           (2)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK             (0x3 << 2)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET           (0)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK             (0x3)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET    (22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK      (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET    (19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK      (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET     (22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK       (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET     (19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK       (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET    (16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK      (0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET             (14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK               (0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET    (11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK      (0x7 << 11)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET          (8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK            (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          (6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET            (3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK              (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET            (0)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x7)
+
+/* Define the bits in register CS1CDR and CS2CDR */
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET                (22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK          (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET                (16)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK          (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET            (6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET            (0)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK              (0x3F)
+
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET                (22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK          (0x7 << 22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET                (16)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK          (0x3F << 16)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET            (6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET            (0)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK              (0x3F)
+
+/* Define the bits in register CDCDR */
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET              (28)
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK                        (0x7 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET           (25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK             (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET           (19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK             (0x3F << 19)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET           (16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK             (0x7 << 16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET           (9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK             (0x3F << 9)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET               (6)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK                 (0x7 << 6)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET              (3)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK                        (0x7 << 3)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET              (0)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK                        (0x7)
+
+/* Define the bits in register CHSCCDR */
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET            (12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK              (0x7 << 12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET            (6)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK              (0x3F << 6)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET           (3)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK             (0x7 << 3)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET           (0)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK             (0x7)
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET            (25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK              (0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET            (19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK              (0x3F << 19)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET             (16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK               (0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET             (9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK               (0x3F << 9)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET         (6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK               (0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET             (0)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK               (0x3F)
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET           (16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK             (0x7 << 16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET           (9)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK             (0x3F << 9)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET            (6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK              (0x7 << 6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET            (0)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK              (0x3F)
+
+/* Define the bits in register CSCDR4 */
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET       (16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK         (0x7 << 16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET       (9)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK         (0x3F << 9)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET       (6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK         (0x7 << 6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET       (0)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK         (0x3F)
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY                   (1 << 16)
+#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY             (1 << 8)
+#define MXC_CCM_CDHIPR_DDR_PODF_BUSY                   (1 << 7)
+#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY                        (1 << 6)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY             (1 << 5)
+#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY       (1 << 4)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY                   (1 << 3)
+#define MXC_CCM_CDHIPR_EMI_PODF_BUSY                   (1 << 2)
+#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY                 (1 << 1)
+#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY                 (1 << 0)
+
+/* Define the bits in register CDCR */
+#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER            (0x1 << 2)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET       (0)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK         (0x3)
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS                (0x1 << 23)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS                (0x1 << 22)
+#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS               (0x1 << 21)
+#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS               (0x1 << 25)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS       (0x1 << 20)
+#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS                (0x1 << 19)
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                (0x1 << 18)
+#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS       (0x1 << 17)
+#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS       (0x1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN             (0x1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                (9)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK          (0x3 << 9)
+#define MXC_CCM_CLPCR_VSTBY                    (0x1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC              (0x1 << 7)
+#define MXC_CCM_CLPCR_SBYOS                    (0x1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM       (0x1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET      (3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                (0x3 << 3)
+#define MXC_CCM_CLPCR_LPM_OFFSET               (0)
+#define MXC_CCM_CLPCR_LPM_MASK                 (0x3)
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED                   (0x1 << 25)
+#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED       (0x1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED                   (0x1 << 20)
+#define MXC_CCM_CISR_EMI_PODF_LOADED                   (0x1 << 19)
+#define MXC_CCM_CISR_AXI_B_PODF_LOADED                 (0x1 << 18)
+#define MXC_CCM_CISR_AXI_A_PODF_LOADED                 (0x1 << 17)
+#define MXC_CCM_CISR_DIVIDER_LOADED                    (0x1 << 16)
+#define MXC_CCM_CISR_COSC_READY                                (0x1 << 6)
+#define MXC_CCM_CISR_CKIH2_READY                       (0x1 << 5)
+#define MXC_CCM_CISR_CKIH_READY                                (0x1 << 4)
+#define MXC_CCM_CISR_FPM_READY                         (0x1 << 3)
+#define MXC_CCM_CISR_LRF_PLL3                          (0x1 << 2)
+#define MXC_CCM_CISR_LRF_PLL2                          (0x1 << 1)
+#define MXC_CCM_CISR_LRF_PLL1                          (0x1)
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED              (0x1 << 25)
+#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED  (0x1 << 21)
+#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED              (0x1 << 20)
+#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED            (0x1 << 19)
+#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED            (0x1 << 18)
+#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED            (0x1 << 17)
+#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED               (0x1 << 16)
+#define MXC_CCM_CIMR_MASK_COSC_READY                   (0x1 << 5)
+#define MXC_CCM_CIMR_MASK_CKIH_READY                   (0x1 << 4)
+#define MXC_CCM_CIMR_MASK_FPM_READY                    (0x1 << 3)
+#define MXC_CCM_CIMR_MASK_LRF_PLL3                     (0x1 << 2)
+#define MXC_CCM_CIMR_MASK_LRF_PLL2                     (0x1 << 1)
+#define MXC_CCM_CIMR_MASK_LRF_PLL1                     (0x1)
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET                   (0x1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                  (21)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK                    (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                  (16)
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK                    (0x1F << 16)
+#define MXC_CCM_CCOSR_CKOL_EN                          (0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                  (4)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK                    (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                  (0)
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK                    (0xF)
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE            (0x1 << 4)
+#define MXC_CCM_CGPR_FPM_SEL                           (0x1 << 3)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET           (0)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK             (0x7)
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGRx_CG_MASK                          0x3
+#define MXC_CCM_CCGRx_MOD_OFF                          0x0
+#define MXC_CCM_CCGRx_MOD_ON                           0x3
+#define MXC_CCM_CCGRx_MOD_IDLE                         0x1
+
+#define MXC_CCM_CCGRx_CG15_MASK                                (0x3 << 30)
+#define MXC_CCM_CCGRx_CG14_MASK                                (0x3 << 28)
+#define MXC_CCM_CCGRx_CG13_MASK                                (0x3 << 26)
+#define MXC_CCM_CCGRx_CG12_MASK                                (0x3 << 24)
+#define MXC_CCM_CCGRx_CG11_MASK                                (0x3 << 22)
+#define MXC_CCM_CCGRx_CG10_MASK                                (0x3 << 20)
+#define MXC_CCM_CCGRx_CG9_MASK                         (0x3 << 18)
+#define MXC_CCM_CCGRx_CG8_MASK                         (0x3 << 16)
+#define MXC_CCM_CCGRx_CG5_MASK                         (0x3 << 10)
+#define MXC_CCM_CCGRx_CG4_MASK                         (0x3 << 8)
+#define MXC_CCM_CCGRx_CG3_MASK                         (0x3 << 6)
+#define MXC_CCM_CCGRx_CG2_MASK                         (0x3 << 4)
+#define MXC_CCM_CCGRx_CG1_MASK                         (0x3 << 2)
+#define MXC_CCM_CCGRx_CG0_MASK                         (0x3 << 0)
+
+#define MXC_CCM_CCGRx_CG15_OFFSET                      30
+#define MXC_CCM_CCGRx_CG14_OFFSET                      28
+#define MXC_CCM_CCGRx_CG13_OFFSET                      26
+#define MXC_CCM_CCGRx_CG12_OFFSET                      24
+#define MXC_CCM_CCGRx_CG11_OFFSET                      22
+#define MXC_CCM_CCGRx_CG10_OFFSET                      20
+#define MXC_CCM_CCGRx_CG9_OFFSET                       18
+#define MXC_CCM_CCGRx_CG8_OFFSET                       16
+#define MXC_CCM_CCGRx_CG7_OFFSET                       14
+#define MXC_CCM_CCGRx_CG6_OFFSET                       12
+#define MXC_CCM_CCGRx_CG5_OFFSET                       10
+#define MXC_CCM_CCGRx_CG4_OFFSET                       8
+#define MXC_CCM_CCGRx_CG3_OFFSET                       6
+#define MXC_CCM_CCGRx_CG2_OFFSET                       4
+#define MXC_CCM_CCGRx_CG1_OFFSET                       2
+#define MXC_CCM_CCGRx_CG0_OFFSET                       0
+
+#define MXC_DPTC_LP_BASE       (MX51_GPC_BASE + 0x80)
+#define MXC_DPTC_GP_BASE       (MX51_GPC_BASE + 0x100)
+#define MXC_DVFS_CORE_BASE     (MX51_GPC_BASE + 0x180)
+#define MXC_DPTC_PER_BASE      (MX51_GPC_BASE + 0x1C0)
+#define MXC_PGC_IPU_BASE       (MX51_GPC_BASE + 0x220)
+#define MXC_PGC_VPU_BASE       (MX51_GPC_BASE + 0x240)
+#define MXC_PGC_GPU_BASE       (MX51_GPC_BASE + 0x260)
+#define MXC_SRPG_NEON_BASE     (MX51_GPC_BASE + 0x280)
+#define MXC_SRPG_ARM_BASE      (MX51_GPC_BASE + 0x2A0)
+#define MXC_SRPG_EMPGC0_BASE   (MX51_GPC_BASE + 0x2C0)
+#define MXC_SRPG_EMPGC1_BASE   (MX51_GPC_BASE + 0x2D0)
+#define MXC_SRPG_MEGAMIX_BASE  (MX51_GPC_BASE + 0x2E0)
+#define MXC_SRPG_EMI_BASE      (MX51_GPC_BASE + 0x300)
+
+/* CORTEXA8 platform */
+#define MXC_CORTEXA8_PLAT_PVID         (MX51_CORTEXA8_BASE + 0x0)
+#define MXC_CORTEXA8_PLAT_GPC          (MX51_CORTEXA8_BASE + 0x4)
+#define MXC_CORTEXA8_PLAT_PIC          (MX51_CORTEXA8_BASE + 0x8)
+#define MXC_CORTEXA8_PLAT_LPC          (MX51_CORTEXA8_BASE + 0xC)
+#define MXC_CORTEXA8_PLAT_NEON_LPC     (MX51_CORTEXA8_BASE + 0x10)
+#define MXC_CORTEXA8_PLAT_ICGC         (MX51_CORTEXA8_BASE + 0x14)
+#define MXC_CORTEXA8_PLAT_AMC          (MX51_CORTEXA8_BASE + 0x18)
+#define MXC_CORTEXA8_PLAT_NMC          (MX51_CORTEXA8_BASE + 0x20)
+#define MXC_CORTEXA8_PLAT_NMS          (MX51_CORTEXA8_BASE + 0x24)
+
+/* DVFS CORE */
+#define MXC_DVFSTHRS           (MXC_DVFS_CORE_BASE + 0x00)
+#define MXC_DVFSCOUN           (MXC_DVFS_CORE_BASE + 0x04)
+#define MXC_DVFSSIG1           (MXC_DVFS_CORE_BASE + 0x08)
+#define MXC_DVFSSIG0           (MXC_DVFS_CORE_BASE + 0x0C)
+#define MXC_DVFSGPC0           (MXC_DVFS_CORE_BASE + 0x10)
+#define MXC_DVFSGPC1           (MXC_DVFS_CORE_BASE + 0x14)
+#define MXC_DVFSGPBT           (MXC_DVFS_CORE_BASE + 0x18)
+#define MXC_DVFSEMAC           (MXC_DVFS_CORE_BASE + 0x1C)
+#define MXC_DVFSCNTR           (MXC_DVFS_CORE_BASE + 0x20)
+#define MXC_DVFSLTR0_0         (MXC_DVFS_CORE_BASE + 0x24)
+#define MXC_DVFSLTR0_1         (MXC_DVFS_CORE_BASE + 0x28)
+#define MXC_DVFSLTR1_0         (MXC_DVFS_CORE_BASE + 0x2C)
+#define MXC_DVFSLTR1_1         (MXC_DVFS_CORE_BASE + 0x30)
+#define MXC_DVFSPT0            (MXC_DVFS_CORE_BASE + 0x34)
+#define MXC_DVFSPT1            (MXC_DVFS_CORE_BASE + 0x38)
+#define MXC_DVFSPT2            (MXC_DVFS_CORE_BASE + 0x3C)
+#define MXC_DVFSPT3            (MXC_DVFS_CORE_BASE + 0x40)
+
+/* GPC */
+#define MXC_GPC_CNTR           (MX51_GPC_BASE + 0x0)
+#define MXC_GPC_PGR            (MX51_GPC_BASE + 0x4)
+#define MXC_GPC_VCR            (MX51_GPC_BASE + 0x8)
+#define MXC_GPC_ALL_PU         (MX51_GPC_BASE + 0xC)
+#define MXC_GPC_NEON           (MX51_GPC_BASE + 0x10)
+#define MXC_GPC_PGR_ARMPG_OFFSET       8
+#define MXC_GPC_PGR_ARMPG_MASK         (3 << 8)
+
+/* PGC */
+#define MXC_PGC_IPU_PGCR       (MXC_PGC_IPU_BASE + 0x0)
+#define MXC_PGC_IPU_PGSR       (MXC_PGC_IPU_BASE + 0xC)
+#define MXC_PGC_VPU_PGCR       (MXC_PGC_VPU_BASE + 0x0)
+#define MXC_PGC_VPU_PGSR       (MXC_PGC_VPU_BASE + 0xC)
+#define MXC_PGC_GPU_PGCR       (MXC_PGC_GPU_BASE + 0x0)
+#define MXC_PGC_GPU_PGSR       (MXC_PGC_GPU_BASE + 0xC)
+
+#define MXC_PGCR_PCR           1
+#define MXC_SRPGCR_PCR         1
+#define MXC_EMPGCR_PCR         1
+#define MXC_PGSR_PSR           1
+
+
+#define MXC_CORTEXA8_PLAT_LPC_DSM      (1 << 0)
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM  (1 << 1)
+
+/* SRPG */
+#define MXC_SRPG_NEON_SRPGCR   (MXC_SRPG_NEON_BASE + 0x0)
+#define MXC_SRPG_NEON_PUPSCR   (MXC_SRPG_NEON_BASE + 0x4)
+#define MXC_SRPG_NEON_PDNSCR   (MXC_SRPG_NEON_BASE + 0x8)
+
+#define MXC_SRPG_ARM_SRPGCR    (MXC_SRPG_ARM_BASE + 0x0)
+#define MXC_SRPG_ARM_PUPSCR    (MXC_SRPG_ARM_BASE + 0x4)
+#define MXC_SRPG_ARM_PDNSCR    (MXC_SRPG_ARM_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
+#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
+#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
+#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
+#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
+
+#define MXC_SRPG_MEGAMIX_SRPGCR                (MXC_SRPG_MEGAMIX_BASE + 0x0)
+#define MXC_SRPG_MEGAMIX_PUPSCR                (MXC_SRPG_MEGAMIX_BASE + 0x4)
+#define MXC_SRPG_MEGAMIX_PDNSCR                (MXC_SRPG_MEGAMIX_BASE + 0x8)
+
+#define MXC_SRPGC_EMI_SRPGCR   (MXC_SRPGC_EMI_BASE + 0x0)
+#define MXC_SRPGC_EMI_PUPSCR   (MXC_SRPGC_EMI_BASE + 0x4)
+#define MXC_SRPGC_EMI_PDNSCR   (MXC_SRPGC_EMI_BASE + 0x8)
+
+#endif                         /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-imx/devices-imx50.h b/arch/arm/mach-imx/devices-imx50.h
new file mode 100644 (file)
index 0000000..7216667
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/mx50.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
+#define imx50_add_imx_uart(id, pdata)  \
+       imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
+
+extern const struct imx_fec_data imx50_fec_data;
+#define imx50_add_fec(pdata)   \
+       imx_add_fec(&imx50_fec_data, pdata)
+
+extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
+#define imx50_add_imx_i2c(id, pdata)   \
+       imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
new file mode 100644 (file)
index 0000000..af488bc
--- /dev/null
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx51.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_fec_data imx51_fec_data;
+#define imx51_add_fec(pdata)   \
+       imx_add_fec(&imx51_fec_data, pdata)
+
+extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
+#define imx51_add_fsl_usb2_udc(pdata)  \
+       imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
+
+extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
+#define imx51_add_imx_i2c(id, pdata)   \
+       imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
+#define imx51_add_hsi2c(pdata) \
+       imx51_add_imx_i2c(2, pdata)
+
+extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
+#define imx51_add_imx_ssi(id, pdata)   \
+       imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
+#define imx51_add_imx_uart(id, pdata)  \
+       imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
+
+extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
+#define imx51_add_mxc_ehci_otg(pdata)  \
+       imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
+extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
+#define imx51_add_mxc_ehci_hs(id, pdata)       \
+       imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
+
+extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
+#define imx51_add_mxc_nand(pdata)      \
+       imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
+
+extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
+#define imx51_add_sdhci_esdhc_imx(id, pdata)   \
+       imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
+
+extern const struct imx_spi_imx_data imx51_cspi_data;
+#define imx51_add_cspi(pdata)  \
+       imx_add_spi_imx(&imx51_cspi_data, pdata)
+
+extern const struct imx_spi_imx_data imx51_ecspi_data[];
+#define imx51_add_ecspi(id, pdata)     \
+       imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
+
+extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
+#define imx51_add_imx2_wdt(id, pdata)  \
+       imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
+
+extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
+#define imx51_add_mxc_pwm(id)  \
+       imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
+
+extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
+#define imx51_add_imx_keypad(pdata)    \
+       imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
+
+extern const struct imx_pata_imx_data imx51_pata_imx_data;
+#define imx51_add_pata_imx() \
+       imx_add_pata_imx(&imx51_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
new file mode 100644 (file)
index 0000000..6e1e5d1
--- /dev/null
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx53.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_fec_data imx53_fec_data;
+#define imx53_add_fec(pdata)   \
+       imx_add_fec(&imx53_fec_data, pdata)
+
+extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
+#define imx53_add_imx_uart(id, pdata)  \
+       imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
+
+
+extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
+#define imx53_add_imx_i2c(id, pdata)   \
+       imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
+
+extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
+#define imx53_add_sdhci_esdhc_imx(id, pdata)   \
+       imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
+
+extern const struct imx_spi_imx_data imx53_ecspi_data[];
+#define imx53_add_ecspi(id, pdata)     \
+       imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
+
+extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
+#define imx53_add_imx2_wdt(id, pdata)  \
+       imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
+
+extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
+#define imx53_add_imx_ssi(id, pdata)   \
+       imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
+#define imx53_add_imx_keypad(pdata)    \
+       imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
+
+extern const struct imx_pata_imx_data imx53_pata_imx_data;
+#define imx53_add_pata_imx() \
+       imx_add_pata_imx(&imx53_pata_imx_data)
+
+extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h
new file mode 100644 (file)
index 0000000..014aa98
--- /dev/null
@@ -0,0 +1,10 @@
+#ifndef _EFIKA_H
+#define _EFIKA_H
+
+#define EFIKA_WLAN_EN          IMX_GPIO_NR(2, 16)
+#define EFIKA_WLAN_RESET       IMX_GPIO_NR(2, 10)
+#define EFIKA_USB_PHY_RESET    IMX_GPIO_NR(2, 9)
+
+void __init efika_board_common_init(void);
+
+#endif
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
new file mode 100644 (file)
index 0000000..c17fa13
--- /dev/null
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define MXC_OTG_OFFSET                 0
+#define MXC_H1_OFFSET                  0x200
+#define MXC_H2_OFFSET                  0x400
+
+/* USB_CTRL */
+#define MXC_OTG_UCTRL_OWIE_BIT         (1 << 27)       /* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT          (1 << 24)       /* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT         (1 << 12)       /* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT         (1 << 11)       /* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT          (1 <<  8)               /* HOST1 power mask */
+
+/* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT     (1 << 8)        /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT              (1 << 5)        /* UH1 Disable Overcurrent Event */
+
+/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2UIE_BIT         (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT         (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT          (1 << 4)
+
+#define MXC_USBCMD_OFFSET              0x140
+
+/* USBCMD */
+#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
+
+int mx51_initialize_usb_hw(int port, unsigned int flags)
+{
+       unsigned int v;
+       void __iomem *usb_base;
+       void __iomem *usbotg_base;
+       void __iomem *usbother_base;
+       int ret = 0;
+
+       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
+       if (!usb_base) {
+               printk(KERN_ERR "%s(): ioremap failed\n", __func__);
+               return -ENOMEM;
+       }
+
+       switch (port) {
+       case 0: /* OTG port */
+               usbotg_base = usb_base + MXC_OTG_OFFSET;
+               break;
+       case 1: /* Host 1 port */
+               usbotg_base = usb_base + MXC_H1_OFFSET;
+               break;
+       case 2: /* Host 2 port */
+               usbotg_base = usb_base + MXC_H2_OFFSET;
+               break;
+       default:
+               printk(KERN_ERR"%s no such port %d\n", __func__, port);
+               ret = -ENOENT;
+               goto error;
+       }
+       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+       switch (port) {
+       case 0: /*OTG port */
+               if (flags & MXC_EHCI_INTERNAL_PHY) {
+                       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                       if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
+                               /* OC/USBPWR is not used */
+                               v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                       } else {
+                               /* OC/USBPWR is used */
+                               v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                       }
+                       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                       v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+                       if (flags & MXC_EHCI_WAKEUP_ENABLED)
+                               v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
+                       else
+                               v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
+                       if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                               v |= MXC_OTG_UCTRL_OPM_BIT;
+                       else
+                               v &= ~MXC_OTG_UCTRL_OPM_BIT;
+                       __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+               }
+               break;
+       case 1: /* Host 1 */
+               /*Host ULPI */
+               v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+               if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                       /* HOST1 wakeup/ULPI intr enable */
+                       v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+               } else {
+                       /* HOST1 wakeup/ULPI intr disable */
+                       v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+               }
+
+               if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                       v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+               else
+                       v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+               __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+
+               v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+               if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                       v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
+               else
+                       v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
+               __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+               v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
+               if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
+                       /* Interrupt Threshold Control:Immediate (no threshold) */
+                       v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
+               __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
+               break;
+       case 2: /* Host 2 ULPI */
+               v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+               if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                       /* HOST1 wakeup/ULPI intr enable */
+                       v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+               } else {
+                       /* HOST1 wakeup/ULPI intr disable */
+                       v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+               }
+
+               if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                       v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+               else
+                       v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+               __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
+               break;
+       }
+
+error:
+       iounmap(usb_base);
+       return ret;
+}
+
diff --git a/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c
new file mode 100644 (file)
index 0000000..a6a3ab8
--- /dev/null
@@ -0,0 +1,206 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/leds.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+
+#include <asm/mach/arch.h>
+
+#include "devices-imx51.h"
+
+#define MBIMX51_TSC2007_GPIO   IMX_GPIO_NR(3, 30)
+#define MBIMX51_LED0           IMX_GPIO_NR(3, 5)
+#define MBIMX51_LED1           IMX_GPIO_NR(3, 6)
+#define MBIMX51_LED2           IMX_GPIO_NR(3, 7)
+#define MBIMX51_LED3           IMX_GPIO_NR(3, 8)
+
+static const struct gpio_led mbimx51_leds[] __initconst = {
+       {
+               .name                   = "led0",
+               .default_trigger        = "heartbeat",
+               .active_low             = 1,
+               .gpio                   = MBIMX51_LED0,
+       },
+       {
+               .name                   = "led1",
+               .default_trigger        = "nand-disk",
+               .active_low             = 1,
+               .gpio                   = MBIMX51_LED1,
+       },
+       {
+               .name                   = "led2",
+               .default_trigger        = "mmc0",
+               .active_low             = 1,
+               .gpio                   = MBIMX51_LED2,
+       },
+       {
+               .name                   = "led3",
+               .default_trigger        = "default-on",
+               .active_low             = 1,
+               .gpio                   = MBIMX51_LED3,
+       },
+};
+
+static const struct gpio_led_platform_data mbimx51_leds_info __initconst = {
+       .leds           = mbimx51_leds,
+       .num_leds       = ARRAY_SIZE(mbimx51_leds),
+};
+
+static iomux_v3_cfg_t mbimx51_pads[] = {
+       /* UART2 */
+       MX51_PAD_UART2_RXD__UART2_RXD,
+       MX51_PAD_UART2_TXD__UART2_TXD,
+
+       /* UART3 */
+       MX51_PAD_UART3_RXD__UART3_RXD,
+       MX51_PAD_UART3_TXD__UART3_TXD,
+       MX51_PAD_KEY_COL4__UART3_RTS,
+       MX51_PAD_KEY_COL5__UART3_CTS,
+
+       /* TSC2007 IRQ */
+       MX51_PAD_NANDF_D10__GPIO3_30,
+
+       /* LEDS */
+       MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
+       MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
+       MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
+       MX51_PAD_DISPB2_SER_RS__GPIO3_8,
+
+       /* KPP */
+       MX51_PAD_KEY_ROW0__KEY_ROW0,
+       MX51_PAD_KEY_ROW1__KEY_ROW1,
+       MX51_PAD_KEY_ROW2__KEY_ROW2,
+       MX51_PAD_KEY_ROW3__KEY_ROW3,
+       MX51_PAD_KEY_COL0__KEY_COL0,
+       MX51_PAD_KEY_COL1__KEY_COL1,
+       MX51_PAD_KEY_COL2__KEY_COL2,
+       MX51_PAD_KEY_COL3__KEY_COL3,
+
+       /* SD 1 */
+       MX51_PAD_SD1_CMD__SD1_CMD,
+       MX51_PAD_SD1_CLK__SD1_CLK,
+       MX51_PAD_SD1_DATA0__SD1_DATA0,
+       MX51_PAD_SD1_DATA1__SD1_DATA1,
+       MX51_PAD_SD1_DATA2__SD1_DATA2,
+       MX51_PAD_SD1_DATA3__SD1_DATA3,
+
+       /* SD 2 */
+       MX51_PAD_SD2_CMD__SD2_CMD,
+       MX51_PAD_SD2_CLK__SD2_CLK,
+       MX51_PAD_SD2_DATA0__SD2_DATA0,
+       MX51_PAD_SD2_DATA1__SD2_DATA1,
+       MX51_PAD_SD2_DATA2__SD2_DATA2,
+       MX51_PAD_SD2_DATA3__SD2_DATA3,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static int mbimx51_keymap[] = {
+       KEY(0, 0, KEY_1),
+       KEY(0, 1, KEY_2),
+       KEY(0, 2, KEY_3),
+       KEY(0, 3, KEY_UP),
+
+       KEY(1, 0, KEY_4),
+       KEY(1, 1, KEY_5),
+       KEY(1, 2, KEY_6),
+       KEY(1, 3, KEY_LEFT),
+
+       KEY(2, 0, KEY_7),
+       KEY(2, 1, KEY_8),
+       KEY(2, 2, KEY_9),
+       KEY(2, 3, KEY_RIGHT),
+
+       KEY(3, 0, KEY_0),
+       KEY(3, 1, KEY_DOWN),
+       KEY(3, 2, KEY_ESC),
+       KEY(3, 3, KEY_ENTER),
+};
+
+static const struct matrix_keymap_data mbimx51_map_data __initconst = {
+       .keymap         = mbimx51_keymap,
+       .keymap_size    = ARRAY_SIZE(mbimx51_keymap),
+};
+
+static int tsc2007_get_pendown_state(void)
+{
+       return !gpio_get_value(MBIMX51_TSC2007_GPIO);
+}
+
+struct tsc2007_platform_data tsc2007_data = {
+       .model = 2007,
+       .x_plate_ohms = 180,
+       .get_pendown_state = tsc2007_get_pendown_state,
+};
+
+static struct i2c_board_info mbimx51_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("tsc2007", 0x49),
+               .irq  = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO),
+               .platform_data = &tsc2007_data,
+       }, {
+               I2C_BOARD_INFO("tlv320aic23", 0x1a),
+       },
+};
+
+/*
+ * baseboard initialization.
+ */
+void __init eukrea_mbimx51_baseboard_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
+                                       ARRAY_SIZE(mbimx51_pads));
+
+       imx51_add_imx_uart(1, NULL);
+       imx51_add_imx_uart(2, &uart_pdata);
+
+       gpio_request(MBIMX51_LED0, "LED0");
+       gpio_direction_output(MBIMX51_LED0, 1);
+       gpio_free(MBIMX51_LED0);
+       gpio_request(MBIMX51_LED1, "LED1");
+       gpio_direction_output(MBIMX51_LED1, 1);
+       gpio_free(MBIMX51_LED1);
+       gpio_request(MBIMX51_LED2, "LED2");
+       gpio_direction_output(MBIMX51_LED2, 1);
+       gpio_free(MBIMX51_LED2);
+       gpio_request(MBIMX51_LED3, "LED3");
+       gpio_direction_output(MBIMX51_LED3, 1);
+       gpio_free(MBIMX51_LED3);
+
+       gpio_led_register_device(-1, &mbimx51_leds_info);
+
+       imx51_add_imx_keypad(&mbimx51_map_data);
+
+       gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
+       gpio_direction_input(MBIMX51_TSC2007_GPIO);
+       irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO),
+                                       IRQF_TRIGGER_FALLING);
+       i2c_register_board_info(1, mbimx51_i2c_devices,
+                               ARRAY_SIZE(mbimx51_i2c_devices));
+
+       imx51_add_sdhci_esdhc_imx(0, NULL);
+       imx51_add_sdhci_esdhc_imx(1, NULL);
+}
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
new file mode 100644 (file)
index 0000000..d817fc8
--- /dev/null
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/audmux.h>
+
+#include "devices-imx51.h"
+
+static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
+       /* LED */
+       MX51_PAD_NANDF_D10__GPIO3_30,
+       /* SWITCH */
+       NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
+                       PAD_CTL_PKE | PAD_CTL_SRE_FAST |
+                       PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
+       /* UART2 */
+       MX51_PAD_UART2_RXD__UART2_RXD,
+       MX51_PAD_UART2_TXD__UART2_TXD,
+       /* UART 3 */
+       MX51_PAD_UART3_RXD__UART3_RXD,
+       MX51_PAD_UART3_TXD__UART3_TXD,
+       MX51_PAD_KEY_COL4__UART3_RTS,
+       MX51_PAD_KEY_COL5__UART3_CTS,
+       /* SD */
+       MX51_PAD_SD1_CMD__SD1_CMD,
+       MX51_PAD_SD1_CLK__SD1_CLK,
+       MX51_PAD_SD1_DATA0__SD1_DATA0,
+       MX51_PAD_SD1_DATA1__SD1_DATA1,
+       MX51_PAD_SD1_DATA2__SD1_DATA2,
+       MX51_PAD_SD1_DATA3__SD1_DATA3,
+       /* SD1 CD */
+       NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
+                       PAD_CTL_PKE | PAD_CTL_SRE_FAST |
+                       PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
+};
+
+#define GPIO_LED1      IMX_GPIO_NR(3, 30)
+#define GPIO_SWITCH1   IMX_GPIO_NR(3, 31)
+
+static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
+       {
+               .name                   = "led1",
+               .default_trigger        = "heartbeat",
+               .active_low             = 1,
+               .gpio                   = GPIO_LED1,
+       },
+};
+
+static const struct gpio_led_platform_data
+               eukrea_mbimxsd_led_info __initconst = {
+       .leds           = eukrea_mbimxsd_leds,
+       .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+       {
+               .gpio           = GPIO_SWITCH1,
+               .code           = BTN_0,
+               .desc           = "BP1",
+               .active_low     = 1,
+               .wakeup         = 1,
+       },
+};
+
+static const struct gpio_keys_platform_data
+               eukrea_mbimxsd_button_data __initconst = {
+       .buttons        = eukrea_mbimxsd_gpio_buttons,
+       .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("tlv320aic23", 0x1a),
+       },
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx51sd init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd51_baseboard_init(void)
+{
+       if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+                       ARRAY_SIZE(eukrea_mbimxsd_pads)))
+               printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+       imx51_add_imx_uart(1, NULL);
+       imx51_add_imx_uart(2, &uart_pdata);
+
+       imx51_add_sdhci_esdhc_imx(0, NULL);
+
+       gpio_request(GPIO_LED1, "LED1");
+       gpio_direction_output(GPIO_LED1, 1);
+       gpio_free(GPIO_LED1);
+
+       gpio_request(GPIO_SWITCH1, "SWITCH1");
+       gpio_direction_input(GPIO_SWITCH1);
+       gpio_free(GPIO_SWITCH1);
+
+       i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+                               ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+       gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
+       imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
+}
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
new file mode 100644 (file)
index 0000000..ccc6158
--- /dev/null
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx51.h>
+
+/*
+ * Lookup table for attaching a specific name and platform_data pointer to
+ * devices as they get created by of_platform_populate().  Ideally this table
+ * would not exist, but the current clock implementation depends on some devices
+ * having a specific name.
+ */
+static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
+       OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
+       OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
+       { /* sentinel */ }
+};
+
+static void __init imx51_tzic_add_irq_domain(struct device_node *np,
+                               struct device_node *interrupt_parent)
+{
+       irq_domain_add_simple(np, 0);
+}
+
+static void __init imx51_gpio_add_irq_domain(struct device_node *np,
+                               struct device_node *interrupt_parent)
+{
+       static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
+                                  32 * 4; /* imx51 gets 4 gpio ports */
+
+       irq_domain_add_simple(np, gpio_irq_base);
+       gpio_irq_base += 32;
+}
+
+static const struct of_device_id imx51_irq_match[] __initconst = {
+       { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
+       { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
+       { /* sentinel */ }
+};
+
+static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
+       { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
+       { /* sentinel */ }
+};
+
+static void __init imx51_dt_init(void)
+{
+       struct device_node *node;
+       const struct of_device_id *of_id;
+       void (*func)(void);
+
+       of_irq_init(imx51_irq_match);
+
+       node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
+       if (node) {
+               of_id = of_match_node(imx51_iomuxc_of_match, node);
+               func = of_id->data;
+               func();
+               of_node_put(node);
+       }
+
+       of_platform_populate(NULL, of_default_bus_match_table,
+                            imx51_auxdata_lookup, NULL);
+}
+
+static void __init imx51_timer_init(void)
+{
+       mx51_clocks_init_dt();
+}
+
+static struct sys_timer imx51_timer = {
+       .init = imx51_timer_init,
+};
+
+static const char *imx51_dt_board_compat[] __initdata = {
+       "fsl,imx51-babbage",
+       NULL
+};
+
+DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
+       .map_io         = mx51_map_io,
+       .init_early     = imx51_init_early,
+       .init_irq       = mx51_init_irq,
+       .handle_irq     = imx51_handle_irq,
+       .timer          = &imx51_timer,
+       .init_machine   = imx51_dt_init,
+       .dt_compat      = imx51_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
new file mode 100644 (file)
index 0000000..ccaa0b8
--- /dev/null
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx53.h>
+
+/*
+ * Lookup table for attaching a specific name and platform_data pointer to
+ * devices as they get created by of_platform_populate().  Ideally this table
+ * would not exist, but the current clock implementation depends on some devices
+ * having a specific name.
+ */
+static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
+       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
+       OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
+       { /* sentinel */ }
+};
+
+static void __init imx53_tzic_add_irq_domain(struct device_node *np,
+                               struct device_node *interrupt_parent)
+{
+       irq_domain_add_simple(np, 0);
+}
+
+static void __init imx53_gpio_add_irq_domain(struct device_node *np,
+                               struct device_node *interrupt_parent)
+{
+       static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
+                                  32 * 7; /* imx53 gets 7 gpio ports */
+
+       irq_domain_add_simple(np, gpio_irq_base);
+       gpio_irq_base += 32;
+}
+
+static const struct of_device_id imx53_irq_match[] __initconst = {
+       { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
+       { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
+       { /* sentinel */ }
+};
+
+static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
+       { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
+       { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
+       { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
+       { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
+       { /* sentinel */ }
+};
+
+static void __init imx53_dt_init(void)
+{
+       struct device_node *node;
+       const struct of_device_id *of_id;
+       void (*func)(void);
+
+       of_irq_init(imx53_irq_match);
+
+       node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
+       if (node) {
+               of_id = of_match_node(imx53_iomuxc_of_match, node);
+               func = of_id->data;
+               func();
+               of_node_put(node);
+       }
+
+       of_platform_populate(NULL, of_default_bus_match_table,
+                            imx53_auxdata_lookup, NULL);
+}
+
+static void __init imx53_timer_init(void)
+{
+       mx53_clocks_init_dt();
+}
+
+static struct sys_timer imx53_timer = {
+       .init = imx53_timer_init,
+};
+
+static const char *imx53_dt_board_compat[] __initdata = {
+       "fsl,imx53-ard",
+       "fsl,imx53-evk",
+       "fsl,imx53-qsb",
+       "fsl,imx53-smd",
+       NULL
+};
+
+DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
+       .map_io         = mx53_map_io,
+       .init_early     = imx53_init_early,
+       .init_irq       = mx53_init_irq,
+       .handle_irq     = imx53_handle_irq,
+       .timer          = &imx53_timer,
+       .init_machine   = imx53_dt_init,
+       .dt_compat      = imx53_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx51.c b/arch/arm/mach-imx/mach-cpuimx51.c
new file mode 100644 (file)
index 0000000..1fc1103
--- /dev/null
@@ -0,0 +1,300 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * based on board-mx51_babbage.c which is
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+
+#define CPUIMX51_USBH1_STP     IMX_GPIO_NR(1, 27)
+#define CPUIMX51_QUARTA_GPIO   IMX_GPIO_NR(3, 28)
+#define CPUIMX51_QUARTB_GPIO   IMX_GPIO_NR(3, 25)
+#define CPUIMX51_QUARTC_GPIO   IMX_GPIO_NR(3, 26)
+#define CPUIMX51_QUARTD_GPIO   IMX_GPIO_NR(3, 27)
+#define CPUIMX51_QUART_XTAL    14745600
+#define CPUIMX51_QUART_REGSHIFT        17
+
+/* USB_CTRL_1 */
+#define MX51_USB_CTRL_1_OFFSET         0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN   (1 << 25)
+
+#define        MX51_USB_PLLDIV_12_MHZ          0x00
+#define        MX51_USB_PLL_DIV_19_2_MHZ       0x01
+#define        MX51_USB_PLL_DIV_24_MHZ         0x02
+
+static struct plat_serial8250_port serial_platform_data[] = {
+       {
+               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
+               .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
+               .irqflags = IRQF_TRIGGER_HIGH,
+               .uartclk = CPUIMX51_QUART_XTAL,
+               .regshift = CPUIMX51_QUART_REGSHIFT,
+               .iotype = UPIO_MEM,
+               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+       }, {
+               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
+               .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
+               .irqflags = IRQF_TRIGGER_HIGH,
+               .uartclk = CPUIMX51_QUART_XTAL,
+               .regshift = CPUIMX51_QUART_REGSHIFT,
+               .iotype = UPIO_MEM,
+               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+       }, {
+               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
+               .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
+               .irqflags = IRQF_TRIGGER_HIGH,
+               .uartclk = CPUIMX51_QUART_XTAL,
+               .regshift = CPUIMX51_QUART_REGSHIFT,
+               .iotype = UPIO_MEM,
+               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+       }, {
+               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
+               .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
+               .irqflags = IRQF_TRIGGER_HIGH,
+               .uartclk = CPUIMX51_QUART_XTAL,
+               .regshift = CPUIMX51_QUART_REGSHIFT,
+               .iotype = UPIO_MEM,
+               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+       }, {
+       }
+};
+
+static struct platform_device serial_device = {
+       .name = "serial8250",
+       .id = 0,
+       .dev = {
+               .platform_data = serial_platform_data,
+       },
+};
+
+static struct platform_device *devices[] __initdata = {
+       &serial_device,
+};
+
+static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
+       /* UART1 */
+       MX51_PAD_UART1_RXD__UART1_RXD,
+       MX51_PAD_UART1_TXD__UART1_TXD,
+       MX51_PAD_UART1_RTS__UART1_RTS,
+       MX51_PAD_UART1_CTS__UART1_CTS,
+
+       /* I2C2 */
+       MX51_PAD_GPIO1_2__I2C2_SCL,
+       MX51_PAD_GPIO1_3__I2C2_SDA,
+       MX51_PAD_NANDF_D10__GPIO3_30,
+
+       /* QUART IRQ */
+       MX51_PAD_NANDF_D15__GPIO3_25,
+       MX51_PAD_NANDF_D14__GPIO3_26,
+       MX51_PAD_NANDF_D13__GPIO3_27,
+       MX51_PAD_NANDF_D12__GPIO3_28,
+
+       /* USB HOST1 */
+       MX51_PAD_USBH1_CLK__USBH1_CLK,
+       MX51_PAD_USBH1_DIR__USBH1_DIR,
+       MX51_PAD_USBH1_NXT__USBH1_NXT,
+       MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+       MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+       MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+       MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+       MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+       MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+       MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+       MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+       MX51_PAD_USBH1_STP__USBH1_STP,
+};
+
+static const struct mxc_nand_platform_data
+               eukrea_cpuimx51_nand_board_info __initconst = {
+       .width          = 1,
+       .hw_ecc         = 1,
+       .flash_bbt      = 1,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const
+struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
+       .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("pcf8563", 0x51),
+       },
+};
+
+/* This function is board specific as the bit mask for the plldiv will also
+be different for other Freescale SoCs, thus a common bitmask is not
+possible and cannot get place in /plat-mxc/ehci.c.*/
+static int initialize_otg_port(struct platform_device *pdev)
+{
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *usbother_base;
+
+       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
+       if (!usb_base)
+               return -ENOMEM;
+       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+       /* Set the PHY clock to 19.2MHz */
+       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+       v |= MX51_USB_PLL_DIV_19_2_MHZ;
+       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       iounmap(usb_base);
+
+       mdelay(10);
+
+       return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
+}
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *usbother_base;
+
+       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
+       if (!usb_base)
+               return -ENOMEM;
+       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+       /* The clock for the USBH1 ULPI port will come externally from the PHY. */
+       v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
+       __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
+       iounmap(usb_base);
+
+       mdelay(10);
+
+       return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                       MXC_EHCI_ITC_NO_THRESHOLD);
+}
+
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
+       .init           = initialize_otg_port,
+       .portsc = MXC_EHCI_UTMI_16BIT,
+};
+
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
+       .operating_mode = FSL_USB2_DR_DEVICE,
+       .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+};
+
+static const struct mxc_usbh_platform_data usbh1_config __initconst = {
+       .init           = initialize_usbh1_port,
+       .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx51_otg_mode(char *options)
+{
+       if (!strcmp(options, "host"))
+               otg_mode_host = 1;
+       else if (!strcmp(options, "device"))
+               otg_mode_host = 0;
+       else
+               pr_info("otg_mode neither \"host\" nor \"device\". "
+                       "Defaulting to device\n");
+       return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init eukrea_cpuimx51_init(void)
+{
+       imx51_soc_init();
+
+       mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
+                                       ARRAY_SIZE(eukrea_cpuimx51_pads));
+
+       imx51_add_imx_uart(0, &uart_pdata);
+       imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
+
+       gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
+       gpio_direction_input(CPUIMX51_QUARTA_GPIO);
+       gpio_free(CPUIMX51_QUARTA_GPIO);
+       gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
+       gpio_direction_input(CPUIMX51_QUARTB_GPIO);
+       gpio_free(CPUIMX51_QUARTB_GPIO);
+       gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
+       gpio_direction_input(CPUIMX51_QUARTC_GPIO);
+       gpio_free(CPUIMX51_QUARTC_GPIO);
+       gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
+       gpio_direction_input(CPUIMX51_QUARTD_GPIO);
+       gpio_free(CPUIMX51_QUARTD_GPIO);
+
+       imx51_add_fec(NULL);
+       platform_add_devices(devices, ARRAY_SIZE(devices));
+
+       imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
+       i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
+                               ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
+
+       if (otg_mode_host)
+               imx51_add_mxc_ehci_otg(&dr_utmi_config);
+       else {
+               initialize_otg_port(NULL);
+               imx51_add_fsl_usb2_udc(&usb_pdata);
+       }
+       imx51_add_mxc_ehci_hs(1, &usbh1_config);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
+       eukrea_mbimx51_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx51_timer_init(void)
+{
+       mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+       .init   = eukrea_cpuimx51_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
+       /* Maintainer: Eric Bénard <eric@eukrea.com> */
+       .atag_offset = 0x100,
+       .map_io = mx51_map_io,
+       .init_early = imx51_init_early,
+       .init_irq = mx51_init_irq,
+       .handle_irq = imx51_handle_irq,
+       .timer = &mxc_timer,
+       .init_machine = eukrea_cpuimx51_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
new file mode 100644 (file)
index 0000000..52a11c1
--- /dev/null
@@ -0,0 +1,338 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * based on board-mx51_babbage.c which is
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/i2c-gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/can/platform/mcp251x.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "cpu_op-mx51.h"
+
+#define USBH1_RST              IMX_GPIO_NR(2, 28)
+#define ETH_RST                        IMX_GPIO_NR(2, 31)
+#define TSC2007_IRQGPIO                IMX_GPIO_NR(3, 12)
+#define CAN_IRQGPIO            IMX_GPIO_NR(1, 1)
+#define CAN_RST                        IMX_GPIO_NR(4, 15)
+#define CAN_NCS                        IMX_GPIO_NR(4, 24)
+#define CAN_RXOBF              IMX_GPIO_NR(1, 4)
+#define CAN_RX1BF              IMX_GPIO_NR(1, 6)
+#define CAN_TXORTS             IMX_GPIO_NR(1, 7)
+#define CAN_TX1RTS             IMX_GPIO_NR(1, 8)
+#define CAN_TX2RTS             IMX_GPIO_NR(1, 9)
+#define I2C_SCL                        IMX_GPIO_NR(4, 16)
+#define I2C_SDA                        IMX_GPIO_NR(4, 17)
+
+/* USB_CTRL_1 */
+#define MX51_USB_CTRL_1_OFFSET         0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN   (1 << 25)
+
+#define        MX51_USB_PLLDIV_12_MHZ          0x00
+#define        MX51_USB_PLL_DIV_19_2_MHZ       0x01
+#define        MX51_USB_PLL_DIV_24_MHZ         0x02
+
+static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
+       /* UART1 */
+       MX51_PAD_UART1_RXD__UART1_RXD,
+       MX51_PAD_UART1_TXD__UART1_TXD,
+       MX51_PAD_UART1_RTS__UART1_RTS,
+       MX51_PAD_UART1_CTS__UART1_CTS,
+
+       /* USB HOST1 */
+       MX51_PAD_USBH1_CLK__USBH1_CLK,
+       MX51_PAD_USBH1_DIR__USBH1_DIR,
+       MX51_PAD_USBH1_NXT__USBH1_NXT,
+       MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+       MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+       MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+       MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+       MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+       MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+       MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+       MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+       MX51_PAD_USBH1_STP__USBH1_STP,
+       MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
+
+       /* FEC */
+       MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
+
+       /* HSI2C */
+       MX51_PAD_I2C1_CLK__GPIO4_16,
+       MX51_PAD_I2C1_DAT__GPIO4_17,
+
+       /* CAN */
+       MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+       MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+       MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+       MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
+       MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
+       MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
+       MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
+       MX51_PAD_GPIO1_6__GPIO1_6,
+       MX51_PAD_GPIO1_7__GPIO1_7,
+       MX51_PAD_GPIO1_8__GPIO1_8,
+       MX51_PAD_GPIO1_9__GPIO1_9,
+
+       /* Touchscreen */
+       /* IRQ */
+       NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
+                       PAD_CTL_PKE | PAD_CTL_SRE_FAST |
+                       PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct tsc2007_platform_data tsc2007_info = {
+       .model                  = 2007,
+       .x_plate_ohms           = 180,
+};
+
+static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("pcf8563", 0x51),
+       }, {
+               I2C_BOARD_INFO("tsc2007", 0x49),
+               .type           = "tsc2007",
+               .platform_data  = &tsc2007_info,
+               .irq            = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
+       },
+};
+
+static const struct mxc_nand_platform_data
+               eukrea_cpuimx51sd_nand_board_info __initconst = {
+       .width          = 1,
+       .hw_ecc         = 1,
+       .flash_bbt      = 1,
+};
+
+/* This function is board specific as the bit mask for the plldiv will also
+be different for other Freescale SoCs, thus a common bitmask is not
+possible and cannot get place in /plat-mxc/ehci.c.*/
+static int initialize_otg_port(struct platform_device *pdev)
+{
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *usbother_base;
+
+       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
+       if (!usb_base)
+               return -ENOMEM;
+       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+       /* Set the PHY clock to 19.2MHz */
+       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+       v |= MX51_USB_PLL_DIV_19_2_MHZ;
+       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       iounmap(usb_base);
+
+       mdelay(10);
+
+       return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
+}
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *usbother_base;
+
+       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
+       if (!usb_base)
+               return -ENOMEM;
+       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+       /* The clock for the USBH1 ULPI port will come from the PHY. */
+       v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
+       __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
+                       usbother_base + MX51_USB_CTRL_1_OFFSET);
+       iounmap(usb_base);
+
+       mdelay(10);
+
+       return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                       MXC_EHCI_ITC_NO_THRESHOLD);
+}
+
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
+       .init           = initialize_otg_port,
+       .portsc = MXC_EHCI_UTMI_16BIT,
+};
+
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
+       .operating_mode = FSL_USB2_DR_DEVICE,
+       .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+};
+
+static const struct mxc_usbh_platform_data usbh1_config __initconst = {
+       .init           = initialize_usbh1_port,
+       .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx51sd_otg_mode(char *options)
+{
+       if (!strcmp(options, "host"))
+               otg_mode_host = 1;
+       else if (!strcmp(options, "device"))
+               otg_mode_host = 0;
+       else
+               pr_info("otg_mode neither \"host\" nor \"device\". "
+                       "Defaulting to device\n");
+       return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
+
+static struct i2c_gpio_platform_data pdata = {
+       .sda_pin                = I2C_SDA,
+       .sda_is_open_drain      = 0,
+       .scl_pin                = I2C_SCL,
+       .scl_is_open_drain      = 0,
+       .udelay                 = 2,
+};
+
+static struct platform_device hsi2c_gpio_device = {
+       .name                   = "i2c-gpio",
+       .id                     = 0,
+       .dev.platform_data      = &pdata,
+};
+
+static struct mcp251x_platform_data mcp251x_info = {
+       .oscillator_frequency = 24E6,
+};
+
+static struct spi_board_info cpuimx51sd_spi_device[] = {
+       {
+               .modalias        = "mcp2515",
+               .max_speed_hz    = 10000000,
+               .bus_num         = 0,
+               .mode           = SPI_MODE_0,
+               .chip_select     = 0,
+               .platform_data   = &mcp251x_info,
+               .irq             = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
+       },
+};
+
+static int cpuimx51sd_spi1_cs[] = {
+       CAN_NCS,
+};
+
+static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
+       .chipselect     = cpuimx51sd_spi1_cs,
+       .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+       &hsi2c_gpio_device,
+};
+
+static void __init eukrea_cpuimx51sd_init(void)
+{
+       imx51_soc_init();
+
+       mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
+                                       ARRAY_SIZE(eukrea_cpuimx51sd_pads));
+
+#if defined(CONFIG_CPU_FREQ_IMX)
+       get_cpu_op = mx51_get_cpu_op;
+#endif
+
+       imx51_add_imx_uart(0, &uart_pdata);
+       imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
+
+       gpio_request(ETH_RST, "eth_rst");
+       gpio_set_value(ETH_RST, 1);
+       imx51_add_fec(NULL);
+
+       gpio_request(CAN_IRQGPIO, "can_irq");
+       gpio_direction_input(CAN_IRQGPIO);
+       gpio_free(CAN_IRQGPIO);
+       gpio_request(CAN_NCS, "can_ncs");
+       gpio_direction_output(CAN_NCS, 1);
+       gpio_free(CAN_NCS);
+       gpio_request(CAN_RST, "can_rst");
+       gpio_direction_output(CAN_RST, 0);
+       msleep(20);
+       gpio_set_value(CAN_RST, 1);
+       imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
+       spi_register_board_info(cpuimx51sd_spi_device,
+                               ARRAY_SIZE(cpuimx51sd_spi_device));
+
+       gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
+       gpio_direction_input(TSC2007_IRQGPIO);
+       gpio_free(TSC2007_IRQGPIO);
+
+       i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
+                       ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
+       platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+       if (otg_mode_host)
+               imx51_add_mxc_ehci_otg(&dr_utmi_config);
+       else {
+               initialize_otg_port(NULL);
+               imx51_add_fsl_usb2_udc(&usb_pdata);
+       }
+
+       gpio_request(USBH1_RST, "usb_rst");
+       gpio_direction_output(USBH1_RST, 0);
+       msleep(20);
+       gpio_set_value(USBH1_RST, 1);
+       imx51_add_mxc_ehci_hs(1, &usbh1_config);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
+       eukrea_mbimxsd51_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx51sd_timer_init(void)
+{
+       mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+       .init   = eukrea_cpuimx51sd_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
+       /* Maintainer: Eric Bénard <eric@eukrea.com> */
+       .atag_offset = 0x100,
+       .map_io = mx51_map_io,
+       .init_early = imx51_init_early,
+       .init_irq = mx51_init_irq,
+       .handle_irq = imx51_handle_irq,
+       .timer = &mxc_timer,
+       .init_machine = eukrea_cpuimx51sd_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c
new file mode 100644 (file)
index 0000000..fc3621d
--- /dev/null
@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx50.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx50.h"
+
+#define FEC_EN         IMX_GPIO_NR(6, 23)
+#define FEC_RESET_B    IMX_GPIO_NR(4, 12)
+
+static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
+       /* SD1 */
+       MX50_PAD_ECSPI2_SS0__GPIO_4_19,
+       MX50_PAD_EIM_CRE__GPIO_1_27,
+       MX50_PAD_SD1_CMD__SD1_CMD,
+
+       MX50_PAD_SD1_CLK__SD1_CLK,
+       MX50_PAD_SD1_D0__SD1_D0,
+       MX50_PAD_SD1_D1__SD1_D1,
+       MX50_PAD_SD1_D2__SD1_D2,
+       MX50_PAD_SD1_D3__SD1_D3,
+
+       /* SD2 */
+       MX50_PAD_SD2_CD__GPIO_5_17,
+       MX50_PAD_SD2_WP__GPIO_5_16,
+       MX50_PAD_SD2_CMD__SD2_CMD,
+       MX50_PAD_SD2_CLK__SD2_CLK,
+       MX50_PAD_SD2_D0__SD2_D0,
+       MX50_PAD_SD2_D1__SD2_D1,
+       MX50_PAD_SD2_D2__SD2_D2,
+       MX50_PAD_SD2_D3__SD2_D3,
+       MX50_PAD_SD2_D4__SD2_D4,
+       MX50_PAD_SD2_D5__SD2_D5,
+       MX50_PAD_SD2_D6__SD2_D6,
+       MX50_PAD_SD2_D7__SD2_D7,
+
+       /* SD3 */
+       MX50_PAD_SD3_CMD__SD3_CMD,
+       MX50_PAD_SD3_CLK__SD3_CLK,
+       MX50_PAD_SD3_D0__SD3_D0,
+       MX50_PAD_SD3_D1__SD3_D1,
+       MX50_PAD_SD3_D2__SD3_D2,
+       MX50_PAD_SD3_D3__SD3_D3,
+       MX50_PAD_SD3_D4__SD3_D4,
+       MX50_PAD_SD3_D5__SD3_D5,
+       MX50_PAD_SD3_D6__SD3_D6,
+       MX50_PAD_SD3_D7__SD3_D7,
+
+       /* PWR_INT */
+       MX50_PAD_ECSPI2_MISO__GPIO_4_18,
+
+       /* UART pad setting */
+       MX50_PAD_UART1_TXD__UART1_TXD,
+       MX50_PAD_UART1_RXD__UART1_RXD,
+       MX50_PAD_UART1_RTS__UART1_RTS,
+       MX50_PAD_UART2_TXD__UART2_TXD,
+       MX50_PAD_UART2_RXD__UART2_RXD,
+       MX50_PAD_UART2_CTS__UART2_CTS,
+       MX50_PAD_UART2_RTS__UART2_RTS,
+
+       MX50_PAD_I2C1_SCL__I2C1_SCL,
+       MX50_PAD_I2C1_SDA__I2C1_SDA,
+       MX50_PAD_I2C2_SCL__I2C2_SCL,
+       MX50_PAD_I2C2_SDA__I2C2_SDA,
+
+       MX50_PAD_EPITO__USBH1_PWR,
+       /* Need to comment below line if
+        * one needs to debug owire.
+        */
+       MX50_PAD_OWIRE__USBH1_OC,
+       /* using gpio to control otg pwr */
+       MX50_PAD_PWM2__GPIO_6_25,
+       MX50_PAD_I2C3_SCL__USBOTG_OC,
+
+       MX50_PAD_SSI_RXC__FEC_MDIO,
+       MX50_PAD_SSI_RXFS__FEC_MDC,
+       MX50_PAD_DISP_D0__FEC_TXCLK,
+       MX50_PAD_DISP_D1__FEC_RX_ER,
+       MX50_PAD_DISP_D2__FEC_RX_DV,
+       MX50_PAD_DISP_D3__FEC_RXD1,
+       MX50_PAD_DISP_D4__FEC_RXD0,
+       MX50_PAD_DISP_D5__FEC_TX_EN,
+       MX50_PAD_DISP_D6__FEC_TXD1,
+       MX50_PAD_DISP_D7__FEC_TXD0,
+       MX50_PAD_I2C3_SDA__GPIO_6_23,
+       MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
+
+       MX50_PAD_CSPI_SS0__CSPI_SS0,
+       MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
+       MX50_PAD_CSPI_MOSI__CSPI_MOSI,
+       MX50_PAD_CSPI_MISO__CSPI_MISO,
+
+       /* SGTL500_OSC_EN */
+       MX50_PAD_UART1_CTS__GPIO_6_8,
+
+       /* SGTL_AMP_SHDN */
+       MX50_PAD_UART3_RXD__GPIO_6_15,
+
+       /* Keypad */
+       MX50_PAD_KEY_COL0__KEY_COL0,
+       MX50_PAD_KEY_ROW0__KEY_ROW0,
+       MX50_PAD_KEY_COL1__KEY_COL1,
+       MX50_PAD_KEY_ROW1__KEY_ROW1,
+       MX50_PAD_KEY_COL2__KEY_COL2,
+       MX50_PAD_KEY_ROW2__KEY_ROW2,
+       MX50_PAD_KEY_COL3__KEY_COL3,
+       MX50_PAD_KEY_ROW3__KEY_ROW3,
+       MX50_PAD_EIM_DA0__KEY_COL4,
+       MX50_PAD_EIM_DA1__KEY_ROW4,
+       MX50_PAD_EIM_DA2__KEY_COL5,
+       MX50_PAD_EIM_DA3__KEY_ROW5,
+       MX50_PAD_EIM_DA4__KEY_COL6,
+       MX50_PAD_EIM_DA5__KEY_ROW6,
+       MX50_PAD_EIM_DA6__KEY_COL7,
+       MX50_PAD_EIM_DA7__KEY_ROW7,
+       /*EIM pads */
+       MX50_PAD_EIM_DA8__GPIO_1_8,
+       MX50_PAD_EIM_DA9__GPIO_1_9,
+       MX50_PAD_EIM_DA10__GPIO_1_10,
+       MX50_PAD_EIM_DA11__GPIO_1_11,
+       MX50_PAD_EIM_DA12__GPIO_1_12,
+       MX50_PAD_EIM_DA13__GPIO_1_13,
+       MX50_PAD_EIM_DA14__GPIO_1_14,
+       MX50_PAD_EIM_DA15__GPIO_1_15,
+       MX50_PAD_EIM_CS2__GPIO_1_16,
+       MX50_PAD_EIM_CS1__GPIO_1_17,
+       MX50_PAD_EIM_CS0__GPIO_1_18,
+       MX50_PAD_EIM_EB0__GPIO_1_19,
+       MX50_PAD_EIM_EB1__GPIO_1_20,
+       MX50_PAD_EIM_WAIT__GPIO_1_21,
+       MX50_PAD_EIM_BCLK__GPIO_1_22,
+       MX50_PAD_EIM_RDY__GPIO_1_23,
+       MX50_PAD_EIM_OE__GPIO_1_24,
+};
+
+/* Serial ports */
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct fec_platform_data fec_data __initconst = {
+       .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static inline void mx50_rdp_fec_reset(void)
+{
+       gpio_request(FEC_EN, "fec-en");
+       gpio_direction_output(FEC_EN, 0);
+       gpio_request(FEC_RESET_B, "fec-reset_b");
+       gpio_direction_output(FEC_RESET_B, 0);
+       msleep(1);
+       gpio_set_value(FEC_RESET_B, 1);
+}
+
+static const struct imxi2c_platform_data i2c_data __initconst = {
+       .bitrate = 100000,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init mx50_rdp_board_init(void)
+{
+       imx50_soc_init();
+
+       mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
+                                       ARRAY_SIZE(mx50_rdp_pads));
+
+       imx50_add_imx_uart(0, &uart_pdata);
+       imx50_add_imx_uart(1, &uart_pdata);
+       mx50_rdp_fec_reset();
+       imx50_add_fec(&fec_data);
+       imx50_add_imx_i2c(0, &i2c_data);
+       imx50_add_imx_i2c(1, &i2c_data);
+       imx50_add_imx_i2c(2, &i2c_data);
+}
+
+static void __init mx50_rdp_timer_init(void)
+{
+       mx50_clocks_init(32768, 24000000, 22579200);
+}
+
+static struct sys_timer mx50_rdp_timer = {
+       .init   = mx50_rdp_timer_init,
+};
+
+MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
+       .map_io = mx50_map_io,
+       .init_early = imx50_init_early,
+       .init_irq = mx50_init_irq,
+       .handle_irq = imx50_handle_irq,
+       .timer = &mx50_rdp_timer,
+       .init_machine = mx50_rdp_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
new file mode 100644 (file)
index 0000000..0578390
--- /dev/null
@@ -0,0 +1,178 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/3ds_debugboard.h>
+
+#include "devices-imx51.h"
+
+#define EXPIO_PARENT_INT       gpio_to_irq(IMX_GPIO_NR(1, 6))
+#define MX51_3DS_ECSPI2_CS     (GPIO_PORTC + 28)
+
+static iomux_v3_cfg_t mx51_3ds_pads[] = {
+       /* UART1 */
+       MX51_PAD_UART1_RXD__UART1_RXD,
+       MX51_PAD_UART1_TXD__UART1_TXD,
+       MX51_PAD_UART1_RTS__UART1_RTS,
+       MX51_PAD_UART1_CTS__UART1_CTS,
+
+       /* UART2 */
+       MX51_PAD_UART2_RXD__UART2_RXD,
+       MX51_PAD_UART2_TXD__UART2_TXD,
+       MX51_PAD_EIM_D25__UART2_CTS,
+       MX51_PAD_EIM_D26__UART2_RTS,
+
+       /* UART3 */
+       MX51_PAD_UART3_RXD__UART3_RXD,
+       MX51_PAD_UART3_TXD__UART3_TXD,
+       MX51_PAD_EIM_D24__UART3_CTS,
+       MX51_PAD_EIM_D27__UART3_RTS,
+
+       /* CPLD PARENT IRQ PIN */
+       MX51_PAD_GPIO1_6__GPIO1_6,
+
+       /* KPP */
+       MX51_PAD_KEY_ROW0__KEY_ROW0,
+       MX51_PAD_KEY_ROW1__KEY_ROW1,
+       MX51_PAD_KEY_ROW2__KEY_ROW2,
+       MX51_PAD_KEY_ROW3__KEY_ROW3,
+       MX51_PAD_KEY_COL0__KEY_COL0,
+       MX51_PAD_KEY_COL1__KEY_COL1,
+       MX51_PAD_KEY_COL2__KEY_COL2,
+       MX51_PAD_KEY_COL3__KEY_COL3,
+       MX51_PAD_KEY_COL4__KEY_COL4,
+       MX51_PAD_KEY_COL5__KEY_COL5,
+
+       /* eCSPI2 */
+       MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
+       MX51_PAD_NANDF_RB3__ECSPI2_MISO,
+       MX51_PAD_NANDF_D15__ECSPI2_MOSI,
+       MX51_PAD_NANDF_D12__GPIO3_28,
+};
+
+/* Serial ports */
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static int mx51_3ds_board_keymap[] = {
+       KEY(0, 0, KEY_1),
+       KEY(0, 1, KEY_2),
+       KEY(0, 2, KEY_3),
+       KEY(0, 3, KEY_F1),
+       KEY(0, 4, KEY_UP),
+       KEY(0, 5, KEY_F2),
+
+       KEY(1, 0, KEY_4),
+       KEY(1, 1, KEY_5),
+       KEY(1, 2, KEY_6),
+       KEY(1, 3, KEY_LEFT),
+       KEY(1, 4, KEY_SELECT),
+       KEY(1, 5, KEY_RIGHT),
+
+       KEY(2, 0, KEY_7),
+       KEY(2, 1, KEY_8),
+       KEY(2, 2, KEY_9),
+       KEY(2, 3, KEY_F3),
+       KEY(2, 4, KEY_DOWN),
+       KEY(2, 5, KEY_F4),
+
+       KEY(3, 0, KEY_0),
+       KEY(3, 1, KEY_OK),
+       KEY(3, 2, KEY_ESC),
+       KEY(3, 3, KEY_ENTER),
+       KEY(3, 4, KEY_MENU),
+       KEY(3, 5, KEY_BACK)
+};
+
+static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
+       .keymap         = mx51_3ds_board_keymap,
+       .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static int mx51_3ds_spi2_cs[] = {
+       MXC_SPI_CS(0),
+       MX51_3DS_ECSPI2_CS,
+};
+
+static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
+       .chipselect     = mx51_3ds_spi2_cs,
+       .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
+};
+
+static struct spi_board_info mx51_3ds_spi_nor_device[] = {
+       {
+        .modalias = "m25p80",
+        .max_speed_hz = 25000000,      /* max spi clock (SCK) speed in HZ */
+        .bus_num = 1,
+        .chip_select = 1,
+        .mode = SPI_MODE_0,
+        .platform_data = NULL,},
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init mx51_3ds_init(void)
+{
+       imx51_soc_init();
+
+       mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
+                                       ARRAY_SIZE(mx51_3ds_pads));
+
+       imx51_add_imx_uart(0, &uart_pdata);
+       imx51_add_imx_uart(1, &uart_pdata);
+       imx51_add_imx_uart(2, &uart_pdata);
+
+       imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
+       spi_register_board_info(mx51_3ds_spi_nor_device,
+                               ARRAY_SIZE(mx51_3ds_spi_nor_device));
+
+       if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+               printk(KERN_WARNING "Init of the debugboard failed, all "
+                                   "devices on the board are unusable.\n");
+
+       imx51_add_sdhci_esdhc_imx(0, NULL);
+       imx51_add_imx_keypad(&mx51_3ds_map_data);
+       imx51_add_imx2_wdt(0, NULL);
+}
+
+static void __init mx51_3ds_timer_init(void)
+{
+       mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mx51_3ds_timer = {
+       .init = mx51_3ds_timer_init,
+};
+
+MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
+       /* Maintainer: Freescale Semiconductor, Inc. */
+       .atag_offset = 0x100,
+       .map_io = mx51_map_io,
+       .init_early = imx51_init_early,
+       .init_irq = mx51_init_irq,
+       .handle_irq = imx51_handle_irq,
+       .timer = &mx51_3ds_timer,
+       .init_machine = mx51_3ds_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
new file mode 100644 (file)
index 0000000..5c83760
--- /dev/null
@@ -0,0 +1,429 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/input.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "cpu_op-mx51.h"
+
+#define BABBAGE_USB_HUB_RESET  IMX_GPIO_NR(1, 7)
+#define BABBAGE_USBH1_STP      IMX_GPIO_NR(1, 27)
+#define BABBAGE_USB_PHY_RESET  IMX_GPIO_NR(2, 5)
+#define BABBAGE_FEC_PHY_RESET  IMX_GPIO_NR(2, 14)
+#define BABBAGE_POWER_KEY      IMX_GPIO_NR(2, 21)
+#define BABBAGE_ECSPI1_CS0     IMX_GPIO_NR(4, 24)
+#define BABBAGE_ECSPI1_CS1     IMX_GPIO_NR(4, 25)
+#define BABBAGE_SD2_CD         IMX_GPIO_NR(1, 6)
+#define BABBAGE_SD2_WP         IMX_GPIO_NR(1, 5)
+
+/* USB_CTRL_1 */
+#define MX51_USB_CTRL_1_OFFSET                 0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN           (1 << 25)
+
+#define        MX51_USB_PLLDIV_12_MHZ          0x00
+#define        MX51_USB_PLL_DIV_19_2_MHZ       0x01
+#define        MX51_USB_PLL_DIV_24_MHZ 0x02
+
+static struct gpio_keys_button babbage_buttons[] = {
+       {
+               .gpio           = BABBAGE_POWER_KEY,
+               .code           = BTN_0,
+               .desc           = "PWR",
+               .active_low     = 1,
+               .wakeup         = 1,
+       },
+};
+
+static const struct gpio_keys_platform_data imx_button_data __initconst = {
+       .buttons        = babbage_buttons,
+       .nbuttons       = ARRAY_SIZE(babbage_buttons),
+};
+
+static iomux_v3_cfg_t mx51babbage_pads[] = {
+       /* UART1 */
+       MX51_PAD_UART1_RXD__UART1_RXD,
+       MX51_PAD_UART1_TXD__UART1_TXD,
+       MX51_PAD_UART1_RTS__UART1_RTS,
+       MX51_PAD_UART1_CTS__UART1_CTS,
+
+       /* UART2 */
+       MX51_PAD_UART2_RXD__UART2_RXD,
+       MX51_PAD_UART2_TXD__UART2_TXD,
+
+       /* UART3 */
+       MX51_PAD_EIM_D25__UART3_RXD,
+       MX51_PAD_EIM_D26__UART3_TXD,
+       MX51_PAD_EIM_D27__UART3_RTS,
+       MX51_PAD_EIM_D24__UART3_CTS,
+
+       /* I2C1 */
+       MX51_PAD_EIM_D16__I2C1_SDA,
+       MX51_PAD_EIM_D19__I2C1_SCL,
+
+       /* I2C2 */
+       MX51_PAD_KEY_COL4__I2C2_SCL,
+       MX51_PAD_KEY_COL5__I2C2_SDA,
+
+       /* HSI2C */
+       MX51_PAD_I2C1_CLK__I2C1_CLK,
+       MX51_PAD_I2C1_DAT__I2C1_DAT,
+
+       /* USB HOST1 */
+       MX51_PAD_USBH1_CLK__USBH1_CLK,
+       MX51_PAD_USBH1_DIR__USBH1_DIR,
+       MX51_PAD_USBH1_NXT__USBH1_NXT,
+       MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+       MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+       MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+       MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+       MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+       MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+       MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+       MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+
+       /* USB HUB reset line*/
+       MX51_PAD_GPIO1_7__GPIO1_7,
+
+       /* USB PHY reset line */
+       MX51_PAD_EIM_D21__GPIO2_5,
+
+       /* FEC */
+       MX51_PAD_EIM_EB2__FEC_MDIO,
+       MX51_PAD_EIM_EB3__FEC_RDATA1,
+       MX51_PAD_EIM_CS2__FEC_RDATA2,
+       MX51_PAD_EIM_CS3__FEC_RDATA3,
+       MX51_PAD_EIM_CS4__FEC_RX_ER,
+       MX51_PAD_EIM_CS5__FEC_CRS,
+       MX51_PAD_NANDF_RB2__FEC_COL,
+       MX51_PAD_NANDF_RB3__FEC_RX_CLK,
+       MX51_PAD_NANDF_D9__FEC_RDATA0,
+       MX51_PAD_NANDF_D8__FEC_TDATA0,
+       MX51_PAD_NANDF_CS2__FEC_TX_ER,
+       MX51_PAD_NANDF_CS3__FEC_MDC,
+       MX51_PAD_NANDF_CS4__FEC_TDATA1,
+       MX51_PAD_NANDF_CS5__FEC_TDATA2,
+       MX51_PAD_NANDF_CS6__FEC_TDATA3,
+       MX51_PAD_NANDF_CS7__FEC_TX_EN,
+       MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+
+       /* FEC PHY reset line */
+       MX51_PAD_EIM_A20__GPIO2_14,
+
+       /* SD 1 */
+       MX51_PAD_SD1_CMD__SD1_CMD,
+       MX51_PAD_SD1_CLK__SD1_CLK,
+       MX51_PAD_SD1_DATA0__SD1_DATA0,
+       MX51_PAD_SD1_DATA1__SD1_DATA1,
+       MX51_PAD_SD1_DATA2__SD1_DATA2,
+       MX51_PAD_SD1_DATA3__SD1_DATA3,
+       /* CD/WP from controller */
+       MX51_PAD_GPIO1_0__SD1_CD,
+       MX51_PAD_GPIO1_1__SD1_WP,
+
+       /* SD 2 */
+       MX51_PAD_SD2_CMD__SD2_CMD,
+       MX51_PAD_SD2_CLK__SD2_CLK,
+       MX51_PAD_SD2_DATA0__SD2_DATA0,
+       MX51_PAD_SD2_DATA1__SD2_DATA1,
+       MX51_PAD_SD2_DATA2__SD2_DATA2,
+       MX51_PAD_SD2_DATA3__SD2_DATA3,
+       /* CD/WP gpio */
+       MX51_PAD_GPIO1_6__GPIO1_6,
+       MX51_PAD_GPIO1_5__GPIO1_5,
+
+       /* eCSPI1 */
+       MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+       MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+       MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+       MX51_PAD_CSPI1_SS0__GPIO4_24,
+       MX51_PAD_CSPI1_SS1__GPIO4_25,
+};
+
+/* Serial ports */
+static const struct imxuart_platform_data uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
+       .bitrate = 100000,
+};
+
+static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
+       .bitrate = 400000,
+};
+
+static struct gpio mx51_babbage_usbh1_gpios[] = {
+       { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
+       { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
+};
+
+static int gpio_usbh1_active(void)
+{
+       iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
+       int ret;
+
+       /* Set USBH1_STP to GPIO and toggle it */
+       mxc_iomux_v3_setup_pad(usbh1stp_gpio);
+       ret = gpio_request_array(mx51_babbage_usbh1_gpios,
+                                       ARRAY_SIZE(mx51_babbage_usbh1_gpios));
+
+       if (ret) {
+               pr_debug("failed to get USBH1 pins: %d\n", ret);
+               return ret;
+       }
+
+       msleep(100);
+       gpio_set_value(BABBAGE_USBH1_STP, 1);
+       gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
+       gpio_free_array(mx51_babbage_usbh1_gpios,
+                                       ARRAY_SIZE(mx51_babbage_usbh1_gpios));
+       return 0;
+}
+
+static inline void babbage_usbhub_reset(void)
+{
+       int ret;
+
+       /* Reset USB hub */
+       ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
+                                       GPIOF_OUT_INIT_LOW, "GPIO1_7");
+       if (ret) {
+               printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
+               return;
+       }
+
+       msleep(2);
+       /* Deassert reset */
+       gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
+}
+
+static inline void babbage_fec_reset(void)
+{
+       int ret;
+
+       /* reset FEC PHY */
+       ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
+                                       GPIOF_OUT_INIT_LOW, "fec-phy-reset");
+       if (ret) {
+               printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+               return;
+       }
+       msleep(1);
+       gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
+}
+
+/* This function is board specific as the bit mask for the plldiv will also
+be different for other Freescale SoCs, thus a common bitmask is not
+possible and cannot get place in /plat-mxc/ehci.c.*/
+static int initialize_otg_port(struct platform_device *pdev)
+{
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *usbother_base;
+
+       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
+       if (!usb_base)
+               return -ENOMEM;
+       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+       /* Set the PHY clock to 19.2MHz */
+       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+       v |= MX51_USB_PLL_DIV_19_2_MHZ;
+       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       iounmap(usb_base);
+
+       mdelay(10);
+
+       return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
+}
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *usbother_base;
+
+       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
+       if (!usb_base)
+               return -ENOMEM;
+       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+       /* The clock for the USBH1 ULPI port will come externally from the PHY. */
+       v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
+       __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
+       iounmap(usb_base);
+
+       mdelay(10);
+
+       return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                       MXC_EHCI_ITC_NO_THRESHOLD);
+}
+
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
+       .init           = initialize_otg_port,
+       .portsc = MXC_EHCI_UTMI_16BIT,
+};
+
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
+       .operating_mode = FSL_USB2_DR_DEVICE,
+       .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+};
+
+static const struct mxc_usbh_platform_data usbh1_config __initconst = {
+       .init           = initialize_usbh1_port,
+       .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init babbage_otg_mode(char *options)
+{
+       if (!strcmp(options, "host"))
+               otg_mode_host = 1;
+       else if (!strcmp(options, "device"))
+               otg_mode_host = 0;
+       else
+               pr_info("otg_mode neither \"host\" nor \"device\". "
+                       "Defaulting to device\n");
+       return 0;
+}
+__setup("otg_mode=", babbage_otg_mode);
+
+static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
+       {
+               .modalias = "mtd_dataflash",
+               .max_speed_hz = 25000000,
+               .bus_num = 0,
+               .chip_select = 1,
+               .mode = SPI_MODE_0,
+               .platform_data = NULL,
+       },
+};
+
+static int mx51_babbage_spi_cs[] = {
+       BABBAGE_ECSPI1_CS0,
+       BABBAGE_ECSPI1_CS1,
+};
+
+static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
+       .chipselect     = mx51_babbage_spi_cs,
+       .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
+};
+
+static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
+       .cd_type = ESDHC_CD_CONTROLLER,
+       .wp_type = ESDHC_WP_CONTROLLER,
+};
+
+static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
+       .cd_gpio = BABBAGE_SD2_CD,
+       .wp_gpio = BABBAGE_SD2_WP,
+       .cd_type = ESDHC_CD_GPIO,
+       .wp_type = ESDHC_WP_GPIO,
+};
+
+void __init imx51_babbage_common_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
+                                        ARRAY_SIZE(mx51babbage_pads));
+}
+
+/*
+ * Board specific initialization.
+ */
+static void __init mx51_babbage_init(void)
+{
+       iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+       iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
+               PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
+
+       imx51_soc_init();
+
+#if defined(CONFIG_CPU_FREQ_IMX)
+       get_cpu_op = mx51_get_cpu_op;
+#endif
+       imx51_babbage_common_init();
+
+       imx51_add_imx_uart(0, &uart_pdata);
+       imx51_add_imx_uart(1, NULL);
+       imx51_add_imx_uart(2, &uart_pdata);
+
+       babbage_fec_reset();
+       imx51_add_fec(NULL);
+
+       /* Set the PAD settings for the pwr key. */
+       mxc_iomux_v3_setup_pad(power_key);
+       imx_add_gpio_keys(&imx_button_data);
+
+       imx51_add_imx_i2c(0, &babbage_i2c_data);
+       imx51_add_imx_i2c(1, &babbage_i2c_data);
+       imx51_add_hsi2c(&babbage_hsi2c_data);
+
+       if (otg_mode_host)
+               imx51_add_mxc_ehci_otg(&dr_utmi_config);
+       else {
+               initialize_otg_port(NULL);
+               imx51_add_fsl_usb2_udc(&usb_pdata);
+       }
+
+       gpio_usbh1_active();
+       imx51_add_mxc_ehci_hs(1, &usbh1_config);
+       /* setback USBH1_STP to be function */
+       mxc_iomux_v3_setup_pad(usbh1stp);
+       babbage_usbhub_reset();
+
+       imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
+       imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
+
+       spi_register_board_info(mx51_babbage_spi_board_info,
+               ARRAY_SIZE(mx51_babbage_spi_board_info));
+       imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
+       imx51_add_imx2_wdt(0, NULL);
+}
+
+static void __init mx51_babbage_timer_init(void)
+{
+       mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mx51_babbage_timer = {
+       .init = mx51_babbage_timer_init,
+};
+
+MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
+       /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
+       .atag_offset = 0x100,
+       .map_io = mx51_map_io,
+       .init_early = imx51_init_early,
+       .init_irq = mx51_init_irq,
+       .handle_irq = imx51_handle_irq,
+       .timer = &mx51_babbage_timer,
+       .init_machine = mx51_babbage_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
new file mode 100644 (file)
index 0000000..a9e4866
--- /dev/null
@@ -0,0 +1,295 @@
+/*
+ * Copyright (C) 2010 Linaro Limited
+ *
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "efika.h"
+
+#define EFIKAMX_PCBID0         IMX_GPIO_NR(3, 16)
+#define EFIKAMX_PCBID1         IMX_GPIO_NR(3, 17)
+#define EFIKAMX_PCBID2         IMX_GPIO_NR(3, 11)
+
+#define EFIKAMX_BLUE_LED       IMX_GPIO_NR(3, 13)
+#define EFIKAMX_GREEN_LED      IMX_GPIO_NR(3, 14)
+#define EFIKAMX_RED_LED                IMX_GPIO_NR(3, 15)
+
+#define EFIKAMX_POWER_KEY      IMX_GPIO_NR(2, 31)
+
+/* board 1.1 doesn't have same reset gpio */
+#define EFIKAMX_RESET1_1       IMX_GPIO_NR(3, 2)
+#define EFIKAMX_RESET          IMX_GPIO_NR(1, 4)
+
+#define EFIKAMX_POWEROFF       IMX_GPIO_NR(4, 13)
+
+#define EFIKAMX_PMIC           IMX_GPIO_NR(1, 6)
+
+/* the pci ids pin have pull up. they're driven low according to board id */
+#define MX51_PAD_PCBID0        IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_PCBID1        IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_PCBID2        IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_PWRKEY        IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
+
+static iomux_v3_cfg_t mx51efikamx_pads[] = {
+       /* board id */
+       MX51_PAD_PCBID0,
+       MX51_PAD_PCBID1,
+       MX51_PAD_PCBID2,
+
+       /* leds */
+       MX51_PAD_CSI1_D9__GPIO3_13,
+       MX51_PAD_CSI1_VSYNC__GPIO3_14,
+       MX51_PAD_CSI1_HSYNC__GPIO3_15,
+
+       /* power key */
+       MX51_PAD_PWRKEY,
+
+       /* reset */
+       MX51_PAD_DI1_PIN13__GPIO3_2,
+       MX51_PAD_GPIO1_4__GPIO1_4,
+
+       /* power off */
+       MX51_PAD_CSI2_VSYNC__GPIO4_13,
+};
+
+/*   PCBID2  PCBID1 PCBID0  STATE
+       1       1      1    ER1:rev1.1
+       1       1      0    ER2:rev1.2
+       1       0      1    ER3:rev1.3
+       1       0      0    ER4:rev1.4
+*/
+static void __init mx51_efikamx_board_id(void)
+{
+       int id;
+
+       /* things are taking time to settle */
+       msleep(150);
+
+       gpio_request(EFIKAMX_PCBID0, "pcbid0");
+       gpio_direction_input(EFIKAMX_PCBID0);
+       gpio_request(EFIKAMX_PCBID1, "pcbid1");
+       gpio_direction_input(EFIKAMX_PCBID1);
+       gpio_request(EFIKAMX_PCBID2, "pcbid2");
+       gpio_direction_input(EFIKAMX_PCBID2);
+
+       id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
+       id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
+       id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
+
+       switch (id) {
+       case 7:
+               system_rev = 0x11;
+               break;
+       case 6:
+               system_rev = 0x12;
+               break;
+       case 5:
+               system_rev = 0x13;
+               break;
+       case 4:
+               system_rev = 0x14;
+               break;
+       default:
+               system_rev = 0x10;
+               break;
+       }
+
+       if ((system_rev == 0x10)
+               || (system_rev == 0x12)
+               || (system_rev == 0x14)) {
+               printk(KERN_WARNING
+                       "EfikaMX: Unsupported board revision 1.%u!\n",
+                       system_rev & 0xf);
+       }
+}
+
+static struct gpio_led mx51_efikamx_leds[] __initdata = {
+       {
+               .name = "efikamx:green",
+               .default_trigger = "default-on",
+               .gpio = EFIKAMX_GREEN_LED,
+       },
+       {
+               .name = "efikamx:red",
+               .default_trigger = "ide-disk",
+               .gpio = EFIKAMX_RED_LED,
+       },
+       {
+               .name = "efikamx:blue",
+               .default_trigger = "mmc0",
+               .gpio = EFIKAMX_BLUE_LED,
+       },
+};
+
+static const struct gpio_led_platform_data
+               mx51_efikamx_leds_data __initconst = {
+       .leds = mx51_efikamx_leds,
+       .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
+};
+
+static struct esdhc_platform_data sd_pdata = {
+       .cd_type = ESDHC_CD_CONTROLLER,
+       .wp_type = ESDHC_WP_CONTROLLER,
+};
+
+static struct gpio_keys_button mx51_efikamx_powerkey[] = {
+       {
+               .code = KEY_POWER,
+               .gpio = EFIKAMX_POWER_KEY,
+               .type = EV_PWR,
+               .desc = "Power Button (CM)",
+               .wakeup = 1,
+               .debounce_interval = 10, /* ms */
+       },
+};
+
+static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
+       .buttons = mx51_efikamx_powerkey,
+       .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
+};
+
+void mx51_efikamx_reset(void)
+{
+       if (system_rev == 0x11)
+               gpio_direction_output(EFIKAMX_RESET1_1, 0);
+       else
+               gpio_direction_output(EFIKAMX_RESET, 0);
+}
+
+static struct regulator *pwgt1, *pwgt2, *coincell;
+
+static void mx51_efikamx_power_off(void)
+{
+       if (!IS_ERR(coincell))
+               regulator_disable(coincell);
+
+       if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+               regulator_disable(pwgt2);
+               regulator_disable(pwgt1);
+       }
+       gpio_direction_output(EFIKAMX_POWEROFF, 1);
+}
+
+static int __init mx51_efikamx_power_init(void)
+{
+       if (machine_is_mx51_efikamx()) {
+               pwgt1 = regulator_get(NULL, "pwgt1");
+               pwgt2 = regulator_get(NULL, "pwgt2");
+               if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                       regulator_enable(pwgt1);
+                       regulator_enable(pwgt2);
+               }
+               gpio_request(EFIKAMX_POWEROFF, "poweroff");
+               pm_power_off = mx51_efikamx_power_off;
+
+               /* enable coincell charger. maybe need a small power driver ? */
+               coincell = regulator_get(NULL, "coincell");
+               if (!IS_ERR(coincell)) {
+                       regulator_set_voltage(coincell, 3000000, 3000000);
+                       regulator_enable(coincell);
+               }
+
+               regulator_has_full_constraints();
+       }
+
+       return 0;
+}
+late_initcall(mx51_efikamx_power_init);
+
+static void __init mx51_efikamx_init(void)
+{
+       imx51_soc_init();
+
+       mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
+                                       ARRAY_SIZE(mx51efikamx_pads));
+       efika_board_common_init();
+
+       mx51_efikamx_board_id();
+
+       /* on < 1.2 boards both SD controllers are used */
+       if (system_rev < 0x12) {
+               imx51_add_sdhci_esdhc_imx(0, NULL);
+               imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
+               mx51_efikamx_leds[2].default_trigger = "mmc1";
+       } else
+               imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
+
+       gpio_led_register_device(-1, &mx51_efikamx_leds_data);
+       imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
+
+       if (system_rev == 0x11) {
+               gpio_request(EFIKAMX_RESET1_1, "reset");
+               gpio_direction_output(EFIKAMX_RESET1_1, 1);
+       } else {
+               gpio_request(EFIKAMX_RESET, "reset");
+               gpio_direction_output(EFIKAMX_RESET, 1);
+       }
+
+       /*
+        * enable wifi by default only on mx
+        * sb and mx have same wlan pin but the value to enable it are
+        * different :/
+        */
+       gpio_request(EFIKA_WLAN_EN, "wlan_en");
+       gpio_direction_output(EFIKA_WLAN_EN, 0);
+       msleep(10);
+
+       gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
+       gpio_direction_output(EFIKA_WLAN_RESET, 0);
+       msleep(10);
+       gpio_set_value(EFIKA_WLAN_RESET, 1);
+}
+
+static void __init mx51_efikamx_timer_init(void)
+{
+       mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+}
+
+static struct sys_timer mx51_efikamx_timer = {
+       .init = mx51_efikamx_timer_init,
+};
+
+MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
+       /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
+       .atag_offset = 0x100,
+       .map_io = mx51_map_io,
+       .init_early = imx51_init_early,
+       .init_irq = mx51_init_irq,
+       .handle_irq = imx51_handle_irq,
+       .timer = &mx51_efikamx_timer,
+       .init_machine = mx51_efikamx_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
new file mode 100644 (file)
index 0000000..38c4a3e
--- /dev/null
@@ -0,0 +1,290 @@
+/*
+ * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <mach/ulpi.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "efika.h"
+
+#define EFIKASB_USBH2_STP      IMX_GPIO_NR(2, 20)
+#define EFIKASB_GREEN_LED      IMX_GPIO_NR(1, 3)
+#define EFIKASB_WHITE_LED      IMX_GPIO_NR(2, 25)
+#define EFIKASB_PCBID0         IMX_GPIO_NR(2, 28)
+#define EFIKASB_PCBID1         IMX_GPIO_NR(2, 29)
+#define EFIKASB_PWRKEY         IMX_GPIO_NR(2, 31)
+#define EFIKASB_LID            IMX_GPIO_NR(3, 14)
+#define EFIKASB_POWEROFF       IMX_GPIO_NR(4, 13)
+#define EFIKASB_RFKILL         IMX_GPIO_NR(3, 1)
+
+#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
+#define MX51_PAD_SD1_CD        IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+
+static iomux_v3_cfg_t mx51efikasb_pads[] = {
+       /* USB HOST2 */
+       MX51_PAD_EIM_D16__USBH2_DATA0,
+       MX51_PAD_EIM_D17__USBH2_DATA1,
+       MX51_PAD_EIM_D18__USBH2_DATA2,
+       MX51_PAD_EIM_D19__USBH2_DATA3,
+       MX51_PAD_EIM_D20__USBH2_DATA4,
+       MX51_PAD_EIM_D21__USBH2_DATA5,
+       MX51_PAD_EIM_D22__USBH2_DATA6,
+       MX51_PAD_EIM_D23__USBH2_DATA7,
+       MX51_PAD_EIM_A24__USBH2_CLK,
+       MX51_PAD_EIM_A25__USBH2_DIR,
+       MX51_PAD_EIM_A26__USBH2_STP,
+       MX51_PAD_EIM_A27__USBH2_NXT,
+
+       /* leds */
+       MX51_PAD_EIM_CS0__GPIO2_25,
+       MX51_PAD_GPIO1_3__GPIO1_3,
+
+       /* pcb id */
+       MX51_PAD_EIM_CS3__GPIO2_28,
+       MX51_PAD_EIM_CS4__GPIO2_29,
+
+       /* lid */
+       MX51_PAD_CSI1_VSYNC__GPIO3_14,
+
+       /* power key*/
+       MX51_PAD_PWRKEY,
+
+       /* wifi/bt button */
+       MX51_PAD_DI1_PIN12__GPIO3_1,
+
+       /* power off */
+       MX51_PAD_CSI2_VSYNC__GPIO4_13,
+
+       /* wdog reset */
+       MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
+
+       /* BT */
+       MX51_PAD_EIM_A17__GPIO2_11,
+
+       MX51_PAD_SD1_CD,
+};
+
+static int initialize_usbh2_port(struct platform_device *pdev)
+{
+       iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
+       iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
+
+       mxc_iomux_v3_setup_pad(usbh2gpio);
+       gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
+       gpio_direction_output(EFIKASB_USBH2_STP, 0);
+       msleep(1);
+       gpio_set_value(EFIKASB_USBH2_STP, 1);
+       msleep(1);
+
+       gpio_free(EFIKASB_USBH2_STP);
+       mxc_iomux_v3_setup_pad(usbh2stp);
+
+       mdelay(10);
+
+       return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
+}
+
+static struct mxc_usbh_platform_data usbh2_config __initdata = {
+       .init   = initialize_usbh2_port,
+       .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static void __init mx51_efikasb_usb(void)
+{
+       usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                       ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
+       if (usbh2_config.otg)
+               imx51_add_mxc_ehci_hs(2, &usbh2_config);
+}
+
+static const struct gpio_led mx51_efikasb_leds[] __initconst = {
+       {
+               .name = "efikasb:green",
+               .default_trigger = "default-on",
+               .gpio = EFIKASB_GREEN_LED,
+               .active_low = 1,
+       },
+       {
+               .name = "efikasb:white",
+               .default_trigger = "caps",
+               .gpio = EFIKASB_WHITE_LED,
+       },
+};
+
+static const struct gpio_led_platform_data
+               mx51_efikasb_leds_data __initconst = {
+       .leds = mx51_efikasb_leds,
+       .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
+};
+
+static struct gpio_keys_button mx51_efikasb_keys[] = {
+       {
+               .code = KEY_POWER,
+               .gpio = EFIKASB_PWRKEY,
+               .type = EV_KEY,
+               .desc = "Power Button",
+               .wakeup = 1,
+               .active_low = 1,
+       },
+       {
+               .code = SW_LID,
+               .gpio = EFIKASB_LID,
+               .type = EV_SW,
+               .desc = "Lid Switch",
+               .active_low = 1,
+       },
+       {
+               .code = KEY_RFKILL,
+               .gpio = EFIKASB_RFKILL,
+               .type = EV_KEY,
+               .desc = "rfkill",
+               .active_low = 1,
+       },
+};
+
+static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
+       .buttons = mx51_efikasb_keys,
+       .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
+};
+
+static struct esdhc_platform_data sd0_pdata = {
+#define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27)
+       .cd_gpio = EFIKASB_SD1_CD,
+       .cd_type = ESDHC_CD_GPIO,
+       .wp_type = ESDHC_WP_CONTROLLER,
+};
+
+static struct esdhc_platform_data sd1_pdata = {
+       .cd_type = ESDHC_CD_CONTROLLER,
+       .wp_type = ESDHC_WP_CONTROLLER,
+};
+
+static struct regulator *pwgt1, *pwgt2;
+
+static void mx51_efikasb_power_off(void)
+{
+       gpio_set_value(EFIKA_USB_PHY_RESET, 0);
+
+       if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+               regulator_disable(pwgt2);
+               regulator_disable(pwgt1);
+       }
+       gpio_direction_output(EFIKASB_POWEROFF, 1);
+}
+
+static int __init mx51_efikasb_power_init(void)
+{
+       if (machine_is_mx51_efikasb()) {
+               pwgt1 = regulator_get(NULL, "pwgt1");
+               pwgt2 = regulator_get(NULL, "pwgt2");
+               if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                       regulator_enable(pwgt1);
+                       regulator_enable(pwgt2);
+               }
+               gpio_request(EFIKASB_POWEROFF, "poweroff");
+               pm_power_off = mx51_efikasb_power_off;
+
+               regulator_has_full_constraints();
+       }
+
+       return 0;
+}
+late_initcall(mx51_efikasb_power_init);
+
+/* 01     R1.3 board
+   10     R2.0 board */
+static void __init mx51_efikasb_board_id(void)
+{
+       int id;
+
+       gpio_request(EFIKASB_PCBID0, "pcb id0");
+       gpio_direction_input(EFIKASB_PCBID0);
+       gpio_request(EFIKASB_PCBID1, "pcb id1");
+       gpio_direction_input(EFIKASB_PCBID1);
+
+       id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
+       id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
+
+       switch (id) {
+       default:
+               break;
+       case 1:
+               system_rev = 0x13;
+               break;
+       case 2:
+               system_rev = 0x20;
+               break;
+       }
+}
+
+static void __init efikasb_board_init(void)
+{
+       imx51_soc_init();
+
+       mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
+                                       ARRAY_SIZE(mx51efikasb_pads));
+       efika_board_common_init();
+
+       mx51_efikasb_board_id();
+       mx51_efikasb_usb();
+       imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
+       imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
+
+       gpio_led_register_device(-1, &mx51_efikasb_leds_data);
+       imx_add_gpio_keys(&mx51_efikasb_keys_data);
+}
+
+static void __init mx51_efikasb_timer_init(void)
+{
+       mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+}
+
+static struct sys_timer mx51_efikasb_timer = {
+       .init   = mx51_efikasb_timer_init,
+};
+
+MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
+       .atag_offset = 0x100,
+       .map_io = mx51_map_io,
+       .init_early = imx51_init_early,
+       .init_irq = mx51_init_irq,
+       .handle_irq = imx51_handle_irq,
+       .init_machine =  efikasb_board_init,
+       .timer = &mx51_efikasb_timer,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
new file mode 100644 (file)
index 0000000..b88a2bc
--- /dev/null
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx53.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx53.h"
+
+#define ARD_ETHERNET_INT_B     IMX_GPIO_NR(2, 31)
+#define ARD_SD1_CD             IMX_GPIO_NR(1, 1)
+#define ARD_SD1_WP             IMX_GPIO_NR(1, 9)
+#define ARD_I2CPORTEXP_B       IMX_GPIO_NR(2, 3)
+#define ARD_VOLUMEDOWN         IMX_GPIO_NR(4, 0)
+#define ARD_HOME                       IMX_GPIO_NR(5, 10)
+#define ARD_BACK                       IMX_GPIO_NR(5, 11)
+#define ARD_PROG                       IMX_GPIO_NR(5, 12)
+#define ARD_VOLUMEUP           IMX_GPIO_NR(5, 13)
+
+static iomux_v3_cfg_t mx53_ard_pads[] = {
+       /* UART1 */
+       MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
+       MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
+       /* WEIM for CS1 */
+       MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
+       MX53_PAD_EIM_D16__EMI_WEIM_D_16,
+       MX53_PAD_EIM_D17__EMI_WEIM_D_17,
+       MX53_PAD_EIM_D18__EMI_WEIM_D_18,
+       MX53_PAD_EIM_D19__EMI_WEIM_D_19,
+       MX53_PAD_EIM_D20__EMI_WEIM_D_20,
+       MX53_PAD_EIM_D21__EMI_WEIM_D_21,
+       MX53_PAD_EIM_D22__EMI_WEIM_D_22,
+       MX53_PAD_EIM_D23__EMI_WEIM_D_23,
+       MX53_PAD_EIM_D24__EMI_WEIM_D_24,
+       MX53_PAD_EIM_D25__EMI_WEIM_D_25,
+       MX53_PAD_EIM_D26__EMI_WEIM_D_26,
+       MX53_PAD_EIM_D27__EMI_WEIM_D_27,
+       MX53_PAD_EIM_D28__EMI_WEIM_D_28,
+       MX53_PAD_EIM_D29__EMI_WEIM_D_29,
+       MX53_PAD_EIM_D30__EMI_WEIM_D_30,
+       MX53_PAD_EIM_D31__EMI_WEIM_D_31,
+       MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+       MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+       MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+       MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+       MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+       MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+       MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+       MX53_PAD_EIM_OE__EMI_WEIM_OE,
+       MX53_PAD_EIM_RW__EMI_WEIM_RW,
+       MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
+       /* SDHC1 */
+       MX53_PAD_SD1_CMD__ESDHC1_CMD,
+       MX53_PAD_SD1_CLK__ESDHC1_CLK,
+       MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+       MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+       MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+       MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+       MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
+       MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
+       MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
+       MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
+       MX53_PAD_GPIO_1__GPIO1_1,
+       MX53_PAD_GPIO_9__GPIO1_9,
+       /* I2C2 */
+       MX53_PAD_EIM_EB2__I2C2_SCL,
+       MX53_PAD_KEY_ROW3__I2C2_SDA,
+       /* I2C3 */
+       MX53_PAD_GPIO_3__I2C3_SCL,
+       MX53_PAD_GPIO_16__I2C3_SDA,
+       /* GPIO */
+       MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
+       MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
+       MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
+       MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
+       MX53_PAD_GPIO_10__GPIO4_0,              /* vol down */
+};
+
+#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)   \
+{                                                      \
+       .gpio           = gpio_num,                             \
+       .type           = EV_KEY,                               \
+       .code           = ev_code,                              \
+       .active_low     = act_low,                              \
+       .desc           = "btn " descr,                 \
+       .wakeup         = wake,                                 \
+}
+
+static struct gpio_keys_button ard_buttons[] = {
+       GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
+       GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
+       GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
+       GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
+       GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
+};
+
+static const struct gpio_keys_platform_data ard_button_data __initconst = {
+       .buttons        = ard_buttons,
+       .nbuttons       = ARRAY_SIZE(ard_buttons),
+};
+
+static struct resource ard_smsc911x_resources[] = {
+       {
+               .start = MX53_CS1_64MB_BASE_ADDR,
+               .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
+               .end =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+struct smsc911x_platform_config ard_smsc911x_config = {
+       .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+       .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+       .flags = SMSC911X_USE_32BIT,
+};
+
+static struct platform_device ard_smsc_lan9220_device = {
+       .name = "smsc911x",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
+       .resource = ard_smsc911x_resources,
+       .dev = {
+               .platform_data = &ard_smsc911x_config,
+       },
+};
+
+static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
+       .cd_gpio = ARD_SD1_CD,
+       .wp_gpio = ARD_SD1_WP,
+};
+
+static struct imxi2c_platform_data mx53_ard_i2c2_data = {
+       .bitrate = 50000,
+};
+
+static struct imxi2c_platform_data mx53_ard_i2c3_data = {
+       .bitrate = 400000,
+};
+
+static void __init mx53_ard_io_init(void)
+{
+       gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
+       gpio_direction_input(ARD_ETHERNET_INT_B);
+
+       gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
+       gpio_direction_output(ARD_I2CPORTEXP_B, 1);
+}
+
+/* Config CS1 settings for ethernet controller */
+static int weim_cs_config(void)
+{
+       u32 reg;
+       void __iomem *weim_base, *iomuxc_base;
+
+       weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
+       if (!weim_base)
+               return -ENOMEM;
+
+       iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
+       if (!iomuxc_base)
+               return -ENOMEM;
+
+       /* CS1 timings for LAN9220 */
+       writel(0x20001, (weim_base + 0x18));
+       writel(0x0, (weim_base + 0x1C));
+       writel(0x16000202, (weim_base + 0x20));
+       writel(0x00000002, (weim_base + 0x24));
+       writel(0x16002082, (weim_base + 0x28));
+       writel(0x00000000, (weim_base + 0x2C));
+       writel(0x00000000, (weim_base + 0x90));
+
+       /* specify 64 MB on CS1 and CS0 on GPR1 */
+       reg = readl(iomuxc_base + 0x4);
+       reg &= ~0x3F;
+       reg |= 0x1B;
+       writel(reg, (iomuxc_base + 0x4));
+
+       iounmap(iomuxc_base);
+       iounmap(weim_base);
+
+       return 0;
+}
+
+void __init imx53_ard_common_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
+                                        ARRAY_SIZE(mx53_ard_pads));
+       weim_cs_config();
+}
+
+static struct platform_device *devices[] __initdata = {
+       &ard_smsc_lan9220_device,
+};
+
+static void __init mx53_ard_board_init(void)
+{
+       imx53_soc_init();
+       imx53_add_imx_uart(0, NULL);
+
+       imx53_ard_common_init();
+       mx53_ard_io_init();
+       platform_add_devices(devices, ARRAY_SIZE(devices));
+
+       imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
+       imx53_add_imx2_wdt(0, NULL);
+       imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
+       imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
+       imx_add_gpio_keys(&ard_button_data);
+       imx53_add_ahci_imx();
+}
+
+static void __init mx53_ard_timer_init(void)
+{
+       mx53_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mx53_ard_timer = {
+       .init   = mx53_ard_timer_init,
+};
+
+MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
+       .map_io = mx53_map_io,
+       .init_early = imx53_init_early,
+       .init_irq = mx53_init_irq,
+       .handle_irq = imx53_handle_irq,
+       .timer = &mx53_ard_timer,
+       .init_machine = mx53_ard_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
new file mode 100644 (file)
index 0000000..c69413d
--- /dev/null
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/iomux-mx53.h>
+
+#define MX53_EVK_FEC_PHY_RST   IMX_GPIO_NR(7, 6)
+#define EVK_ECSPI1_CS0         IMX_GPIO_NR(2, 30)
+#define EVK_ECSPI1_CS1         IMX_GPIO_NR(3, 19)
+#define MX53EVK_LED            IMX_GPIO_NR(7, 7)
+
+#include "devices-imx53.h"
+
+static iomux_v3_cfg_t mx53_evk_pads[] = {
+       MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+       MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+
+       MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+       MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+       MX53_PAD_PATA_DIOR__UART2_RTS,
+       MX53_PAD_PATA_INTRQ__UART2_CTS,
+
+       MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
+       MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
+
+       MX53_PAD_EIM_D16__ECSPI1_SCLK,
+       MX53_PAD_EIM_D17__ECSPI1_MISO,
+       MX53_PAD_EIM_D18__ECSPI1_MOSI,
+
+       /* ecspi chip select lines */
+       MX53_PAD_EIM_EB2__GPIO2_30,
+       MX53_PAD_EIM_D19__GPIO3_19,
+       /* LED */
+       MX53_PAD_PATA_DA_1__GPIO7_7,
+};
+
+static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct gpio_led mx53evk_leds[] __initconst = {
+       {
+               .name                   = "green",
+               .default_trigger        = "heartbeat",
+               .gpio                   = MX53EVK_LED,
+       },
+};
+
+static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
+       .leds           = mx53evk_leds,
+       .num_leds       = ARRAY_SIZE(mx53evk_leds),
+};
+
+static inline void mx53_evk_init_uart(void)
+{
+       imx53_add_imx_uart(0, NULL);
+       imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
+       imx53_add_imx_uart(2, NULL);
+}
+
+static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
+       .bitrate = 100000,
+};
+
+static inline void mx53_evk_fec_reset(void)
+{
+       int ret;
+
+       /* reset FEC PHY */
+       ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
+                                                       "fec-phy-reset");
+       if (ret) {
+               printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+               return;
+       }
+       msleep(1);
+       gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
+}
+
+static struct fec_platform_data mx53_evk_fec_pdata = {
+       .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
+       {
+               .modalias = "mtd_dataflash",
+               .max_speed_hz = 25000000,
+               .bus_num = 0,
+               .chip_select = 1,
+               .mode = SPI_MODE_0,
+               .platform_data = NULL,
+       },
+};
+
+static int mx53_evk_spi_cs[] = {
+       EVK_ECSPI1_CS0,
+       EVK_ECSPI1_CS1,
+};
+
+static const struct spi_imx_master mx53_evk_spi_data __initconst = {
+       .chipselect     = mx53_evk_spi_cs,
+       .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
+};
+
+void __init imx53_evk_common_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
+                                        ARRAY_SIZE(mx53_evk_pads));
+}
+
+static void __init mx53_evk_board_init(void)
+{
+       imx53_soc_init();
+       imx53_evk_common_init();
+
+       mx53_evk_init_uart();
+       mx53_evk_fec_reset();
+       imx53_add_fec(&mx53_evk_fec_pdata);
+
+       imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
+       imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
+
+       imx53_add_sdhci_esdhc_imx(0, NULL);
+       imx53_add_sdhci_esdhc_imx(1, NULL);
+
+       spi_register_board_info(mx53_evk_spi_board_info,
+               ARRAY_SIZE(mx53_evk_spi_board_info));
+       imx53_add_ecspi(0, &mx53_evk_spi_data);
+       imx53_add_imx2_wdt(0, NULL);
+       gpio_led_register_device(-1, &mx53evk_leds_data);
+}
+
+static void __init mx53_evk_timer_init(void)
+{
+       mx53_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mx53_evk_timer = {
+       .init   = mx53_evk_timer_init,
+};
+
+MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
+       .map_io = mx53_map_io,
+       .init_early = imx53_init_early,
+       .init_irq = mx53_init_irq,
+       .handle_irq = imx53_handle_irq,
+       .timer = &mx53_evk_timer,
+       .init_machine = mx53_evk_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
new file mode 100644 (file)
index 0000000..e64a8f7
--- /dev/null
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx53.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx53.h"
+
+#define MX53_LOCO_POWER                        IMX_GPIO_NR(1, 8)
+#define MX53_LOCO_UI1                  IMX_GPIO_NR(2, 14)
+#define MX53_LOCO_UI2                  IMX_GPIO_NR(2, 15)
+#define LOCO_FEC_PHY_RST               IMX_GPIO_NR(7, 6)
+#define LOCO_LED                       IMX_GPIO_NR(7, 7)
+#define LOCO_SD3_CD                    IMX_GPIO_NR(3, 11)
+#define LOCO_SD3_WP                    IMX_GPIO_NR(3, 12)
+#define LOCO_SD1_CD                    IMX_GPIO_NR(3, 13)
+#define LOCO_ACCEL_EN                  IMX_GPIO_NR(6, 14)
+
+static iomux_v3_cfg_t mx53_loco_pads[] = {
+       /* FEC */
+       MX53_PAD_FEC_MDC__FEC_MDC,
+       MX53_PAD_FEC_MDIO__FEC_MDIO,
+       MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+       MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+       MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+       MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+       MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+       MX53_PAD_FEC_TX_EN__FEC_TX_EN,
+       MX53_PAD_FEC_TXD1__FEC_TDATA_1,
+       MX53_PAD_FEC_TXD0__FEC_TDATA_0,
+       /* FEC_nRST */
+       MX53_PAD_PATA_DA_0__GPIO7_6,
+       /* FEC_nINT */
+       MX53_PAD_PATA_DATA4__GPIO2_4,
+       /* AUDMUX5 */
+       MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
+       MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
+       MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
+       MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
+       /* I2C1 */
+       MX53_PAD_CSI0_DAT8__I2C1_SDA,
+       MX53_PAD_CSI0_DAT9__I2C1_SCL,
+       MX53_PAD_NANDF_CS1__GPIO6_14,   /* Accelerometer Enable */
+       /* I2C2 */
+       MX53_PAD_KEY_COL3__I2C2_SCL,
+       MX53_PAD_KEY_ROW3__I2C2_SDA,
+       /* SD1 */
+       MX53_PAD_SD1_CMD__ESDHC1_CMD,
+       MX53_PAD_SD1_CLK__ESDHC1_CLK,
+       MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+       MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+       MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+       MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+       /* SD1_CD */
+       MX53_PAD_EIM_DA13__GPIO3_13,
+       /* SD3 */
+       MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
+       MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
+       MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
+       MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
+       MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
+       MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
+       MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
+       MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
+       MX53_PAD_PATA_IORDY__ESDHC3_CLK,
+       MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+       /* SD3_CD */
+       MX53_PAD_EIM_DA11__GPIO3_11,
+       /* SD3_WP */
+       MX53_PAD_EIM_DA12__GPIO3_12,
+       /* VGA */
+       MX53_PAD_EIM_OE__IPU_DI1_PIN7,
+       MX53_PAD_EIM_RW__IPU_DI1_PIN8,
+       /* DISPLB */
+       MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
+       MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
+       MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
+       MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
+       /* DISP0_POWER_EN */
+       MX53_PAD_EIM_D24__GPIO3_24,
+       /* DISP0 DET INT */
+       MX53_PAD_EIM_D31__GPIO3_31,
+       /* LVDS */
+       MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+       MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+       MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+       MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+       MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+       MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
+       MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
+       MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
+       MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
+       MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
+       /* I2C1 */
+       MX53_PAD_CSI0_DAT8__I2C1_SDA,
+       MX53_PAD_CSI0_DAT9__I2C1_SCL,
+       /* UART1 */
+       MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+       MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+       /* CSI0 */
+       MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
+       MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
+       MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
+       MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
+       MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
+       MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
+       MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
+       MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
+       MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
+       MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
+       MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
+       /* DISPLAY */
+       MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+       MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+       MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+       MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+       MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+       MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+       MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+       MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+       MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+       MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+       MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+       MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+       MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+       MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+       MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+       MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+       MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+       MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+       MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+       MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+       MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+       MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+       MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+       MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+       MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+       MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+       MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+       MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+       /* Audio CLK*/
+       MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
+       /* PWM */
+       MX53_PAD_GPIO_1__PWM2_PWMO,
+       /* SPDIF */
+       MX53_PAD_GPIO_7__SPDIF_PLOCK,
+       MX53_PAD_GPIO_17__SPDIF_OUT1,
+       /* GPIO */
+       MX53_PAD_PATA_DA_1__GPIO7_7,            /* LED */
+       MX53_PAD_PATA_DA_2__GPIO7_8,
+       MX53_PAD_PATA_DATA5__GPIO2_5,
+       MX53_PAD_PATA_DATA6__GPIO2_6,
+       MX53_PAD_PATA_DATA14__GPIO2_14,
+       MX53_PAD_PATA_DATA15__GPIO2_15,
+       MX53_PAD_PATA_INTRQ__GPIO7_2,
+       MX53_PAD_EIM_WAIT__GPIO5_0,
+       MX53_PAD_NANDF_WP_B__GPIO6_9,
+       MX53_PAD_NANDF_RB0__GPIO6_10,
+       MX53_PAD_NANDF_CS1__GPIO6_14,
+       MX53_PAD_NANDF_CS2__GPIO6_15,
+       MX53_PAD_NANDF_CS3__GPIO6_16,
+       MX53_PAD_GPIO_5__GPIO1_5,
+       MX53_PAD_GPIO_16__GPIO7_11,
+       MX53_PAD_GPIO_8__GPIO1_8,
+};
+
+#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)   \
+{                                                              \
+       .gpio           = gpio_num,                             \
+       .type           = EV_KEY,                               \
+       .code           = ev_code,                              \
+       .active_low     = act_low,                              \
+       .desc           = "btn " descr,                         \
+       .wakeup         = wake,                                 \
+}
+
+static struct gpio_keys_button loco_buttons[] = {
+       GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
+       GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
+       GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
+};
+
+static const struct gpio_keys_platform_data loco_button_data __initconst = {
+       .buttons        = loco_buttons,
+       .nbuttons       = ARRAY_SIZE(loco_buttons),
+};
+
+static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
+       .cd_gpio = LOCO_SD1_CD,
+       .cd_type = ESDHC_CD_GPIO,
+       .wp_type = ESDHC_WP_NONE,
+};
+
+static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
+       .cd_gpio = LOCO_SD3_CD,
+       .wp_gpio = LOCO_SD3_WP,
+       .cd_type = ESDHC_CD_GPIO,
+       .wp_type = ESDHC_WP_GPIO,
+};
+
+static inline void mx53_loco_fec_reset(void)
+{
+       int ret;
+
+       /* reset FEC PHY */
+       ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
+       if (ret) {
+               printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+               return;
+       }
+       gpio_direction_output(LOCO_FEC_PHY_RST, 0);
+       msleep(1);
+       gpio_set_value(LOCO_FEC_PHY_RST, 1);
+}
+
+static struct fec_platform_data mx53_loco_fec_data = {
+       .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
+       .bitrate = 100000,
+};
+
+static const struct gpio_led mx53loco_leds[] __initconst = {
+       {
+               .name                   = "green",
+               .default_trigger        = "heartbeat",
+               .gpio                   = LOCO_LED,
+       },
+};
+
+static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
+       .leds           = mx53loco_leds,
+       .num_leds       = ARRAY_SIZE(mx53loco_leds),
+};
+
+void __init imx53_qsb_common_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
+                                        ARRAY_SIZE(mx53_loco_pads));
+}
+
+static struct i2c_board_info mx53loco_i2c_devices[] = {
+       {
+               I2C_BOARD_INFO("mma8450", 0x1C),
+       },
+};
+
+static void __init mx53_loco_board_init(void)
+{
+       int ret;
+       imx53_soc_init();
+       imx53_qsb_common_init();
+
+       imx53_add_imx_uart(0, NULL);
+       mx53_loco_fec_reset();
+       imx53_add_fec(&mx53_loco_fec_data);
+       imx53_add_imx2_wdt(0, NULL);
+
+       ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
+       if (ret)
+               pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
+
+       i2c_register_board_info(0, mx53loco_i2c_devices,
+                               ARRAY_SIZE(mx53loco_i2c_devices));
+       imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
+       imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
+       imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
+       imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
+       imx_add_gpio_keys(&loco_button_data);
+       gpio_led_register_device(-1, &mx53loco_leds_data);
+       imx53_add_ahci_imx();
+}
+
+static void __init mx53_loco_timer_init(void)
+{
+       mx53_clocks_init(32768, 24000000, 0, 0);
+}
+
+static struct sys_timer mx53_loco_timer = {
+       .init   = mx53_loco_timer_init,
+};
+
+MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
+       .map_io = mx53_map_io,
+       .init_early = imx53_init_early,
+       .init_irq = mx53_init_irq,
+       .handle_irq = imx53_handle_irq,
+       .timer = &mx53_loco_timer,
+       .init_machine = mx53_loco_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
new file mode 100644 (file)
index 0000000..d498573
--- /dev/null
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx53.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx53.h"
+
+#define SMD_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
+#define MX53_SMD_SATA_PWR_EN    IMX_GPIO_NR(3, 3)
+
+static iomux_v3_cfg_t mx53_smd_pads[] = {
+       MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+       MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+
+       MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+       MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+
+       MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
+       MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
+       MX53_PAD_PATA_DA_1__UART3_CTS,
+       MX53_PAD_PATA_DA_2__UART3_RTS,
+       /* I2C1 */
+       MX53_PAD_CSI0_DAT8__I2C1_SDA,
+       MX53_PAD_CSI0_DAT9__I2C1_SCL,
+       /* SD1 */
+       MX53_PAD_SD1_CMD__ESDHC1_CMD,
+       MX53_PAD_SD1_CLK__ESDHC1_CLK,
+       MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+       MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+       MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+       MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+       /* SD2 */
+       MX53_PAD_SD2_CMD__ESDHC2_CMD,
+       MX53_PAD_SD2_CLK__ESDHC2_CLK,
+       MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
+       MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
+       MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
+       MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
+       /* SD3 */
+       MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
+       MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
+       MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
+       MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
+       MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
+       MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
+       MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
+       MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
+       MX53_PAD_PATA_IORDY__ESDHC3_CLK,
+       MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+};
+
+static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mx53_smd_init_uart(void)
+{
+       imx53_add_imx_uart(0, NULL);
+       imx53_add_imx_uart(1, NULL);
+       imx53_add_imx_uart(2, &mx53_smd_uart_data);
+}
+
+static inline void mx53_smd_fec_reset(void)
+{
+       int ret;
+
+       /* reset FEC PHY */
+       ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
+       if (ret) {
+               printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
+               return;
+       }
+       gpio_direction_output(SMD_FEC_PHY_RST, 0);
+       msleep(1);
+       gpio_set_value(SMD_FEC_PHY_RST, 1);
+}
+
+static struct fec_platform_data mx53_smd_fec_data = {
+       .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
+       .bitrate = 100000,
+};
+
+static inline void mx53_smd_ahci_pwr_on(void)
+{
+       int ret;
+
+       /* Enable SATA PWR */
+       ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
+                       GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
+       if (ret) {
+               pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
+               return;
+       }
+}
+
+void __init imx53_smd_common_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
+                                        ARRAY_SIZE(mx53_smd_pads));
+}
+
+static void __init mx53_smd_board_init(void)
+{
+       imx53_soc_init();
+       imx53_smd_common_init();
+
+       mx53_smd_init_uart();
+       mx53_smd_fec_reset();
+       imx53_add_fec(&mx53_smd_fec_data);
+       imx53_add_imx2_wdt(0, NULL);
+       imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
+       imx53_add_sdhci_esdhc_imx(0, NULL);
+       imx53_add_sdhci_esdhc_imx(1, NULL);
+       imx53_add_sdhci_esdhc_imx(2, NULL);
+       mx53_smd_ahci_pwr_on();
+       imx53_add_ahci_imx();
+}
+
+static void __init mx53_smd_timer_init(void)
+{
+       mx53_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mx53_smd_timer = {
+       .init   = mx53_smd_timer_init,
+};
+
+MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
+       .map_io = mx53_map_io,
+       .init_early = imx53_init_early,
+       .init_irq = mx53_init_irq,
+       .handle_irq = imx53_handle_irq,
+       .timer = &mx53_smd_timer,
+       .init_machine = mx53_smd_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
new file mode 100644 (file)
index 0000000..26eacc9
--- /dev/null
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License.  You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ *
+ * Create static mapping between physical to virtual memory.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/devices-common.h>
+#include <mach/iomux-v3.h>
+
+static void imx5_idle(void)
+{
+       mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+}
+
+/*
+ * Define the MX50 memory map.
+ */
+static struct map_desc mx50_io_desc[] __initdata = {
+       imx_map_entry(MX50, TZIC, MT_DEVICE),
+       imx_map_entry(MX50, SPBA0, MT_DEVICE),
+       imx_map_entry(MX50, AIPS1, MT_DEVICE),
+       imx_map_entry(MX50, AIPS2, MT_DEVICE),
+};
+
+/*
+ * Define the MX51 memory map.
+ */
+static struct map_desc mx51_io_desc[] __initdata = {
+       imx_map_entry(MX51, TZIC, MT_DEVICE),
+       imx_map_entry(MX51, IRAM, MT_DEVICE),
+       imx_map_entry(MX51, AIPS1, MT_DEVICE),
+       imx_map_entry(MX51, SPBA0, MT_DEVICE),
+       imx_map_entry(MX51, AIPS2, MT_DEVICE),
+};
+
+/*
+ * Define the MX53 memory map.
+ */
+static struct map_desc mx53_io_desc[] __initdata = {
+       imx_map_entry(MX53, TZIC, MT_DEVICE),
+       imx_map_entry(MX53, AIPS1, MT_DEVICE),
+       imx_map_entry(MX53, SPBA0, MT_DEVICE),
+       imx_map_entry(MX53, AIPS2, MT_DEVICE),
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx50_map_io(void)
+{
+       iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
+}
+
+void __init mx51_map_io(void)
+{
+       iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
+}
+
+void __init mx53_map_io(void)
+{
+       iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+}
+
+void __init imx50_init_early(void)
+{
+       mxc_set_cpu_type(MXC_CPU_MX50);
+       mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
+       mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
+}
+
+void __init imx51_init_early(void)
+{
+       mxc_set_cpu_type(MXC_CPU_MX51);
+       mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
+       mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
+       imx_idle = imx5_idle;
+}
+
+void __init imx53_init_early(void)
+{
+       mxc_set_cpu_type(MXC_CPU_MX53);
+       mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
+       mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
+}
+
+void __init mx50_init_irq(void)
+{
+       tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
+}
+
+void __init mx51_init_irq(void)
+{
+       tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
+}
+
+void __init mx53_init_irq(void)
+{
+       tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
+}
+
+static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
+       .ap_2_ap_addr = 642,
+       .uart_2_mcu_addr = 817,
+       .mcu_2_app_addr = 747,
+       .mcu_2_shp_addr = 961,
+       .ata_2_mcu_addr = 1473,
+       .mcu_2_ata_addr = 1392,
+       .app_2_per_addr = 1033,
+       .app_2_mcu_addr = 683,
+       .shp_2_per_addr = 1251,
+       .shp_2_mcu_addr = 892,
+};
+
+static struct sdma_platform_data imx51_sdma_pdata __initdata = {
+       .fw_name = "sdma-imx51.bin",
+       .script_addrs = &imx51_sdma_script,
+};
+
+static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
+       .ap_2_ap_addr = 642,
+       .app_2_mcu_addr = 683,
+       .mcu_2_app_addr = 747,
+       .uart_2_mcu_addr = 817,
+       .shp_2_mcu_addr = 891,
+       .mcu_2_shp_addr = 960,
+       .uartsh_2_mcu_addr = 1032,
+       .spdif_2_mcu_addr = 1100,
+       .mcu_2_spdif_addr = 1134,
+       .firi_2_mcu_addr = 1193,
+       .mcu_2_firi_addr = 1290,
+};
+
+static struct sdma_platform_data imx53_sdma_pdata __initdata = {
+       .fw_name = "sdma-imx53.bin",
+       .script_addrs = &imx53_sdma_script,
+};
+
+void __init imx50_soc_init(void)
+{
+       /* i.mx50 has the i.mx31 type gpio */
+       mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
+       mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
+       mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
+       mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
+       mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
+       mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
+}
+
+void __init imx51_soc_init(void)
+{
+       /* i.mx51 has the i.mx31 type gpio */
+       mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
+       mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
+       mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
+       mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
+
+       /* i.mx51 has the i.mx35 type sdma */
+       imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+}
+
+void __init imx53_soc_init(void)
+{
+       /* i.mx53 has the i.mx31 type gpio */
+       mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
+       mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
+       mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
+       mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
+       mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
+       mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
+       mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
+
+       /* i.mx53 has the i.mx35 type sdma */
+       imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+}
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
new file mode 100644 (file)
index 0000000..ec6ca91
--- /dev/null
@@ -0,0 +1,632 @@
+/*
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <mach/ulpi.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "efika.h"
+#include "cpu_op-mx51.h"
+
+#define MX51_USB_CTRL_1_OFFSET          0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
+#define        MX51_USB_PLL_DIV_19_2_MHZ       0x01
+
+#define EFIKAMX_USB_HUB_RESET  IMX_GPIO_NR(1, 5)
+#define EFIKAMX_USBH1_STP      IMX_GPIO_NR(1, 27)
+
+#define EFIKAMX_SPI_CS0                IMX_GPIO_NR(4, 24)
+#define EFIKAMX_SPI_CS1                IMX_GPIO_NR(4, 25)
+
+#define EFIKAMX_PMIC           IMX_GPIO_NR(1, 6)
+
+static iomux_v3_cfg_t mx51efika_pads[] = {
+       /* UART1 */
+       MX51_PAD_UART1_RXD__UART1_RXD,
+       MX51_PAD_UART1_TXD__UART1_TXD,
+       MX51_PAD_UART1_RTS__UART1_RTS,
+       MX51_PAD_UART1_CTS__UART1_CTS,
+
+       /* SD 1 */
+       MX51_PAD_SD1_CMD__SD1_CMD,
+       MX51_PAD_SD1_CLK__SD1_CLK,
+       MX51_PAD_SD1_DATA0__SD1_DATA0,
+       MX51_PAD_SD1_DATA1__SD1_DATA1,
+       MX51_PAD_SD1_DATA2__SD1_DATA2,
+       MX51_PAD_SD1_DATA3__SD1_DATA3,
+
+       /* SD 2 */
+       MX51_PAD_SD2_CMD__SD2_CMD,
+       MX51_PAD_SD2_CLK__SD2_CLK,
+       MX51_PAD_SD2_DATA0__SD2_DATA0,
+       MX51_PAD_SD2_DATA1__SD2_DATA1,
+       MX51_PAD_SD2_DATA2__SD2_DATA2,
+       MX51_PAD_SD2_DATA3__SD2_DATA3,
+
+       /* SD/MMC WP/CD */
+       MX51_PAD_GPIO1_0__SD1_CD,
+       MX51_PAD_GPIO1_1__SD1_WP,
+       MX51_PAD_GPIO1_7__SD2_WP,
+       MX51_PAD_GPIO1_8__SD2_CD,
+
+       /* spi */
+       MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+       MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+       MX51_PAD_CSPI1_SS0__GPIO4_24,
+       MX51_PAD_CSPI1_SS1__GPIO4_25,
+       MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
+       MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+       MX51_PAD_GPIO1_6__GPIO1_6,
+
+       /* USB HOST1 */
+       MX51_PAD_USBH1_CLK__USBH1_CLK,
+       MX51_PAD_USBH1_DIR__USBH1_DIR,
+       MX51_PAD_USBH1_NXT__USBH1_NXT,
+       MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+       MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+       MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+       MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+       MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+       MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+       MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+       MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+
+       /* USB HUB RESET */
+       MX51_PAD_GPIO1_5__GPIO1_5,
+
+       /* WLAN */
+       MX51_PAD_EIM_A22__GPIO2_16,
+       MX51_PAD_EIM_A16__GPIO2_10,
+
+       /* USB PHY RESET */
+       MX51_PAD_EIM_D27__GPIO2_9,
+};
+
+/* Serial ports */
+static const struct imxuart_platform_data uart_pdata = {
+       .flags = IMXUART_HAVE_RTSCTS,
+};
+
+/* This function is board specific as the bit mask for the plldiv will also
+ * be different for other Freescale SoCs, thus a common bitmask is not
+ * possible and cannot get place in /plat-mxc/ehci.c.
+ */
+static int initialize_otg_port(struct platform_device *pdev)
+{
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *usbother_base;
+       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
+       if (!usb_base)
+               return -ENOMEM;
+       usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+
+       /* Set the PHY clock to 19.2MHz */
+       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+       v |= MX51_USB_PLL_DIV_19_2_MHZ;
+       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+       iounmap(usb_base);
+
+       mdelay(10);
+
+       return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
+}
+
+static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
+       .init   = initialize_otg_port,
+       .portsc = MXC_EHCI_UTMI_16BIT,
+};
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+       iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+       iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
+       u32 v;
+       void __iomem *usb_base;
+       void __iomem *socregs_base;
+
+       mxc_iomux_v3_setup_pad(usbh1gpio);
+       gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
+       gpio_direction_output(EFIKAMX_USBH1_STP, 0);
+       msleep(1);
+       gpio_set_value(EFIKAMX_USBH1_STP, 1);
+       msleep(1);
+
+       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
+       socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+
+       /* The clock for the USBH1 ULPI port will come externally */
+       /* from the PHY. */
+       v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
+       __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
+                       socregs_base + MX51_USB_CTRL_1_OFFSET);
+
+       iounmap(usb_base);
+
+       gpio_free(EFIKAMX_USBH1_STP);
+       mxc_iomux_v3_setup_pad(usbh1stp);
+
+       mdelay(10);
+
+       return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
+}
+
+static struct mxc_usbh_platform_data usbh1_config __initdata = {
+       .init   = initialize_usbh1_port,
+       .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static void mx51_efika_hubreset(void)
+{
+       gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
+       gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
+       msleep(1);
+       gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
+       msleep(1);
+       gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
+}
+
+static void __init mx51_efika_usb(void)
+{
+       mx51_efika_hubreset();
+
+       /* pulling it low, means no USB at all... */
+       gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
+       gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
+       msleep(1);
+       gpio_set_value(EFIKA_USB_PHY_RESET, 1);
+
+       usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                       ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
+
+       imx51_add_mxc_ehci_otg(&dr_utmi_config);
+       if (usbh1_config.otg)
+               imx51_add_mxc_ehci_hs(1, &usbh1_config);
+}
+
+static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
+       {
+        .name = "u-boot",
+        .offset = 0,
+        .size = SZ_256K,
+       },
+       {
+         .name = "config",
+         .offset = MTDPART_OFS_APPEND,
+         .size = SZ_64K,
+       },
+};
+
+static struct flash_platform_data mx51_efika_spi_flash_data = {
+       .name           = "spi_flash",
+       .parts          = mx51_efika_spi_nor_partitions,
+       .nr_parts       = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
+       .type           = "sst25vf032b",
+};
+
+static struct regulator_consumer_supply sw1_consumers[] = {
+       {
+               .supply = "cpu_vcc",
+       }
+};
+
+static struct regulator_consumer_supply vdig_consumers[] = {
+       /* sgtl5000 */
+       REGULATOR_SUPPLY("VDDA", "1-000a"),
+       REGULATOR_SUPPLY("VDDD", "1-000a"),
+};
+
+static struct regulator_consumer_supply vvideo_consumers[] = {
+       /* sgtl5000 */
+       REGULATOR_SUPPLY("VDDIO", "1-000a"),
+};
+
+static struct regulator_consumer_supply vsd_consumers[] = {
+       REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
+       REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
+};
+
+static struct regulator_consumer_supply pwgt1_consumer[] = {
+       {
+               .supply = "pwgt1",
+       }
+};
+
+static struct regulator_consumer_supply pwgt2_consumer[] = {
+       {
+               .supply = "pwgt2",
+       }
+};
+
+static struct regulator_consumer_supply coincell_consumer[] = {
+       {
+               .supply = "coincell",
+       }
+};
+
+static struct regulator_init_data sw1_init = {
+       .constraints = {
+               .name = "SW1",
+               .min_uV = 600000,
+               .max_uV = 1375000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .valid_modes_mask = 0,
+               .always_on = 1,
+               .boot_on = 1,
+               .state_mem = {
+                       .uV = 850000,
+                       .mode = REGULATOR_MODE_NORMAL,
+                       .enabled = 1,
+               },
+       },
+       .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+       .consumer_supplies = sw1_consumers,
+};
+
+static struct regulator_init_data sw2_init = {
+       .constraints = {
+               .name = "SW2",
+               .min_uV = 900000,
+               .max_uV = 1850000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .always_on = 1,
+               .boot_on = 1,
+               .state_mem = {
+                       .uV = 950000,
+                       .mode = REGULATOR_MODE_NORMAL,
+                       .enabled = 1,
+               },
+       }
+};
+
+static struct regulator_init_data sw3_init = {
+       .constraints = {
+               .name = "SW3",
+               .min_uV = 1100000,
+               .max_uV = 1850000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .always_on = 1,
+               .boot_on = 1,
+       }
+};
+
+static struct regulator_init_data sw4_init = {
+       .constraints = {
+               .name = "SW4",
+               .min_uV = 1100000,
+               .max_uV = 1850000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .always_on = 1,
+               .boot_on = 1,
+       }
+};
+
+static struct regulator_init_data viohi_init = {
+       .constraints = {
+               .name = "VIOHI",
+               .boot_on = 1,
+               .always_on = 1,
+       }
+};
+
+static struct regulator_init_data vusb_init = {
+       .constraints = {
+               .name = "VUSB",
+               .boot_on = 1,
+               .always_on = 1,
+       }
+};
+
+static struct regulator_init_data swbst_init = {
+       .constraints = {
+               .name = "SWBST",
+       }
+};
+
+static struct regulator_init_data vdig_init = {
+       .constraints = {
+               .name = "VDIG",
+               .min_uV = 1050000,
+               .max_uV = 1800000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+               .boot_on = 1,
+               .always_on = 1,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
+       .consumer_supplies = vdig_consumers,
+};
+
+static struct regulator_init_data vpll_init = {
+       .constraints = {
+               .name = "VPLL",
+               .min_uV = 1050000,
+               .max_uV = 1800000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+               .boot_on = 1,
+               .always_on = 1,
+       }
+};
+
+static struct regulator_init_data vusb2_init = {
+       .constraints = {
+               .name = "VUSB2",
+               .min_uV = 2400000,
+               .max_uV = 2775000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .boot_on = 1,
+               .always_on = 1,
+       }
+};
+
+static struct regulator_init_data vvideo_init = {
+       .constraints = {
+               .name = "VVIDEO",
+               .min_uV = 2775000,
+               .max_uV = 2775000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+               .boot_on = 1,
+               .apply_uV = 1,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
+       .consumer_supplies = vvideo_consumers,
+};
+
+static struct regulator_init_data vaudio_init = {
+       .constraints = {
+               .name = "VAUDIO",
+               .min_uV = 2300000,
+               .max_uV = 3000000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+               .boot_on = 1,
+       }
+};
+
+static struct regulator_init_data vsd_init = {
+       .constraints = {
+               .name = "VSD",
+               .min_uV = 1800000,
+               .max_uV = 3150000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE,
+               .boot_on = 1,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
+       .consumer_supplies = vsd_consumers,
+};
+
+static struct regulator_init_data vcam_init = {
+       .constraints = {
+               .name = "VCAM",
+               .min_uV = 2500000,
+               .max_uV = 3000000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE |
+                       REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+               .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+               .boot_on = 1,
+       }
+};
+
+static struct regulator_init_data vgen1_init = {
+       .constraints = {
+               .name = "VGEN1",
+               .min_uV = 1200000,
+               .max_uV = 3150000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+               .boot_on = 1,
+               .always_on = 1,
+       }
+};
+
+static struct regulator_init_data vgen2_init = {
+       .constraints = {
+               .name = "VGEN2",
+               .min_uV = 1200000,
+               .max_uV = 3150000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+               .boot_on = 1,
+               .always_on = 1,
+       }
+};
+
+static struct regulator_init_data vgen3_init = {
+       .constraints = {
+               .name = "VGEN3",
+               .min_uV = 1800000,
+               .max_uV = 2900000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+               .boot_on = 1,
+               .always_on = 1,
+       }
+};
+
+static struct regulator_init_data gpo1_init = {
+       .constraints = {
+               .name = "GPO1",
+       }
+};
+
+static struct regulator_init_data gpo2_init = {
+       .constraints = {
+               .name = "GPO2",
+       }
+};
+
+static struct regulator_init_data gpo3_init = {
+       .constraints = {
+               .name = "GPO3",
+       }
+};
+
+static struct regulator_init_data gpo4_init = {
+       .constraints = {
+               .name = "GPO4",
+       }
+};
+
+static struct regulator_init_data pwgt1_init = {
+       .constraints = {
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .boot_on        = 1,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
+       .consumer_supplies = pwgt1_consumer,
+};
+
+static struct regulator_init_data pwgt2_init = {
+       .constraints = {
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .boot_on        = 1,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
+       .consumer_supplies = pwgt2_consumer,
+};
+
+static struct regulator_init_data vcoincell_init = {
+       .constraints = {
+               .name = "COINCELL",
+               .min_uV = 3000000,
+               .max_uV = 3000000,
+               .valid_ops_mask =
+                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
+       .consumer_supplies = coincell_consumer,
+};
+
+static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
+       { .id = MC13892_SW1,            .init_data =  &sw1_init },
+       { .id = MC13892_SW2,            .init_data =  &sw2_init },
+       { .id = MC13892_SW3,            .init_data =  &sw3_init },
+       { .id = MC13892_SW4,            .init_data =  &sw4_init },
+       { .id = MC13892_SWBST,          .init_data =  &swbst_init },
+       { .id = MC13892_VIOHI,          .init_data =  &viohi_init },
+       { .id = MC13892_VPLL,           .init_data =  &vpll_init },
+       { .id = MC13892_VDIG,           .init_data =  &vdig_init },
+       { .id = MC13892_VSD,            .init_data =  &vsd_init },
+       { .id = MC13892_VUSB2,          .init_data =  &vusb2_init },
+       { .id = MC13892_VVIDEO,         .init_data =  &vvideo_init },
+       { .id = MC13892_VAUDIO,         .init_data =  &vaudio_init },
+       { .id = MC13892_VCAM,           .init_data =  &vcam_init },
+       { .id = MC13892_VGEN1,          .init_data =  &vgen1_init },
+       { .id = MC13892_VGEN2,          .init_data =  &vgen2_init },
+       { .id = MC13892_VGEN3,          .init_data =  &vgen3_init },
+       { .id = MC13892_VUSB,           .init_data =  &vusb_init },
+       { .id = MC13892_GPO1,           .init_data =  &gpo1_init },
+       { .id = MC13892_GPO2,           .init_data =  &gpo2_init },
+       { .id = MC13892_GPO3,           .init_data =  &gpo3_init },
+       { .id = MC13892_GPO4,           .init_data =  &gpo4_init },
+       { .id = MC13892_PWGT1SPI,       .init_data = &pwgt1_init },
+       { .id = MC13892_PWGT2SPI,       .init_data = &pwgt2_init },
+       { .id = MC13892_VCOINCELL,      .init_data = &vcoincell_init },
+};
+
+static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
+       .flags = MC13XXX_USE_RTC,
+       .regulators = {
+               .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
+               .regulators = mx51_efika_regulators,
+       },
+};
+
+static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
+       {
+               .modalias = "m25p80",
+               .max_speed_hz = 25000000,
+               .bus_num = 0,
+               .chip_select = 1,
+               .platform_data = &mx51_efika_spi_flash_data,
+               .irq = -1,
+       },
+       {
+               .modalias = "mc13892",
+               .max_speed_hz = 1000000,
+               .bus_num = 0,
+               .chip_select = 0,
+               .platform_data = &mx51_efika_mc13892_data,
+               .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
+       },
+};
+
+static int mx51_efika_spi_cs[] = {
+       EFIKAMX_SPI_CS0,
+       EFIKAMX_SPI_CS1,
+};
+
+static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
+       .chipselect     = mx51_efika_spi_cs,
+       .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
+};
+
+void __init efika_board_common_init(void)
+{
+       mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
+                                       ARRAY_SIZE(mx51efika_pads));
+       imx51_add_imx_uart(0, &uart_pdata);
+       mx51_efika_usb();
+
+       /* FIXME: comes from original code. check this. */
+       if (mx51_revision() < IMX_CHIP_REVISION_2_0)
+               sw2_init.constraints.state_mem.uV = 1100000;
+       else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
+               sw2_init.constraints.state_mem.uV = 1250000;
+               sw1_init.constraints.state_mem.uV = 1000000;
+       }
+       if (machine_is_mx51_efikasb())
+               vgen1_init.constraints.max_uV = 1200000;
+
+       gpio_request(EFIKAMX_PMIC, "pmic irq");
+       gpio_direction_input(EFIKAMX_PMIC);
+       spi_register_board_info(mx51_efika_spi_board_info,
+               ARRAY_SIZE(mx51_efika_spi_board_info));
+       imx51_add_ecspi(0, &mx51_efika_spi_pdata);
+
+       imx51_add_pata_imx();
+
+#if defined(CONFIG_CPU_FREQ_IMX)
+       get_cpu_op = mx51_get_cpu_op;
+#endif
+}
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
new file mode 100644 (file)
index 0000000..3d57b5d
--- /dev/null
@@ -0,0 +1,156 @@
+/*
+ *  Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/suspend.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include "crm-regs-imx5.h"
+
+static struct clk *gpc_dvfs_clk;
+
+/*
+ * set cpu low power mode before WFI instruction. This function is called
+ * mx5 because it can be used for mx50, mx51, and mx53.
+ */
+void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
+{
+       u32 plat_lpc, arm_srpgcr, ccm_clpcr;
+       u32 empgc0, empgc1;
+       int stop_mode = 0;
+
+       /* always allow platform to issue a deep sleep mode request */
+       plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
+           ~(MXC_CORTEXA8_PLAT_LPC_DSM);
+       ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
+       arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
+       empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
+       empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
+
+       switch (mode) {
+       case WAIT_CLOCKED:
+               break;
+       case WAIT_UNCLOCKED:
+               ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
+               break;
+       case WAIT_UNCLOCKED_POWER_OFF:
+       case STOP_POWER_OFF:
+               plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
+                           | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
+               if (mode == WAIT_UNCLOCKED_POWER_OFF) {
+                       ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
+                       ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
+                       ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
+                       stop_mode = 0;
+               } else {
+                       ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
+                       ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
+                       ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
+                       ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
+                       stop_mode = 1;
+               }
+               arm_srpgcr |= MXC_SRPGCR_PCR;
+
+               if (tzic_enable_wake(1) != 0)
+                       return;
+               break;
+       case STOP_POWER_ON:
+               ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
+               break;
+       default:
+               printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
+               return;
+       }
+
+       __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
+       __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
+       __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
+
+       /* Enable NEON SRPG for all but MX50TO1.0. */
+       if (mx50_revision() != IMX_CHIP_REVISION_1_0)
+               __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
+
+       if (stop_mode) {
+               empgc0 |= MXC_SRPGCR_PCR;
+               empgc1 |= MXC_SRPGCR_PCR;
+
+               __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
+               __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
+       }
+}
+
+static int mx5_suspend_prepare(void)
+{
+       return clk_enable(gpc_dvfs_clk);
+}
+
+static int mx5_suspend_enter(suspend_state_t state)
+{
+       switch (state) {
+       case PM_SUSPEND_MEM:
+               mx5_cpu_lp_set(STOP_POWER_OFF);
+               break;
+       case PM_SUSPEND_STANDBY:
+               mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       if (state == PM_SUSPEND_MEM) {
+               local_flush_tlb_all();
+               flush_cache_all();
+
+               /*clear the EMPGC0/1 bits */
+               __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
+               __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
+       }
+       cpu_do_idle();
+       return 0;
+}
+
+static void mx5_suspend_finish(void)
+{
+       clk_disable(gpc_dvfs_clk);
+}
+
+static int mx5_pm_valid(suspend_state_t state)
+{
+       return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
+}
+
+static const struct platform_suspend_ops mx5_suspend_ops = {
+       .valid = mx5_pm_valid,
+       .prepare = mx5_suspend_prepare,
+       .enter = mx5_suspend_enter,
+       .finish = mx5_suspend_finish,
+};
+
+static int __init mx5_pm_init(void)
+{
+       if (!cpu_is_mx51() && !cpu_is_mx53())
+               return 0;
+
+       if (gpc_dvfs_clk == NULL)
+               gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+
+       if (!IS_ERR(gpc_dvfs_clk)) {
+               if (cpu_is_mx51())
+                       suspend_set_ops(&mx5_suspend_ops);
+       } else
+               return -EPERM;
+
+       return 0;
+}
+device_initcall(mx5_pm_init);
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
deleted file mode 100644 (file)
index af0c212..0000000
+++ /dev/null
@@ -1,244 +0,0 @@
-if ARCH_MX5
-
-# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
-# image. So for most time, SOC_IMX50/51/53 should be used.
-
-config ARCH_MX51
-       bool
-
-config ARCH_MX50
-       bool
-
-config ARCH_MX53
-       bool
-
-config SOC_IMX50
-       bool
-       select CPU_V7
-       select ARM_L1_CACHE_SHIFT_6
-       select MXC_TZIC
-       select ARCH_MXC_IOMUX_V3
-       select ARCH_MXC_AUDMUX_V2
-       select ARCH_HAS_CPUFREQ
-       select ARCH_MX50
-
-config SOC_IMX51
-       bool
-       select CPU_V7
-       select ARM_L1_CACHE_SHIFT_6
-       select MXC_TZIC
-       select ARCH_MXC_IOMUX_V3
-       select ARCH_MXC_AUDMUX_V2
-       select ARCH_HAS_CPUFREQ
-       select ARCH_MX51
-
-config SOC_IMX53
-       bool
-       select CPU_V7
-       select ARM_L1_CACHE_SHIFT_6
-       select MXC_TZIC
-       select ARCH_MXC_IOMUX_V3
-       select ARCH_MX53
-
-#comment "i.MX50 machines:"
-
-config MACH_MX50_RDP
-       bool "Support MX50 reference design platform"
-       depends on BROKEN
-       select SOC_IMX50
-       select IMX_HAVE_PLATFORM_IMX_I2C
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       select IMX_HAVE_PLATFORM_SPI_IMX
-       help
-         Include support for MX50 reference design platform (RDP) board. This
-         includes specific configurations for the board and its peripherals.
-
-comment "i.MX51 machines:"
-
-config MACH_IMX51_DT
-       bool "Support i.MX51 platforms from device tree"
-       select SOC_IMX51
-       select USE_OF
-       select MACH_MX51_BABBAGE
-       help
-         Include support for Freescale i.MX51 based platforms
-         using the device tree for discovery
-
-config MACH_MX51_BABBAGE
-       bool "Support MX51 BABBAGE platforms"
-       select SOC_IMX51
-       select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-       select IMX_HAVE_PLATFORM_IMX2_WDT
-       select IMX_HAVE_PLATFORM_IMX_I2C
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_MXC_EHCI
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       select IMX_HAVE_PLATFORM_SPI_IMX
-       help
-         Include support for MX51 Babbage platform, also known as MX51EVK in
-         u-boot. This includes specific configurations for the board and its
-         peripherals.
-
-config MACH_MX51_3DS
-       bool "Support MX51PDK (3DS)"
-       select SOC_IMX51
-       select IMX_HAVE_PLATFORM_IMX2_WDT
-       select IMX_HAVE_PLATFORM_IMX_KEYPAD
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       select IMX_HAVE_PLATFORM_SPI_IMX
-       select MXC_DEBUG_BOARD
-       help
-         Include support for MX51PDK (3DS) platform. This includes specific
-         configurations for the board and its peripherals.
-
-config MACH_EUKREA_CPUIMX51
-       bool "Support Eukrea CPUIMX51 module"
-       select SOC_IMX51
-       select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-       select IMX_HAVE_PLATFORM_IMX_I2C
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_MXC_EHCI
-       select IMX_HAVE_PLATFORM_MXC_NAND
-       select IMX_HAVE_PLATFORM_SPI_IMX
-       help
-         Include support for Eukrea CPUIMX51 platform. This includes
-         specific configurations for the module and its peripherals.
-
-choice
-       prompt "Baseboard"
-       depends on MACH_EUKREA_CPUIMX51
-       default MACH_EUKREA_MBIMX51_BASEBOARD
-
-config MACH_EUKREA_MBIMX51_BASEBOARD
-       prompt "Eukrea MBIMX51 development board"
-       bool
-       select IMX_HAVE_PLATFORM_IMX_KEYPAD
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       select LEDS_GPIO_REGISTER
-       help
-         This adds board specific devices that can be found on Eukrea's
-         MBIMX51 evaluation board.
-
-endchoice
-
-config MACH_EUKREA_CPUIMX51SD
-       bool "Support Eukrea CPUIMX51SD module"
-       select SOC_IMX51
-       select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-       select IMX_HAVE_PLATFORM_IMX_I2C
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_MXC_EHCI
-       select IMX_HAVE_PLATFORM_MXC_NAND
-       select IMX_HAVE_PLATFORM_SPI_IMX
-       help
-         Include support for Eukrea CPUIMX51SD platform. This includes
-         specific configurations for the module and its peripherals.
-
-choice
-       prompt "Baseboard"
-       depends on MACH_EUKREA_CPUIMX51SD
-       default MACH_EUKREA_MBIMXSD51_BASEBOARD
-
-config MACH_EUKREA_MBIMXSD51_BASEBOARD
-       prompt "Eukrea MBIMXSD development board"
-       bool
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       select LEDS_GPIO_REGISTER
-       help
-         This adds board specific devices that can be found on Eukrea's
-         MBIMXSD evaluation board.
-
-endchoice
-
-config MX51_EFIKA_COMMON
-       bool
-       select SOC_IMX51
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_MXC_EHCI
-       select IMX_HAVE_PLATFORM_PATA_IMX
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       select IMX_HAVE_PLATFORM_SPI_IMX
-       select MXC_ULPI if USB_ULPI
-
-config MACH_MX51_EFIKAMX
-       bool "Support MX51 Genesi Efika MX nettop"
-       select LEDS_GPIO_REGISTER
-       select MX51_EFIKA_COMMON
-       help
-         Include support for Genesi Efika MX nettop. This includes specific
-         configurations for the board and its peripherals.
-
-config MACH_MX51_EFIKASB
-       bool "Support MX51 Genesi Efika Smartbook"
-       select LEDS_GPIO_REGISTER
-       select MX51_EFIKA_COMMON
-       help
-         Include support for Genesi Efika Smartbook. This includes specific
-         configurations for the board and its peripherals.
-
-comment "i.MX53 machines:"
-
-config MACH_IMX53_DT
-       bool "Support i.MX53 platforms from device tree"
-       select SOC_IMX53
-       select USE_OF
-       select MACH_MX53_ARD
-       select MACH_MX53_EVK
-       select MACH_MX53_LOCO
-       select MACH_MX53_SMD
-       help
-         Include support for Freescale i.MX53 based platforms
-         using the device tree for discovery
-
-config MACH_MX53_EVK
-       bool "Support MX53 EVK platforms"
-       select SOC_IMX53
-       select IMX_HAVE_PLATFORM_IMX2_WDT
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_IMX_I2C
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       select IMX_HAVE_PLATFORM_SPI_IMX
-       select LEDS_GPIO_REGISTER
-       help
-         Include support for MX53 EVK platform. This includes specific
-         configurations for the board and its peripherals.
-
-config MACH_MX53_SMD
-       bool "Support MX53 SMD platforms"
-       select SOC_IMX53
-       select IMX_HAVE_PLATFORM_IMX2_WDT
-       select IMX_HAVE_PLATFORM_IMX_I2C
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       help
-         Include support for MX53 SMD platform. This includes specific
-         configurations for the board and its peripherals.
-
-config MACH_MX53_LOCO
-       bool "Support MX53 LOCO platforms"
-       select SOC_IMX53
-       select IMX_HAVE_PLATFORM_IMX2_WDT
-       select IMX_HAVE_PLATFORM_IMX_I2C
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       select IMX_HAVE_PLATFORM_GPIO_KEYS
-       select LEDS_GPIO_REGISTER
-       help
-         Include support for MX53 LOCO platform. This includes specific
-         configurations for the board and its peripherals.
-
-config MACH_MX53_ARD
-       bool "Support MX53 ARD platforms"
-       select SOC_IMX53
-       select IMX_HAVE_PLATFORM_IMX2_WDT
-       select IMX_HAVE_PLATFORM_IMX_I2C
-       select IMX_HAVE_PLATFORM_IMX_UART
-       select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-       select IMX_HAVE_PLATFORM_GPIO_KEYS
-       help
-         Include support for MX53 ARD platform. This includes specific
-         configurations for the board and its peripherals.
-
-endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
deleted file mode 100644 (file)
index 0fc6080..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-obj-y   := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o
-
-obj-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
-obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
-obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
-obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
-obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
-obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
-obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
-obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
-obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
-obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
-obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
-
-obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
-obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot
deleted file mode 100644 (file)
index ca207ca..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-   zreladdr-$(CONFIG_ARCH_MX50)        += 0x70008000
-params_phys-$(CONFIG_ARCH_MX50)        := 0x70000100
-initrd_phys-$(CONFIG_ARCH_MX50)        := 0x70800000
-   zreladdr-$(CONFIG_ARCH_MX51)        += 0x90008000
-params_phys-$(CONFIG_ARCH_MX51)        := 0x90000100
-initrd_phys-$(CONFIG_ARCH_MX51)        := 0x90800000
-   zreladdr-$(CONFIG_ARCH_MX53)        += 0x70008000
-params_phys-$(CONFIG_ARCH_MX53)        := 0x70000100
-initrd_phys-$(CONFIG_ARCH_MX53)        := 0x70800000
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
deleted file mode 100644 (file)
index 1fc1103..0000000
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- *
- * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
- *
- * based on board-mx51_babbage.c which is
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-
-#include <mach/eukrea-baseboards.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-
-#define CPUIMX51_USBH1_STP     IMX_GPIO_NR(1, 27)
-#define CPUIMX51_QUARTA_GPIO   IMX_GPIO_NR(3, 28)
-#define CPUIMX51_QUARTB_GPIO   IMX_GPIO_NR(3, 25)
-#define CPUIMX51_QUARTC_GPIO   IMX_GPIO_NR(3, 26)
-#define CPUIMX51_QUARTD_GPIO   IMX_GPIO_NR(3, 27)
-#define CPUIMX51_QUART_XTAL    14745600
-#define CPUIMX51_QUART_REGSHIFT        17
-
-/* USB_CTRL_1 */
-#define MX51_USB_CTRL_1_OFFSET         0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN   (1 << 25)
-
-#define        MX51_USB_PLLDIV_12_MHZ          0x00
-#define        MX51_USB_PLL_DIV_19_2_MHZ       0x01
-#define        MX51_USB_PLL_DIV_24_MHZ         0x02
-
-static struct plat_serial8250_port serial_platform_data[] = {
-       {
-               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
-               .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
-               .irqflags = IRQF_TRIGGER_HIGH,
-               .uartclk = CPUIMX51_QUART_XTAL,
-               .regshift = CPUIMX51_QUART_REGSHIFT,
-               .iotype = UPIO_MEM,
-               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-       }, {
-               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
-               .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
-               .irqflags = IRQF_TRIGGER_HIGH,
-               .uartclk = CPUIMX51_QUART_XTAL,
-               .regshift = CPUIMX51_QUART_REGSHIFT,
-               .iotype = UPIO_MEM,
-               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-       }, {
-               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
-               .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
-               .irqflags = IRQF_TRIGGER_HIGH,
-               .uartclk = CPUIMX51_QUART_XTAL,
-               .regshift = CPUIMX51_QUART_REGSHIFT,
-               .iotype = UPIO_MEM,
-               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-       }, {
-               .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
-               .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
-               .irqflags = IRQF_TRIGGER_HIGH,
-               .uartclk = CPUIMX51_QUART_XTAL,
-               .regshift = CPUIMX51_QUART_REGSHIFT,
-               .iotype = UPIO_MEM,
-               .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-       }, {
-       }
-};
-
-static struct platform_device serial_device = {
-       .name = "serial8250",
-       .id = 0,
-       .dev = {
-               .platform_data = serial_platform_data,
-       },
-};
-
-static struct platform_device *devices[] __initdata = {
-       &serial_device,
-};
-
-static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
-       /* UART1 */
-       MX51_PAD_UART1_RXD__UART1_RXD,
-       MX51_PAD_UART1_TXD__UART1_TXD,
-       MX51_PAD_UART1_RTS__UART1_RTS,
-       MX51_PAD_UART1_CTS__UART1_CTS,
-
-       /* I2C2 */
-       MX51_PAD_GPIO1_2__I2C2_SCL,
-       MX51_PAD_GPIO1_3__I2C2_SDA,
-       MX51_PAD_NANDF_D10__GPIO3_30,
-
-       /* QUART IRQ */
-       MX51_PAD_NANDF_D15__GPIO3_25,
-       MX51_PAD_NANDF_D14__GPIO3_26,
-       MX51_PAD_NANDF_D13__GPIO3_27,
-       MX51_PAD_NANDF_D12__GPIO3_28,
-
-       /* USB HOST1 */
-       MX51_PAD_USBH1_CLK__USBH1_CLK,
-       MX51_PAD_USBH1_DIR__USBH1_DIR,
-       MX51_PAD_USBH1_NXT__USBH1_NXT,
-       MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-       MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-       MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-       MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-       MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-       MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-       MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-       MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-       MX51_PAD_USBH1_STP__USBH1_STP,
-};
-
-static const struct mxc_nand_platform_data
-               eukrea_cpuimx51_nand_board_info __initconst = {
-       .width          = 1,
-       .hw_ecc         = 1,
-       .flash_bbt      = 1,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const
-struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
-       .bitrate = 100000,
-};
-
-static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
-       {
-               I2C_BOARD_INFO("pcf8563", 0x51),
-       },
-};
-
-/* This function is board specific as the bit mask for the plldiv will also
-be different for other Freescale SoCs, thus a common bitmask is not
-possible and cannot get place in /plat-mxc/ehci.c.*/
-static int initialize_otg_port(struct platform_device *pdev)
-{
-       u32 v;
-       void __iomem *usb_base;
-       void __iomem *usbother_base;
-
-       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-       if (!usb_base)
-               return -ENOMEM;
-       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-       /* Set the PHY clock to 19.2MHz */
-       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-       v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-       v |= MX51_USB_PLL_DIV_19_2_MHZ;
-       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-       iounmap(usb_base);
-
-       mdelay(10);
-
-       return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
-}
-
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-       u32 v;
-       void __iomem *usb_base;
-       void __iomem *usbother_base;
-
-       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-       if (!usb_base)
-               return -ENOMEM;
-       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-       /* The clock for the USBH1 ULPI port will come externally from the PHY. */
-       v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
-       __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
-       iounmap(usb_base);
-
-       mdelay(10);
-
-       return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
-                       MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-       .init           = initialize_otg_port,
-       .portsc = MXC_EHCI_UTMI_16BIT,
-};
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
-       .operating_mode = FSL_USB2_DR_DEVICE,
-       .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
-};
-
-static const struct mxc_usbh_platform_data usbh1_config __initconst = {
-       .init           = initialize_usbh1_port,
-       .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static int otg_mode_host;
-
-static int __init eukrea_cpuimx51_otg_mode(char *options)
-{
-       if (!strcmp(options, "host"))
-               otg_mode_host = 1;
-       else if (!strcmp(options, "device"))
-               otg_mode_host = 0;
-       else
-               pr_info("otg_mode neither \"host\" nor \"device\". "
-                       "Defaulting to device\n");
-       return 0;
-}
-__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
-
-/*
- * Board specific initialization.
- */
-static void __init eukrea_cpuimx51_init(void)
-{
-       imx51_soc_init();
-
-       mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
-                                       ARRAY_SIZE(eukrea_cpuimx51_pads));
-
-       imx51_add_imx_uart(0, &uart_pdata);
-       imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
-
-       gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
-       gpio_direction_input(CPUIMX51_QUARTA_GPIO);
-       gpio_free(CPUIMX51_QUARTA_GPIO);
-       gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
-       gpio_direction_input(CPUIMX51_QUARTB_GPIO);
-       gpio_free(CPUIMX51_QUARTB_GPIO);
-       gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
-       gpio_direction_input(CPUIMX51_QUARTC_GPIO);
-       gpio_free(CPUIMX51_QUARTC_GPIO);
-       gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
-       gpio_direction_input(CPUIMX51_QUARTD_GPIO);
-       gpio_free(CPUIMX51_QUARTD_GPIO);
-
-       imx51_add_fec(NULL);
-       platform_add_devices(devices, ARRAY_SIZE(devices));
-
-       imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
-       i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
-                               ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
-
-       if (otg_mode_host)
-               imx51_add_mxc_ehci_otg(&dr_utmi_config);
-       else {
-               initialize_otg_port(NULL);
-               imx51_add_fsl_usb2_udc(&usb_pdata);
-       }
-       imx51_add_mxc_ehci_hs(1, &usbh1_config);
-
-#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
-       eukrea_mbimx51_baseboard_init();
-#endif
-}
-
-static void __init eukrea_cpuimx51_timer_init(void)
-{
-       mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mxc_timer = {
-       .init   = eukrea_cpuimx51_timer_init,
-};
-
-MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
-       /* Maintainer: Eric Bénard <eric@eukrea.com> */
-       .atag_offset = 0x100,
-       .map_io = mx51_map_io,
-       .init_early = imx51_init_early,
-       .init_irq = mx51_init_irq,
-       .handle_irq = imx51_handle_irq,
-       .timer = &mxc_timer,
-       .init_machine = eukrea_cpuimx51_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
deleted file mode 100644 (file)
index 52a11c1..0000000
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- *
- * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
- *
- * based on board-mx51_babbage.c which is
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/i2c/tsc2007.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/i2c-gpio.h>
-#include <linux/spi/spi.h>
-#include <linux/can/platform/mcp251x.h>
-
-#include <mach/eukrea-baseboards.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "cpu_op-mx51.h"
-
-#define USBH1_RST              IMX_GPIO_NR(2, 28)
-#define ETH_RST                        IMX_GPIO_NR(2, 31)
-#define TSC2007_IRQGPIO                IMX_GPIO_NR(3, 12)
-#define CAN_IRQGPIO            IMX_GPIO_NR(1, 1)
-#define CAN_RST                        IMX_GPIO_NR(4, 15)
-#define CAN_NCS                        IMX_GPIO_NR(4, 24)
-#define CAN_RXOBF              IMX_GPIO_NR(1, 4)
-#define CAN_RX1BF              IMX_GPIO_NR(1, 6)
-#define CAN_TXORTS             IMX_GPIO_NR(1, 7)
-#define CAN_TX1RTS             IMX_GPIO_NR(1, 8)
-#define CAN_TX2RTS             IMX_GPIO_NR(1, 9)
-#define I2C_SCL                        IMX_GPIO_NR(4, 16)
-#define I2C_SDA                        IMX_GPIO_NR(4, 17)
-
-/* USB_CTRL_1 */
-#define MX51_USB_CTRL_1_OFFSET         0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN   (1 << 25)
-
-#define        MX51_USB_PLLDIV_12_MHZ          0x00
-#define        MX51_USB_PLL_DIV_19_2_MHZ       0x01
-#define        MX51_USB_PLL_DIV_24_MHZ         0x02
-
-static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
-       /* UART1 */
-       MX51_PAD_UART1_RXD__UART1_RXD,
-       MX51_PAD_UART1_TXD__UART1_TXD,
-       MX51_PAD_UART1_RTS__UART1_RTS,
-       MX51_PAD_UART1_CTS__UART1_CTS,
-
-       /* USB HOST1 */
-       MX51_PAD_USBH1_CLK__USBH1_CLK,
-       MX51_PAD_USBH1_DIR__USBH1_DIR,
-       MX51_PAD_USBH1_NXT__USBH1_NXT,
-       MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-       MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-       MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-       MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-       MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-       MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-       MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-       MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-       MX51_PAD_USBH1_STP__USBH1_STP,
-       MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
-
-       /* FEC */
-       MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
-
-       /* HSI2C */
-       MX51_PAD_I2C1_CLK__GPIO4_16,
-       MX51_PAD_I2C1_DAT__GPIO4_17,
-
-       /* CAN */
-       MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-       MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-       MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-       MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
-       MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
-       MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
-       MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
-       MX51_PAD_GPIO1_6__GPIO1_6,
-       MX51_PAD_GPIO1_7__GPIO1_7,
-       MX51_PAD_GPIO1_8__GPIO1_8,
-       MX51_PAD_GPIO1_9__GPIO1_9,
-
-       /* Touchscreen */
-       /* IRQ */
-       NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
-                       PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                       PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct tsc2007_platform_data tsc2007_info = {
-       .model                  = 2007,
-       .x_plate_ohms           = 180,
-};
-
-static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
-       {
-               I2C_BOARD_INFO("pcf8563", 0x51),
-       }, {
-               I2C_BOARD_INFO("tsc2007", 0x49),
-               .type           = "tsc2007",
-               .platform_data  = &tsc2007_info,
-               .irq            = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
-       },
-};
-
-static const struct mxc_nand_platform_data
-               eukrea_cpuimx51sd_nand_board_info __initconst = {
-       .width          = 1,
-       .hw_ecc         = 1,
-       .flash_bbt      = 1,
-};
-
-/* This function is board specific as the bit mask for the plldiv will also
-be different for other Freescale SoCs, thus a common bitmask is not
-possible and cannot get place in /plat-mxc/ehci.c.*/
-static int initialize_otg_port(struct platform_device *pdev)
-{
-       u32 v;
-       void __iomem *usb_base;
-       void __iomem *usbother_base;
-
-       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-       if (!usb_base)
-               return -ENOMEM;
-       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-       /* Set the PHY clock to 19.2MHz */
-       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-       v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-       v |= MX51_USB_PLL_DIV_19_2_MHZ;
-       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-       iounmap(usb_base);
-
-       mdelay(10);
-
-       return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
-}
-
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-       u32 v;
-       void __iomem *usb_base;
-       void __iomem *usbother_base;
-
-       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-       if (!usb_base)
-               return -ENOMEM;
-       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-       /* The clock for the USBH1 ULPI port will come from the PHY. */
-       v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
-       __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
-                       usbother_base + MX51_USB_CTRL_1_OFFSET);
-       iounmap(usb_base);
-
-       mdelay(10);
-
-       return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
-                       MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-       .init           = initialize_otg_port,
-       .portsc = MXC_EHCI_UTMI_16BIT,
-};
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
-       .operating_mode = FSL_USB2_DR_DEVICE,
-       .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
-};
-
-static const struct mxc_usbh_platform_data usbh1_config __initconst = {
-       .init           = initialize_usbh1_port,
-       .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static int otg_mode_host;
-
-static int __init eukrea_cpuimx51sd_otg_mode(char *options)
-{
-       if (!strcmp(options, "host"))
-               otg_mode_host = 1;
-       else if (!strcmp(options, "device"))
-               otg_mode_host = 0;
-       else
-               pr_info("otg_mode neither \"host\" nor \"device\". "
-                       "Defaulting to device\n");
-       return 0;
-}
-__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
-
-static struct i2c_gpio_platform_data pdata = {
-       .sda_pin                = I2C_SDA,
-       .sda_is_open_drain      = 0,
-       .scl_pin                = I2C_SCL,
-       .scl_is_open_drain      = 0,
-       .udelay                 = 2,
-};
-
-static struct platform_device hsi2c_gpio_device = {
-       .name                   = "i2c-gpio",
-       .id                     = 0,
-       .dev.platform_data      = &pdata,
-};
-
-static struct mcp251x_platform_data mcp251x_info = {
-       .oscillator_frequency = 24E6,
-};
-
-static struct spi_board_info cpuimx51sd_spi_device[] = {
-       {
-               .modalias        = "mcp2515",
-               .max_speed_hz    = 10000000,
-               .bus_num         = 0,
-               .mode           = SPI_MODE_0,
-               .chip_select     = 0,
-               .platform_data   = &mcp251x_info,
-               .irq             = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
-       },
-};
-
-static int cpuimx51sd_spi1_cs[] = {
-       CAN_NCS,
-};
-
-static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
-       .chipselect     = cpuimx51sd_spi1_cs,
-       .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
-};
-
-static struct platform_device *platform_devices[] __initdata = {
-       &hsi2c_gpio_device,
-};
-
-static void __init eukrea_cpuimx51sd_init(void)
-{
-       imx51_soc_init();
-
-       mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
-                                       ARRAY_SIZE(eukrea_cpuimx51sd_pads));
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-       get_cpu_op = mx51_get_cpu_op;
-#endif
-
-       imx51_add_imx_uart(0, &uart_pdata);
-       imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
-
-       gpio_request(ETH_RST, "eth_rst");
-       gpio_set_value(ETH_RST, 1);
-       imx51_add_fec(NULL);
-
-       gpio_request(CAN_IRQGPIO, "can_irq");
-       gpio_direction_input(CAN_IRQGPIO);
-       gpio_free(CAN_IRQGPIO);
-       gpio_request(CAN_NCS, "can_ncs");
-       gpio_direction_output(CAN_NCS, 1);
-       gpio_free(CAN_NCS);
-       gpio_request(CAN_RST, "can_rst");
-       gpio_direction_output(CAN_RST, 0);
-       msleep(20);
-       gpio_set_value(CAN_RST, 1);
-       imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
-       spi_register_board_info(cpuimx51sd_spi_device,
-                               ARRAY_SIZE(cpuimx51sd_spi_device));
-
-       gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
-       gpio_direction_input(TSC2007_IRQGPIO);
-       gpio_free(TSC2007_IRQGPIO);
-
-       i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
-                       ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
-       platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
-       if (otg_mode_host)
-               imx51_add_mxc_ehci_otg(&dr_utmi_config);
-       else {
-               initialize_otg_port(NULL);
-               imx51_add_fsl_usb2_udc(&usb_pdata);
-       }
-
-       gpio_request(USBH1_RST, "usb_rst");
-       gpio_direction_output(USBH1_RST, 0);
-       msleep(20);
-       gpio_set_value(USBH1_RST, 1);
-       imx51_add_mxc_ehci_hs(1, &usbh1_config);
-
-#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
-       eukrea_mbimxsd51_baseboard_init();
-#endif
-}
-
-static void __init eukrea_cpuimx51sd_timer_init(void)
-{
-       mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mxc_timer = {
-       .init   = eukrea_cpuimx51sd_timer_init,
-};
-
-MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
-       /* Maintainer: Eric Bénard <eric@eukrea.com> */
-       .atag_offset = 0x100,
-       .map_io = mx51_map_io,
-       .init_early = imx51_init_early,
-       .init_irq = mx51_init_irq,
-       .handle_irq = imx51_handle_irq,
-       .timer = &mxc_timer,
-       .init_machine = eukrea_cpuimx51sd_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
deleted file mode 100644 (file)
index fc3621d..0000000
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx50.h>
-
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx50.h"
-
-#define FEC_EN         IMX_GPIO_NR(6, 23)
-#define FEC_RESET_B    IMX_GPIO_NR(4, 12)
-
-static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
-       /* SD1 */
-       MX50_PAD_ECSPI2_SS0__GPIO_4_19,
-       MX50_PAD_EIM_CRE__GPIO_1_27,
-       MX50_PAD_SD1_CMD__SD1_CMD,
-
-       MX50_PAD_SD1_CLK__SD1_CLK,
-       MX50_PAD_SD1_D0__SD1_D0,
-       MX50_PAD_SD1_D1__SD1_D1,
-       MX50_PAD_SD1_D2__SD1_D2,
-       MX50_PAD_SD1_D3__SD1_D3,
-
-       /* SD2 */
-       MX50_PAD_SD2_CD__GPIO_5_17,
-       MX50_PAD_SD2_WP__GPIO_5_16,
-       MX50_PAD_SD2_CMD__SD2_CMD,
-       MX50_PAD_SD2_CLK__SD2_CLK,
-       MX50_PAD_SD2_D0__SD2_D0,
-       MX50_PAD_SD2_D1__SD2_D1,
-       MX50_PAD_SD2_D2__SD2_D2,
-       MX50_PAD_SD2_D3__SD2_D3,
-       MX50_PAD_SD2_D4__SD2_D4,
-       MX50_PAD_SD2_D5__SD2_D5,
-       MX50_PAD_SD2_D6__SD2_D6,
-       MX50_PAD_SD2_D7__SD2_D7,
-
-       /* SD3 */
-       MX50_PAD_SD3_CMD__SD3_CMD,
-       MX50_PAD_SD3_CLK__SD3_CLK,
-       MX50_PAD_SD3_D0__SD3_D0,
-       MX50_PAD_SD3_D1__SD3_D1,
-       MX50_PAD_SD3_D2__SD3_D2,
-       MX50_PAD_SD3_D3__SD3_D3,
-       MX50_PAD_SD3_D4__SD3_D4,
-       MX50_PAD_SD3_D5__SD3_D5,
-       MX50_PAD_SD3_D6__SD3_D6,
-       MX50_PAD_SD3_D7__SD3_D7,
-
-       /* PWR_INT */
-       MX50_PAD_ECSPI2_MISO__GPIO_4_18,
-
-       /* UART pad setting */
-       MX50_PAD_UART1_TXD__UART1_TXD,
-       MX50_PAD_UART1_RXD__UART1_RXD,
-       MX50_PAD_UART1_RTS__UART1_RTS,
-       MX50_PAD_UART2_TXD__UART2_TXD,
-       MX50_PAD_UART2_RXD__UART2_RXD,
-       MX50_PAD_UART2_CTS__UART2_CTS,
-       MX50_PAD_UART2_RTS__UART2_RTS,
-
-       MX50_PAD_I2C1_SCL__I2C1_SCL,
-       MX50_PAD_I2C1_SDA__I2C1_SDA,
-       MX50_PAD_I2C2_SCL__I2C2_SCL,
-       MX50_PAD_I2C2_SDA__I2C2_SDA,
-
-       MX50_PAD_EPITO__USBH1_PWR,
-       /* Need to comment below line if
-        * one needs to debug owire.
-        */
-       MX50_PAD_OWIRE__USBH1_OC,
-       /* using gpio to control otg pwr */
-       MX50_PAD_PWM2__GPIO_6_25,
-       MX50_PAD_I2C3_SCL__USBOTG_OC,
-
-       MX50_PAD_SSI_RXC__FEC_MDIO,
-       MX50_PAD_SSI_RXFS__FEC_MDC,
-       MX50_PAD_DISP_D0__FEC_TXCLK,
-       MX50_PAD_DISP_D1__FEC_RX_ER,
-       MX50_PAD_DISP_D2__FEC_RX_DV,
-       MX50_PAD_DISP_D3__FEC_RXD1,
-       MX50_PAD_DISP_D4__FEC_RXD0,
-       MX50_PAD_DISP_D5__FEC_TX_EN,
-       MX50_PAD_DISP_D6__FEC_TXD1,
-       MX50_PAD_DISP_D7__FEC_TXD0,
-       MX50_PAD_I2C3_SDA__GPIO_6_23,
-       MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
-
-       MX50_PAD_CSPI_SS0__CSPI_SS0,
-       MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
-       MX50_PAD_CSPI_MOSI__CSPI_MOSI,
-       MX50_PAD_CSPI_MISO__CSPI_MISO,
-
-       /* SGTL500_OSC_EN */
-       MX50_PAD_UART1_CTS__GPIO_6_8,
-
-       /* SGTL_AMP_SHDN */
-       MX50_PAD_UART3_RXD__GPIO_6_15,
-
-       /* Keypad */
-       MX50_PAD_KEY_COL0__KEY_COL0,
-       MX50_PAD_KEY_ROW0__KEY_ROW0,
-       MX50_PAD_KEY_COL1__KEY_COL1,
-       MX50_PAD_KEY_ROW1__KEY_ROW1,
-       MX50_PAD_KEY_COL2__KEY_COL2,
-       MX50_PAD_KEY_ROW2__KEY_ROW2,
-       MX50_PAD_KEY_COL3__KEY_COL3,
-       MX50_PAD_KEY_ROW3__KEY_ROW3,
-       MX50_PAD_EIM_DA0__KEY_COL4,
-       MX50_PAD_EIM_DA1__KEY_ROW4,
-       MX50_PAD_EIM_DA2__KEY_COL5,
-       MX50_PAD_EIM_DA3__KEY_ROW5,
-       MX50_PAD_EIM_DA4__KEY_COL6,
-       MX50_PAD_EIM_DA5__KEY_ROW6,
-       MX50_PAD_EIM_DA6__KEY_COL7,
-       MX50_PAD_EIM_DA7__KEY_ROW7,
-       /*EIM pads */
-       MX50_PAD_EIM_DA8__GPIO_1_8,
-       MX50_PAD_EIM_DA9__GPIO_1_9,
-       MX50_PAD_EIM_DA10__GPIO_1_10,
-       MX50_PAD_EIM_DA11__GPIO_1_11,
-       MX50_PAD_EIM_DA12__GPIO_1_12,
-       MX50_PAD_EIM_DA13__GPIO_1_13,
-       MX50_PAD_EIM_DA14__GPIO_1_14,
-       MX50_PAD_EIM_DA15__GPIO_1_15,
-       MX50_PAD_EIM_CS2__GPIO_1_16,
-       MX50_PAD_EIM_CS1__GPIO_1_17,
-       MX50_PAD_EIM_CS0__GPIO_1_18,
-       MX50_PAD_EIM_EB0__GPIO_1_19,
-       MX50_PAD_EIM_EB1__GPIO_1_20,
-       MX50_PAD_EIM_WAIT__GPIO_1_21,
-       MX50_PAD_EIM_BCLK__GPIO_1_22,
-       MX50_PAD_EIM_RDY__GPIO_1_23,
-       MX50_PAD_EIM_OE__GPIO_1_24,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata __initconst = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct fec_platform_data fec_data __initconst = {
-       .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static inline void mx50_rdp_fec_reset(void)
-{
-       gpio_request(FEC_EN, "fec-en");
-       gpio_direction_output(FEC_EN, 0);
-       gpio_request(FEC_RESET_B, "fec-reset_b");
-       gpio_direction_output(FEC_RESET_B, 0);
-       msleep(1);
-       gpio_set_value(FEC_RESET_B, 1);
-}
-
-static const struct imxi2c_platform_data i2c_data __initconst = {
-       .bitrate = 100000,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init mx50_rdp_board_init(void)
-{
-       imx50_soc_init();
-
-       mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
-                                       ARRAY_SIZE(mx50_rdp_pads));
-
-       imx50_add_imx_uart(0, &uart_pdata);
-       imx50_add_imx_uart(1, &uart_pdata);
-       mx50_rdp_fec_reset();
-       imx50_add_fec(&fec_data);
-       imx50_add_imx_i2c(0, &i2c_data);
-       imx50_add_imx_i2c(1, &i2c_data);
-       imx50_add_imx_i2c(2, &i2c_data);
-}
-
-static void __init mx50_rdp_timer_init(void)
-{
-       mx50_clocks_init(32768, 24000000, 22579200);
-}
-
-static struct sys_timer mx50_rdp_timer = {
-       .init   = mx50_rdp_timer_init,
-};
-
-MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
-       .map_io = mx50_map_io,
-       .init_early = imx50_init_early,
-       .init_irq = mx50_init_irq,
-       .handle_irq = imx50_handle_irq,
-       .timer = &mx50_rdp_timer,
-       .init_machine = mx50_rdp_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
deleted file mode 100644 (file)
index 0578390..0000000
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx51.h>
-#include <mach/3ds_debugboard.h>
-
-#include "devices-imx51.h"
-
-#define EXPIO_PARENT_INT       gpio_to_irq(IMX_GPIO_NR(1, 6))
-#define MX51_3DS_ECSPI2_CS     (GPIO_PORTC + 28)
-
-static iomux_v3_cfg_t mx51_3ds_pads[] = {
-       /* UART1 */
-       MX51_PAD_UART1_RXD__UART1_RXD,
-       MX51_PAD_UART1_TXD__UART1_TXD,
-       MX51_PAD_UART1_RTS__UART1_RTS,
-       MX51_PAD_UART1_CTS__UART1_CTS,
-
-       /* UART2 */
-       MX51_PAD_UART2_RXD__UART2_RXD,
-       MX51_PAD_UART2_TXD__UART2_TXD,
-       MX51_PAD_EIM_D25__UART2_CTS,
-       MX51_PAD_EIM_D26__UART2_RTS,
-
-       /* UART3 */
-       MX51_PAD_UART3_RXD__UART3_RXD,
-       MX51_PAD_UART3_TXD__UART3_TXD,
-       MX51_PAD_EIM_D24__UART3_CTS,
-       MX51_PAD_EIM_D27__UART3_RTS,
-
-       /* CPLD PARENT IRQ PIN */
-       MX51_PAD_GPIO1_6__GPIO1_6,
-
-       /* KPP */
-       MX51_PAD_KEY_ROW0__KEY_ROW0,
-       MX51_PAD_KEY_ROW1__KEY_ROW1,
-       MX51_PAD_KEY_ROW2__KEY_ROW2,
-       MX51_PAD_KEY_ROW3__KEY_ROW3,
-       MX51_PAD_KEY_COL0__KEY_COL0,
-       MX51_PAD_KEY_COL1__KEY_COL1,
-       MX51_PAD_KEY_COL2__KEY_COL2,
-       MX51_PAD_KEY_COL3__KEY_COL3,
-       MX51_PAD_KEY_COL4__KEY_COL4,
-       MX51_PAD_KEY_COL5__KEY_COL5,
-
-       /* eCSPI2 */
-       MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
-       MX51_PAD_NANDF_RB3__ECSPI2_MISO,
-       MX51_PAD_NANDF_D15__ECSPI2_MOSI,
-       MX51_PAD_NANDF_D12__GPIO3_28,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata __initconst = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static int mx51_3ds_board_keymap[] = {
-       KEY(0, 0, KEY_1),
-       KEY(0, 1, KEY_2),
-       KEY(0, 2, KEY_3),
-       KEY(0, 3, KEY_F1),
-       KEY(0, 4, KEY_UP),
-       KEY(0, 5, KEY_F2),
-
-       KEY(1, 0, KEY_4),
-       KEY(1, 1, KEY_5),
-       KEY(1, 2, KEY_6),
-       KEY(1, 3, KEY_LEFT),
-       KEY(1, 4, KEY_SELECT),
-       KEY(1, 5, KEY_RIGHT),
-
-       KEY(2, 0, KEY_7),
-       KEY(2, 1, KEY_8),
-       KEY(2, 2, KEY_9),
-       KEY(2, 3, KEY_F3),
-       KEY(2, 4, KEY_DOWN),
-       KEY(2, 5, KEY_F4),
-
-       KEY(3, 0, KEY_0),
-       KEY(3, 1, KEY_OK),
-       KEY(3, 2, KEY_ESC),
-       KEY(3, 3, KEY_ENTER),
-       KEY(3, 4, KEY_MENU),
-       KEY(3, 5, KEY_BACK)
-};
-
-static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
-       .keymap         = mx51_3ds_board_keymap,
-       .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
-};
-
-static int mx51_3ds_spi2_cs[] = {
-       MXC_SPI_CS(0),
-       MX51_3DS_ECSPI2_CS,
-};
-
-static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
-       .chipselect     = mx51_3ds_spi2_cs,
-       .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
-};
-
-static struct spi_board_info mx51_3ds_spi_nor_device[] = {
-       {
-        .modalias = "m25p80",
-        .max_speed_hz = 25000000,      /* max spi clock (SCK) speed in HZ */
-        .bus_num = 1,
-        .chip_select = 1,
-        .mode = SPI_MODE_0,
-        .platform_data = NULL,},
-};
-
-/*
- * Board specific initialization.
- */
-static void __init mx51_3ds_init(void)
-{
-       imx51_soc_init();
-
-       mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
-                                       ARRAY_SIZE(mx51_3ds_pads));
-
-       imx51_add_imx_uart(0, &uart_pdata);
-       imx51_add_imx_uart(1, &uart_pdata);
-       imx51_add_imx_uart(2, &uart_pdata);
-
-       imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
-       spi_register_board_info(mx51_3ds_spi_nor_device,
-                               ARRAY_SIZE(mx51_3ds_spi_nor_device));
-
-       if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
-               printk(KERN_WARNING "Init of the debugboard failed, all "
-                                   "devices on the board are unusable.\n");
-
-       imx51_add_sdhci_esdhc_imx(0, NULL);
-       imx51_add_imx_keypad(&mx51_3ds_map_data);
-       imx51_add_imx2_wdt(0, NULL);
-}
-
-static void __init mx51_3ds_timer_init(void)
-{
-       mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx51_3ds_timer = {
-       .init = mx51_3ds_timer_init,
-};
-
-MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
-       /* Maintainer: Freescale Semiconductor, Inc. */
-       .atag_offset = 0x100,
-       .map_io = mx51_map_io,
-       .init_early = imx51_init_early,
-       .init_irq = mx51_init_irq,
-       .handle_irq = imx51_handle_irq,
-       .timer = &mx51_3ds_timer,
-       .init_machine = mx51_3ds_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
deleted file mode 100644 (file)
index 5c83760..0000000
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "cpu_op-mx51.h"
-
-#define BABBAGE_USB_HUB_RESET  IMX_GPIO_NR(1, 7)
-#define BABBAGE_USBH1_STP      IMX_GPIO_NR(1, 27)
-#define BABBAGE_USB_PHY_RESET  IMX_GPIO_NR(2, 5)
-#define BABBAGE_FEC_PHY_RESET  IMX_GPIO_NR(2, 14)
-#define BABBAGE_POWER_KEY      IMX_GPIO_NR(2, 21)
-#define BABBAGE_ECSPI1_CS0     IMX_GPIO_NR(4, 24)
-#define BABBAGE_ECSPI1_CS1     IMX_GPIO_NR(4, 25)
-#define BABBAGE_SD2_CD         IMX_GPIO_NR(1, 6)
-#define BABBAGE_SD2_WP         IMX_GPIO_NR(1, 5)
-
-/* USB_CTRL_1 */
-#define MX51_USB_CTRL_1_OFFSET                 0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN           (1 << 25)
-
-#define        MX51_USB_PLLDIV_12_MHZ          0x00
-#define        MX51_USB_PLL_DIV_19_2_MHZ       0x01
-#define        MX51_USB_PLL_DIV_24_MHZ 0x02
-
-static struct gpio_keys_button babbage_buttons[] = {
-       {
-               .gpio           = BABBAGE_POWER_KEY,
-               .code           = BTN_0,
-               .desc           = "PWR",
-               .active_low     = 1,
-               .wakeup         = 1,
-       },
-};
-
-static const struct gpio_keys_platform_data imx_button_data __initconst = {
-       .buttons        = babbage_buttons,
-       .nbuttons       = ARRAY_SIZE(babbage_buttons),
-};
-
-static iomux_v3_cfg_t mx51babbage_pads[] = {
-       /* UART1 */
-       MX51_PAD_UART1_RXD__UART1_RXD,
-       MX51_PAD_UART1_TXD__UART1_TXD,
-       MX51_PAD_UART1_RTS__UART1_RTS,
-       MX51_PAD_UART1_CTS__UART1_CTS,
-
-       /* UART2 */
-       MX51_PAD_UART2_RXD__UART2_RXD,
-       MX51_PAD_UART2_TXD__UART2_TXD,
-
-       /* UART3 */
-       MX51_PAD_EIM_D25__UART3_RXD,
-       MX51_PAD_EIM_D26__UART3_TXD,
-       MX51_PAD_EIM_D27__UART3_RTS,
-       MX51_PAD_EIM_D24__UART3_CTS,
-
-       /* I2C1 */
-       MX51_PAD_EIM_D16__I2C1_SDA,
-       MX51_PAD_EIM_D19__I2C1_SCL,
-
-       /* I2C2 */
-       MX51_PAD_KEY_COL4__I2C2_SCL,
-       MX51_PAD_KEY_COL5__I2C2_SDA,
-
-       /* HSI2C */
-       MX51_PAD_I2C1_CLK__I2C1_CLK,
-       MX51_PAD_I2C1_DAT__I2C1_DAT,
-
-       /* USB HOST1 */
-       MX51_PAD_USBH1_CLK__USBH1_CLK,
-       MX51_PAD_USBH1_DIR__USBH1_DIR,
-       MX51_PAD_USBH1_NXT__USBH1_NXT,
-       MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-       MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-       MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-       MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-       MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-       MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-       MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-       MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-
-       /* USB HUB reset line*/
-       MX51_PAD_GPIO1_7__GPIO1_7,
-
-       /* USB PHY reset line */
-       MX51_PAD_EIM_D21__GPIO2_5,
-
-       /* FEC */
-       MX51_PAD_EIM_EB2__FEC_MDIO,
-       MX51_PAD_EIM_EB3__FEC_RDATA1,
-       MX51_PAD_EIM_CS2__FEC_RDATA2,
-       MX51_PAD_EIM_CS3__FEC_RDATA3,
-       MX51_PAD_EIM_CS4__FEC_RX_ER,
-       MX51_PAD_EIM_CS5__FEC_CRS,
-       MX51_PAD_NANDF_RB2__FEC_COL,
-       MX51_PAD_NANDF_RB3__FEC_RX_CLK,
-       MX51_PAD_NANDF_D9__FEC_RDATA0,
-       MX51_PAD_NANDF_D8__FEC_TDATA0,
-       MX51_PAD_NANDF_CS2__FEC_TX_ER,
-       MX51_PAD_NANDF_CS3__FEC_MDC,
-       MX51_PAD_NANDF_CS4__FEC_TDATA1,
-       MX51_PAD_NANDF_CS5__FEC_TDATA2,
-       MX51_PAD_NANDF_CS6__FEC_TDATA3,
-       MX51_PAD_NANDF_CS7__FEC_TX_EN,
-       MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
-
-       /* FEC PHY reset line */
-       MX51_PAD_EIM_A20__GPIO2_14,
-
-       /* SD 1 */
-       MX51_PAD_SD1_CMD__SD1_CMD,
-       MX51_PAD_SD1_CLK__SD1_CLK,
-       MX51_PAD_SD1_DATA0__SD1_DATA0,
-       MX51_PAD_SD1_DATA1__SD1_DATA1,
-       MX51_PAD_SD1_DATA2__SD1_DATA2,
-       MX51_PAD_SD1_DATA3__SD1_DATA3,
-       /* CD/WP from controller */
-       MX51_PAD_GPIO1_0__SD1_CD,
-       MX51_PAD_GPIO1_1__SD1_WP,
-
-       /* SD 2 */
-       MX51_PAD_SD2_CMD__SD2_CMD,
-       MX51_PAD_SD2_CLK__SD2_CLK,
-       MX51_PAD_SD2_DATA0__SD2_DATA0,
-       MX51_PAD_SD2_DATA1__SD2_DATA1,
-       MX51_PAD_SD2_DATA2__SD2_DATA2,
-       MX51_PAD_SD2_DATA3__SD2_DATA3,
-       /* CD/WP gpio */
-       MX51_PAD_GPIO1_6__GPIO1_6,
-       MX51_PAD_GPIO1_5__GPIO1_5,
-
-       /* eCSPI1 */
-       MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-       MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-       MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-       MX51_PAD_CSPI1_SS0__GPIO4_24,
-       MX51_PAD_CSPI1_SS1__GPIO4_25,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata __initconst = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
-       .bitrate = 100000,
-};
-
-static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
-       .bitrate = 400000,
-};
-
-static struct gpio mx51_babbage_usbh1_gpios[] = {
-       { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
-       { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
-};
-
-static int gpio_usbh1_active(void)
-{
-       iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
-       int ret;
-
-       /* Set USBH1_STP to GPIO and toggle it */
-       mxc_iomux_v3_setup_pad(usbh1stp_gpio);
-       ret = gpio_request_array(mx51_babbage_usbh1_gpios,
-                                       ARRAY_SIZE(mx51_babbage_usbh1_gpios));
-
-       if (ret) {
-               pr_debug("failed to get USBH1 pins: %d\n", ret);
-               return ret;
-       }
-
-       msleep(100);
-       gpio_set_value(BABBAGE_USBH1_STP, 1);
-       gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
-       gpio_free_array(mx51_babbage_usbh1_gpios,
-                                       ARRAY_SIZE(mx51_babbage_usbh1_gpios));
-       return 0;
-}
-
-static inline void babbage_usbhub_reset(void)
-{
-       int ret;
-
-       /* Reset USB hub */
-       ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
-                                       GPIOF_OUT_INIT_LOW, "GPIO1_7");
-       if (ret) {
-               printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
-               return;
-       }
-
-       msleep(2);
-       /* Deassert reset */
-       gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
-}
-
-static inline void babbage_fec_reset(void)
-{
-       int ret;
-
-       /* reset FEC PHY */
-       ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
-                                       GPIOF_OUT_INIT_LOW, "fec-phy-reset");
-       if (ret) {
-               printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-               return;
-       }
-       msleep(1);
-       gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
-}
-
-/* This function is board specific as the bit mask for the plldiv will also
-be different for other Freescale SoCs, thus a common bitmask is not
-possible and cannot get place in /plat-mxc/ehci.c.*/
-static int initialize_otg_port(struct platform_device *pdev)
-{
-       u32 v;
-       void __iomem *usb_base;
-       void __iomem *usbother_base;
-
-       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-       if (!usb_base)
-               return -ENOMEM;
-       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-       /* Set the PHY clock to 19.2MHz */
-       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-       v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-       v |= MX51_USB_PLL_DIV_19_2_MHZ;
-       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-       iounmap(usb_base);
-
-       mdelay(10);
-
-       return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
-}
-
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-       u32 v;
-       void __iomem *usb_base;
-       void __iomem *usbother_base;
-
-       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-       if (!usb_base)
-               return -ENOMEM;
-       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-       /* The clock for the USBH1 ULPI port will come externally from the PHY. */
-       v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
-       __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
-       iounmap(usb_base);
-
-       mdelay(10);
-
-       return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
-                       MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-       .init           = initialize_otg_port,
-       .portsc = MXC_EHCI_UTMI_16BIT,
-};
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
-       .operating_mode = FSL_USB2_DR_DEVICE,
-       .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
-};
-
-static const struct mxc_usbh_platform_data usbh1_config __initconst = {
-       .init           = initialize_usbh1_port,
-       .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static int otg_mode_host;
-
-static int __init babbage_otg_mode(char *options)
-{
-       if (!strcmp(options, "host"))
-               otg_mode_host = 1;
-       else if (!strcmp(options, "device"))
-               otg_mode_host = 0;
-       else
-               pr_info("otg_mode neither \"host\" nor \"device\". "
-                       "Defaulting to device\n");
-       return 0;
-}
-__setup("otg_mode=", babbage_otg_mode);
-
-static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
-       {
-               .modalias = "mtd_dataflash",
-               .max_speed_hz = 25000000,
-               .bus_num = 0,
-               .chip_select = 1,
-               .mode = SPI_MODE_0,
-               .platform_data = NULL,
-       },
-};
-
-static int mx51_babbage_spi_cs[] = {
-       BABBAGE_ECSPI1_CS0,
-       BABBAGE_ECSPI1_CS1,
-};
-
-static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
-       .chipselect     = mx51_babbage_spi_cs,
-       .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
-};
-
-static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
-       .cd_type = ESDHC_CD_CONTROLLER,
-       .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
-       .cd_gpio = BABBAGE_SD2_CD,
-       .wp_gpio = BABBAGE_SD2_WP,
-       .cd_type = ESDHC_CD_GPIO,
-       .wp_type = ESDHC_WP_GPIO,
-};
-
-void __init imx51_babbage_common_init(void)
-{
-       mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
-                                        ARRAY_SIZE(mx51babbage_pads));
-}
-
-/*
- * Board specific initialization.
- */
-static void __init mx51_babbage_init(void)
-{
-       iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-       iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
-               PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
-
-       imx51_soc_init();
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-       get_cpu_op = mx51_get_cpu_op;
-#endif
-       imx51_babbage_common_init();
-
-       imx51_add_imx_uart(0, &uart_pdata);
-       imx51_add_imx_uart(1, NULL);
-       imx51_add_imx_uart(2, &uart_pdata);
-
-       babbage_fec_reset();
-       imx51_add_fec(NULL);
-
-       /* Set the PAD settings for the pwr key. */
-       mxc_iomux_v3_setup_pad(power_key);
-       imx_add_gpio_keys(&imx_button_data);
-
-       imx51_add_imx_i2c(0, &babbage_i2c_data);
-       imx51_add_imx_i2c(1, &babbage_i2c_data);
-       imx51_add_hsi2c(&babbage_hsi2c_data);
-
-       if (otg_mode_host)
-               imx51_add_mxc_ehci_otg(&dr_utmi_config);
-       else {
-               initialize_otg_port(NULL);
-               imx51_add_fsl_usb2_udc(&usb_pdata);
-       }
-
-       gpio_usbh1_active();
-       imx51_add_mxc_ehci_hs(1, &usbh1_config);
-       /* setback USBH1_STP to be function */
-       mxc_iomux_v3_setup_pad(usbh1stp);
-       babbage_usbhub_reset();
-
-       imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
-       imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
-
-       spi_register_board_info(mx51_babbage_spi_board_info,
-               ARRAY_SIZE(mx51_babbage_spi_board_info));
-       imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
-       imx51_add_imx2_wdt(0, NULL);
-}
-
-static void __init mx51_babbage_timer_init(void)
-{
-       mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx51_babbage_timer = {
-       .init = mx51_babbage_timer_init,
-};
-
-MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
-       /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
-       .atag_offset = 0x100,
-       .map_io = mx51_map_io,
-       .init_early = imx51_init_early,
-       .init_irq = mx51_init_irq,
-       .handle_irq = imx51_handle_irq,
-       .timer = &mx51_babbage_timer,
-       .init_machine = mx51_babbage_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
deleted file mode 100644 (file)
index a9e4866..0000000
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * Copyright (C) 2010 Linaro Limited
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-
-#define EFIKAMX_PCBID0         IMX_GPIO_NR(3, 16)
-#define EFIKAMX_PCBID1         IMX_GPIO_NR(3, 17)
-#define EFIKAMX_PCBID2         IMX_GPIO_NR(3, 11)
-
-#define EFIKAMX_BLUE_LED       IMX_GPIO_NR(3, 13)
-#define EFIKAMX_GREEN_LED      IMX_GPIO_NR(3, 14)
-#define EFIKAMX_RED_LED                IMX_GPIO_NR(3, 15)
-
-#define EFIKAMX_POWER_KEY      IMX_GPIO_NR(2, 31)
-
-/* board 1.1 doesn't have same reset gpio */
-#define EFIKAMX_RESET1_1       IMX_GPIO_NR(3, 2)
-#define EFIKAMX_RESET          IMX_GPIO_NR(1, 4)
-
-#define EFIKAMX_POWEROFF       IMX_GPIO_NR(4, 13)
-
-#define EFIKAMX_PMIC           IMX_GPIO_NR(1, 6)
-
-/* the pci ids pin have pull up. they're driven low according to board id */
-#define MX51_PAD_PCBID0        IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID1        IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID2        IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PWRKEY        IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-
-static iomux_v3_cfg_t mx51efikamx_pads[] = {
-       /* board id */
-       MX51_PAD_PCBID0,
-       MX51_PAD_PCBID1,
-       MX51_PAD_PCBID2,
-
-       /* leds */
-       MX51_PAD_CSI1_D9__GPIO3_13,
-       MX51_PAD_CSI1_VSYNC__GPIO3_14,
-       MX51_PAD_CSI1_HSYNC__GPIO3_15,
-
-       /* power key */
-       MX51_PAD_PWRKEY,
-
-       /* reset */
-       MX51_PAD_DI1_PIN13__GPIO3_2,
-       MX51_PAD_GPIO1_4__GPIO1_4,
-
-       /* power off */
-       MX51_PAD_CSI2_VSYNC__GPIO4_13,
-};
-
-/*   PCBID2  PCBID1 PCBID0  STATE
-       1       1      1    ER1:rev1.1
-       1       1      0    ER2:rev1.2
-       1       0      1    ER3:rev1.3
-       1       0      0    ER4:rev1.4
-*/
-static void __init mx51_efikamx_board_id(void)
-{
-       int id;
-
-       /* things are taking time to settle */
-       msleep(150);
-
-       gpio_request(EFIKAMX_PCBID0, "pcbid0");
-       gpio_direction_input(EFIKAMX_PCBID0);
-       gpio_request(EFIKAMX_PCBID1, "pcbid1");
-       gpio_direction_input(EFIKAMX_PCBID1);
-       gpio_request(EFIKAMX_PCBID2, "pcbid2");
-       gpio_direction_input(EFIKAMX_PCBID2);
-
-       id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
-       id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
-       id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
-
-       switch (id) {
-       case 7:
-               system_rev = 0x11;
-               break;
-       case 6:
-               system_rev = 0x12;
-               break;
-       case 5:
-               system_rev = 0x13;
-               break;
-       case 4:
-               system_rev = 0x14;
-               break;
-       default:
-               system_rev = 0x10;
-               break;
-       }
-
-       if ((system_rev == 0x10)
-               || (system_rev == 0x12)
-               || (system_rev == 0x14)) {
-               printk(KERN_WARNING
-                       "EfikaMX: Unsupported board revision 1.%u!\n",
-                       system_rev & 0xf);
-       }
-}
-
-static struct gpio_led mx51_efikamx_leds[] __initdata = {
-       {
-               .name = "efikamx:green",
-               .default_trigger = "default-on",
-               .gpio = EFIKAMX_GREEN_LED,
-       },
-       {
-               .name = "efikamx:red",
-               .default_trigger = "ide-disk",
-               .gpio = EFIKAMX_RED_LED,
-       },
-       {
-               .name = "efikamx:blue",
-               .default_trigger = "mmc0",
-               .gpio = EFIKAMX_BLUE_LED,
-       },
-};
-
-static const struct gpio_led_platform_data
-               mx51_efikamx_leds_data __initconst = {
-       .leds = mx51_efikamx_leds,
-       .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
-};
-
-static struct esdhc_platform_data sd_pdata = {
-       .cd_type = ESDHC_CD_CONTROLLER,
-       .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct gpio_keys_button mx51_efikamx_powerkey[] = {
-       {
-               .code = KEY_POWER,
-               .gpio = EFIKAMX_POWER_KEY,
-               .type = EV_PWR,
-               .desc = "Power Button (CM)",
-               .wakeup = 1,
-               .debounce_interval = 10, /* ms */
-       },
-};
-
-static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
-       .buttons = mx51_efikamx_powerkey,
-       .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
-};
-
-void mx51_efikamx_reset(void)
-{
-       if (system_rev == 0x11)
-               gpio_direction_output(EFIKAMX_RESET1_1, 0);
-       else
-               gpio_direction_output(EFIKAMX_RESET, 0);
-}
-
-static struct regulator *pwgt1, *pwgt2, *coincell;
-
-static void mx51_efikamx_power_off(void)
-{
-       if (!IS_ERR(coincell))
-               regulator_disable(coincell);
-
-       if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-               regulator_disable(pwgt2);
-               regulator_disable(pwgt1);
-       }
-       gpio_direction_output(EFIKAMX_POWEROFF, 1);
-}
-
-static int __init mx51_efikamx_power_init(void)
-{
-       if (machine_is_mx51_efikamx()) {
-               pwgt1 = regulator_get(NULL, "pwgt1");
-               pwgt2 = regulator_get(NULL, "pwgt2");
-               if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                       regulator_enable(pwgt1);
-                       regulator_enable(pwgt2);
-               }
-               gpio_request(EFIKAMX_POWEROFF, "poweroff");
-               pm_power_off = mx51_efikamx_power_off;
-
-               /* enable coincell charger. maybe need a small power driver ? */
-               coincell = regulator_get(NULL, "coincell");
-               if (!IS_ERR(coincell)) {
-                       regulator_set_voltage(coincell, 3000000, 3000000);
-                       regulator_enable(coincell);
-               }
-
-               regulator_has_full_constraints();
-       }
-
-       return 0;
-}
-late_initcall(mx51_efikamx_power_init);
-
-static void __init mx51_efikamx_init(void)
-{
-       imx51_soc_init();
-
-       mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
-                                       ARRAY_SIZE(mx51efikamx_pads));
-       efika_board_common_init();
-
-       mx51_efikamx_board_id();
-
-       /* on < 1.2 boards both SD controllers are used */
-       if (system_rev < 0x12) {
-               imx51_add_sdhci_esdhc_imx(0, NULL);
-               imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
-               mx51_efikamx_leds[2].default_trigger = "mmc1";
-       } else
-               imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
-
-       gpio_led_register_device(-1, &mx51_efikamx_leds_data);
-       imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
-
-       if (system_rev == 0x11) {
-               gpio_request(EFIKAMX_RESET1_1, "reset");
-               gpio_direction_output(EFIKAMX_RESET1_1, 1);
-       } else {
-               gpio_request(EFIKAMX_RESET, "reset");
-               gpio_direction_output(EFIKAMX_RESET, 1);
-       }
-
-       /*
-        * enable wifi by default only on mx
-        * sb and mx have same wlan pin but the value to enable it are
-        * different :/
-        */
-       gpio_request(EFIKA_WLAN_EN, "wlan_en");
-       gpio_direction_output(EFIKA_WLAN_EN, 0);
-       msleep(10);
-
-       gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
-       gpio_direction_output(EFIKA_WLAN_RESET, 0);
-       msleep(10);
-       gpio_set_value(EFIKA_WLAN_RESET, 1);
-}
-
-static void __init mx51_efikamx_timer_init(void)
-{
-       mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-
-static struct sys_timer mx51_efikamx_timer = {
-       .init = mx51_efikamx_timer_init,
-};
-
-MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
-       /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
-       .atag_offset = 0x100,
-       .map_io = mx51_map_io,
-       .init_early = imx51_init_early,
-       .init_irq = mx51_init_irq,
-       .handle_irq = imx51_handle_irq,
-       .timer = &mx51_efikamx_timer,
-       .init_machine = mx51_efikamx_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
deleted file mode 100644 (file)
index 38c4a3e..0000000
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-
-#define EFIKASB_USBH2_STP      IMX_GPIO_NR(2, 20)
-#define EFIKASB_GREEN_LED      IMX_GPIO_NR(1, 3)
-#define EFIKASB_WHITE_LED      IMX_GPIO_NR(2, 25)
-#define EFIKASB_PCBID0         IMX_GPIO_NR(2, 28)
-#define EFIKASB_PCBID1         IMX_GPIO_NR(2, 29)
-#define EFIKASB_PWRKEY         IMX_GPIO_NR(2, 31)
-#define EFIKASB_LID            IMX_GPIO_NR(3, 14)
-#define EFIKASB_POWEROFF       IMX_GPIO_NR(4, 13)
-#define EFIKASB_RFKILL         IMX_GPIO_NR(3, 1)
-
-#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-#define MX51_PAD_SD1_CD        IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-
-static iomux_v3_cfg_t mx51efikasb_pads[] = {
-       /* USB HOST2 */
-       MX51_PAD_EIM_D16__USBH2_DATA0,
-       MX51_PAD_EIM_D17__USBH2_DATA1,
-       MX51_PAD_EIM_D18__USBH2_DATA2,
-       MX51_PAD_EIM_D19__USBH2_DATA3,
-       MX51_PAD_EIM_D20__USBH2_DATA4,
-       MX51_PAD_EIM_D21__USBH2_DATA5,
-       MX51_PAD_EIM_D22__USBH2_DATA6,
-       MX51_PAD_EIM_D23__USBH2_DATA7,
-       MX51_PAD_EIM_A24__USBH2_CLK,
-       MX51_PAD_EIM_A25__USBH2_DIR,
-       MX51_PAD_EIM_A26__USBH2_STP,
-       MX51_PAD_EIM_A27__USBH2_NXT,
-
-       /* leds */
-       MX51_PAD_EIM_CS0__GPIO2_25,
-       MX51_PAD_GPIO1_3__GPIO1_3,
-
-       /* pcb id */
-       MX51_PAD_EIM_CS3__GPIO2_28,
-       MX51_PAD_EIM_CS4__GPIO2_29,
-
-       /* lid */
-       MX51_PAD_CSI1_VSYNC__GPIO3_14,
-
-       /* power key*/
-       MX51_PAD_PWRKEY,
-
-       /* wifi/bt button */
-       MX51_PAD_DI1_PIN12__GPIO3_1,
-
-       /* power off */
-       MX51_PAD_CSI2_VSYNC__GPIO4_13,
-
-       /* wdog reset */
-       MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
-
-       /* BT */
-       MX51_PAD_EIM_A17__GPIO2_11,
-
-       MX51_PAD_SD1_CD,
-};
-
-static int initialize_usbh2_port(struct platform_device *pdev)
-{
-       iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
-       iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
-
-       mxc_iomux_v3_setup_pad(usbh2gpio);
-       gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
-       gpio_direction_output(EFIKASB_USBH2_STP, 0);
-       msleep(1);
-       gpio_set_value(EFIKASB_USBH2_STP, 1);
-       msleep(1);
-
-       gpio_free(EFIKASB_USBH2_STP);
-       mxc_iomux_v3_setup_pad(usbh2stp);
-
-       mdelay(10);
-
-       return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static struct mxc_usbh_platform_data usbh2_config __initdata = {
-       .init   = initialize_usbh2_port,
-       .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static void __init mx51_efikasb_usb(void)
-{
-       usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                       ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-       if (usbh2_config.otg)
-               imx51_add_mxc_ehci_hs(2, &usbh2_config);
-}
-
-static const struct gpio_led mx51_efikasb_leds[] __initconst = {
-       {
-               .name = "efikasb:green",
-               .default_trigger = "default-on",
-               .gpio = EFIKASB_GREEN_LED,
-               .active_low = 1,
-       },
-       {
-               .name = "efikasb:white",
-               .default_trigger = "caps",
-               .gpio = EFIKASB_WHITE_LED,
-       },
-};
-
-static const struct gpio_led_platform_data
-               mx51_efikasb_leds_data __initconst = {
-       .leds = mx51_efikasb_leds,
-       .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
-};
-
-static struct gpio_keys_button mx51_efikasb_keys[] = {
-       {
-               .code = KEY_POWER,
-               .gpio = EFIKASB_PWRKEY,
-               .type = EV_KEY,
-               .desc = "Power Button",
-               .wakeup = 1,
-               .active_low = 1,
-       },
-       {
-               .code = SW_LID,
-               .gpio = EFIKASB_LID,
-               .type = EV_SW,
-               .desc = "Lid Switch",
-               .active_low = 1,
-       },
-       {
-               .code = KEY_RFKILL,
-               .gpio = EFIKASB_RFKILL,
-               .type = EV_KEY,
-               .desc = "rfkill",
-               .active_low = 1,
-       },
-};
-
-static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
-       .buttons = mx51_efikasb_keys,
-       .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
-};
-
-static struct esdhc_platform_data sd0_pdata = {
-#define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27)
-       .cd_gpio = EFIKASB_SD1_CD,
-       .cd_type = ESDHC_CD_GPIO,
-       .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct esdhc_platform_data sd1_pdata = {
-       .cd_type = ESDHC_CD_CONTROLLER,
-       .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct regulator *pwgt1, *pwgt2;
-
-static void mx51_efikasb_power_off(void)
-{
-       gpio_set_value(EFIKA_USB_PHY_RESET, 0);
-
-       if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-               regulator_disable(pwgt2);
-               regulator_disable(pwgt1);
-       }
-       gpio_direction_output(EFIKASB_POWEROFF, 1);
-}
-
-static int __init mx51_efikasb_power_init(void)
-{
-       if (machine_is_mx51_efikasb()) {
-               pwgt1 = regulator_get(NULL, "pwgt1");
-               pwgt2 = regulator_get(NULL, "pwgt2");
-               if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                       regulator_enable(pwgt1);
-                       regulator_enable(pwgt2);
-               }
-               gpio_request(EFIKASB_POWEROFF, "poweroff");
-               pm_power_off = mx51_efikasb_power_off;
-
-               regulator_has_full_constraints();
-       }
-
-       return 0;
-}
-late_initcall(mx51_efikasb_power_init);
-
-/* 01     R1.3 board
-   10     R2.0 board */
-static void __init mx51_efikasb_board_id(void)
-{
-       int id;
-
-       gpio_request(EFIKASB_PCBID0, "pcb id0");
-       gpio_direction_input(EFIKASB_PCBID0);
-       gpio_request(EFIKASB_PCBID1, "pcb id1");
-       gpio_direction_input(EFIKASB_PCBID1);
-
-       id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
-       id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
-
-       switch (id) {
-       default:
-               break;
-       case 1:
-               system_rev = 0x13;
-               break;
-       case 2:
-               system_rev = 0x20;
-               break;
-       }
-}
-
-static void __init efikasb_board_init(void)
-{
-       imx51_soc_init();
-
-       mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
-                                       ARRAY_SIZE(mx51efikasb_pads));
-       efika_board_common_init();
-
-       mx51_efikasb_board_id();
-       mx51_efikasb_usb();
-       imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
-       imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
-
-       gpio_led_register_device(-1, &mx51_efikasb_leds_data);
-       imx_add_gpio_keys(&mx51_efikasb_keys_data);
-}
-
-static void __init mx51_efikasb_timer_init(void)
-{
-       mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-
-static struct sys_timer mx51_efikasb_timer = {
-       .init   = mx51_efikasb_timer_init,
-};
-
-MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
-       .atag_offset = 0x100,
-       .map_io = mx51_map_io,
-       .init_early = imx51_init_early,
-       .init_irq = mx51_init_irq,
-       .handle_irq = imx51_handle_irq,
-       .init_machine =  efikasb_board_init,
-       .timer = &mx51_efikasb_timer,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
deleted file mode 100644 (file)
index b88a2bc..0000000
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define ARD_ETHERNET_INT_B     IMX_GPIO_NR(2, 31)
-#define ARD_SD1_CD             IMX_GPIO_NR(1, 1)
-#define ARD_SD1_WP             IMX_GPIO_NR(1, 9)
-#define ARD_I2CPORTEXP_B       IMX_GPIO_NR(2, 3)
-#define ARD_VOLUMEDOWN         IMX_GPIO_NR(4, 0)
-#define ARD_HOME                       IMX_GPIO_NR(5, 10)
-#define ARD_BACK                       IMX_GPIO_NR(5, 11)
-#define ARD_PROG                       IMX_GPIO_NR(5, 12)
-#define ARD_VOLUMEUP           IMX_GPIO_NR(5, 13)
-
-static iomux_v3_cfg_t mx53_ard_pads[] = {
-       /* UART1 */
-       MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
-       MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
-       /* WEIM for CS1 */
-       MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
-       MX53_PAD_EIM_D16__EMI_WEIM_D_16,
-       MX53_PAD_EIM_D17__EMI_WEIM_D_17,
-       MX53_PAD_EIM_D18__EMI_WEIM_D_18,
-       MX53_PAD_EIM_D19__EMI_WEIM_D_19,
-       MX53_PAD_EIM_D20__EMI_WEIM_D_20,
-       MX53_PAD_EIM_D21__EMI_WEIM_D_21,
-       MX53_PAD_EIM_D22__EMI_WEIM_D_22,
-       MX53_PAD_EIM_D23__EMI_WEIM_D_23,
-       MX53_PAD_EIM_D24__EMI_WEIM_D_24,
-       MX53_PAD_EIM_D25__EMI_WEIM_D_25,
-       MX53_PAD_EIM_D26__EMI_WEIM_D_26,
-       MX53_PAD_EIM_D27__EMI_WEIM_D_27,
-       MX53_PAD_EIM_D28__EMI_WEIM_D_28,
-       MX53_PAD_EIM_D29__EMI_WEIM_D_29,
-       MX53_PAD_EIM_D30__EMI_WEIM_D_30,
-       MX53_PAD_EIM_D31__EMI_WEIM_D_31,
-       MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
-       MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
-       MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
-       MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
-       MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
-       MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
-       MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
-       MX53_PAD_EIM_OE__EMI_WEIM_OE,
-       MX53_PAD_EIM_RW__EMI_WEIM_RW,
-       MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
-       /* SDHC1 */
-       MX53_PAD_SD1_CMD__ESDHC1_CMD,
-       MX53_PAD_SD1_CLK__ESDHC1_CLK,
-       MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-       MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-       MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-       MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-       MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
-       MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
-       MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
-       MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
-       MX53_PAD_GPIO_1__GPIO1_1,
-       MX53_PAD_GPIO_9__GPIO1_9,
-       /* I2C2 */
-       MX53_PAD_EIM_EB2__I2C2_SCL,
-       MX53_PAD_KEY_ROW3__I2C2_SDA,
-       /* I2C3 */
-       MX53_PAD_GPIO_3__I2C3_SCL,
-       MX53_PAD_GPIO_16__I2C3_SDA,
-       /* GPIO */
-       MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
-       MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
-       MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
-       MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
-       MX53_PAD_GPIO_10__GPIO4_0,              /* vol down */
-};
-
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)   \
-{                                                      \
-       .gpio           = gpio_num,                             \
-       .type           = EV_KEY,                               \
-       .code           = ev_code,                              \
-       .active_low     = act_low,                              \
-       .desc           = "btn " descr,                 \
-       .wakeup         = wake,                                 \
-}
-
-static struct gpio_keys_button ard_buttons[] = {
-       GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
-       GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
-       GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
-       GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
-       GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-
-static const struct gpio_keys_platform_data ard_button_data __initconst = {
-       .buttons        = ard_buttons,
-       .nbuttons       = ARRAY_SIZE(ard_buttons),
-};
-
-static struct resource ard_smsc911x_resources[] = {
-       {
-               .start = MX53_CS1_64MB_BASE_ADDR,
-               .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
-               .flags = IORESOURCE_MEM,
-       },
-       {
-               .start =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
-               .end =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
-               .flags = IORESOURCE_IRQ,
-       },
-};
-
-struct smsc911x_platform_config ard_smsc911x_config = {
-       .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-       .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
-       .flags = SMSC911X_USE_32BIT,
-};
-
-static struct platform_device ard_smsc_lan9220_device = {
-       .name = "smsc911x",
-       .id = -1,
-       .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
-       .resource = ard_smsc911x_resources,
-       .dev = {
-               .platform_data = &ard_smsc911x_config,
-       },
-};
-
-static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
-       .cd_gpio = ARD_SD1_CD,
-       .wp_gpio = ARD_SD1_WP,
-};
-
-static struct imxi2c_platform_data mx53_ard_i2c2_data = {
-       .bitrate = 50000,
-};
-
-static struct imxi2c_platform_data mx53_ard_i2c3_data = {
-       .bitrate = 400000,
-};
-
-static void __init mx53_ard_io_init(void)
-{
-       gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
-       gpio_direction_input(ARD_ETHERNET_INT_B);
-
-       gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
-       gpio_direction_output(ARD_I2CPORTEXP_B, 1);
-}
-
-/* Config CS1 settings for ethernet controller */
-static int weim_cs_config(void)
-{
-       u32 reg;
-       void __iomem *weim_base, *iomuxc_base;
-
-       weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
-       if (!weim_base)
-               return -ENOMEM;
-
-       iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
-       if (!iomuxc_base)
-               return -ENOMEM;
-
-       /* CS1 timings for LAN9220 */
-       writel(0x20001, (weim_base + 0x18));
-       writel(0x0, (weim_base + 0x1C));
-       writel(0x16000202, (weim_base + 0x20));
-       writel(0x00000002, (weim_base + 0x24));
-       writel(0x16002082, (weim_base + 0x28));
-       writel(0x00000000, (weim_base + 0x2C));
-       writel(0x00000000, (weim_base + 0x90));
-
-       /* specify 64 MB on CS1 and CS0 on GPR1 */
-       reg = readl(iomuxc_base + 0x4);
-       reg &= ~0x3F;
-       reg |= 0x1B;
-       writel(reg, (iomuxc_base + 0x4));
-
-       iounmap(iomuxc_base);
-       iounmap(weim_base);
-
-       return 0;
-}
-
-void __init imx53_ard_common_init(void)
-{
-       mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
-                                        ARRAY_SIZE(mx53_ard_pads));
-       weim_cs_config();
-}
-
-static struct platform_device *devices[] __initdata = {
-       &ard_smsc_lan9220_device,
-};
-
-static void __init mx53_ard_board_init(void)
-{
-       imx53_soc_init();
-       imx53_add_imx_uart(0, NULL);
-
-       imx53_ard_common_init();
-       mx53_ard_io_init();
-       platform_add_devices(devices, ARRAY_SIZE(devices));
-
-       imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
-       imx53_add_imx2_wdt(0, NULL);
-       imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
-       imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
-       imx_add_gpio_keys(&ard_button_data);
-       imx53_add_ahci_imx();
-}
-
-static void __init mx53_ard_timer_init(void)
-{
-       mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_ard_timer = {
-       .init   = mx53_ard_timer_init,
-};
-
-MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
-       .map_io = mx53_map_io,
-       .init_early = imx53_init_early,
-       .init_irq = mx53_init_irq,
-       .handle_irq = imx53_handle_irq,
-       .timer = &mx53_ard_timer,
-       .init_machine = mx53_ard_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
deleted file mode 100644 (file)
index c69413d..0000000
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/iomux-mx53.h>
-
-#define MX53_EVK_FEC_PHY_RST   IMX_GPIO_NR(7, 6)
-#define EVK_ECSPI1_CS0         IMX_GPIO_NR(2, 30)
-#define EVK_ECSPI1_CS1         IMX_GPIO_NR(3, 19)
-#define MX53EVK_LED            IMX_GPIO_NR(7, 7)
-
-#include "devices-imx53.h"
-
-static iomux_v3_cfg_t mx53_evk_pads[] = {
-       MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-       MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-
-       MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-       MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-       MX53_PAD_PATA_DIOR__UART2_RTS,
-       MX53_PAD_PATA_INTRQ__UART2_CTS,
-
-       MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-       MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-
-       MX53_PAD_EIM_D16__ECSPI1_SCLK,
-       MX53_PAD_EIM_D17__ECSPI1_MISO,
-       MX53_PAD_EIM_D18__ECSPI1_MOSI,
-
-       /* ecspi chip select lines */
-       MX53_PAD_EIM_EB2__GPIO2_30,
-       MX53_PAD_EIM_D19__GPIO3_19,
-       /* LED */
-       MX53_PAD_PATA_DA_1__GPIO7_7,
-};
-
-static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct gpio_led mx53evk_leds[] __initconst = {
-       {
-               .name                   = "green",
-               .default_trigger        = "heartbeat",
-               .gpio                   = MX53EVK_LED,
-       },
-};
-
-static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
-       .leds           = mx53evk_leds,
-       .num_leds       = ARRAY_SIZE(mx53evk_leds),
-};
-
-static inline void mx53_evk_init_uart(void)
-{
-       imx53_add_imx_uart(0, NULL);
-       imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
-       imx53_add_imx_uart(2, NULL);
-}
-
-static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
-       .bitrate = 100000,
-};
-
-static inline void mx53_evk_fec_reset(void)
-{
-       int ret;
-
-       /* reset FEC PHY */
-       ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
-                                                       "fec-phy-reset");
-       if (ret) {
-               printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-               return;
-       }
-       msleep(1);
-       gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
-}
-
-static struct fec_platform_data mx53_evk_fec_pdata = {
-       .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
-       {
-               .modalias = "mtd_dataflash",
-               .max_speed_hz = 25000000,
-               .bus_num = 0,
-               .chip_select = 1,
-               .mode = SPI_MODE_0,
-               .platform_data = NULL,
-       },
-};
-
-static int mx53_evk_spi_cs[] = {
-       EVK_ECSPI1_CS0,
-       EVK_ECSPI1_CS1,
-};
-
-static const struct spi_imx_master mx53_evk_spi_data __initconst = {
-       .chipselect     = mx53_evk_spi_cs,
-       .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
-};
-
-void __init imx53_evk_common_init(void)
-{
-       mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
-                                        ARRAY_SIZE(mx53_evk_pads));
-}
-
-static void __init mx53_evk_board_init(void)
-{
-       imx53_soc_init();
-       imx53_evk_common_init();
-
-       mx53_evk_init_uart();
-       mx53_evk_fec_reset();
-       imx53_add_fec(&mx53_evk_fec_pdata);
-
-       imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
-       imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
-
-       imx53_add_sdhci_esdhc_imx(0, NULL);
-       imx53_add_sdhci_esdhc_imx(1, NULL);
-
-       spi_register_board_info(mx53_evk_spi_board_info,
-               ARRAY_SIZE(mx53_evk_spi_board_info));
-       imx53_add_ecspi(0, &mx53_evk_spi_data);
-       imx53_add_imx2_wdt(0, NULL);
-       gpio_led_register_device(-1, &mx53evk_leds_data);
-}
-
-static void __init mx53_evk_timer_init(void)
-{
-       mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_evk_timer = {
-       .init   = mx53_evk_timer_init,
-};
-
-MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
-       .map_io = mx53_map_io,
-       .init_early = imx53_init_early,
-       .init_irq = mx53_init_irq,
-       .handle_irq = imx53_handle_irq,
-       .timer = &mx53_evk_timer,
-       .init_machine = mx53_evk_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
deleted file mode 100644 (file)
index e64a8f7..0000000
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define MX53_LOCO_POWER                        IMX_GPIO_NR(1, 8)
-#define MX53_LOCO_UI1                  IMX_GPIO_NR(2, 14)
-#define MX53_LOCO_UI2                  IMX_GPIO_NR(2, 15)
-#define LOCO_FEC_PHY_RST               IMX_GPIO_NR(7, 6)
-#define LOCO_LED                       IMX_GPIO_NR(7, 7)
-#define LOCO_SD3_CD                    IMX_GPIO_NR(3, 11)
-#define LOCO_SD3_WP                    IMX_GPIO_NR(3, 12)
-#define LOCO_SD1_CD                    IMX_GPIO_NR(3, 13)
-#define LOCO_ACCEL_EN                  IMX_GPIO_NR(6, 14)
-
-static iomux_v3_cfg_t mx53_loco_pads[] = {
-       /* FEC */
-       MX53_PAD_FEC_MDC__FEC_MDC,
-       MX53_PAD_FEC_MDIO__FEC_MDIO,
-       MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-       MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-       MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-       MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-       MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-       MX53_PAD_FEC_TX_EN__FEC_TX_EN,
-       MX53_PAD_FEC_TXD1__FEC_TDATA_1,
-       MX53_PAD_FEC_TXD0__FEC_TDATA_0,
-       /* FEC_nRST */
-       MX53_PAD_PATA_DA_0__GPIO7_6,
-       /* FEC_nINT */
-       MX53_PAD_PATA_DATA4__GPIO2_4,
-       /* AUDMUX5 */
-       MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
-       MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
-       MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
-       MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
-       /* I2C1 */
-       MX53_PAD_CSI0_DAT8__I2C1_SDA,
-       MX53_PAD_CSI0_DAT9__I2C1_SCL,
-       MX53_PAD_NANDF_CS1__GPIO6_14,   /* Accelerometer Enable */
-       /* I2C2 */
-       MX53_PAD_KEY_COL3__I2C2_SCL,
-       MX53_PAD_KEY_ROW3__I2C2_SDA,
-       /* SD1 */
-       MX53_PAD_SD1_CMD__ESDHC1_CMD,
-       MX53_PAD_SD1_CLK__ESDHC1_CLK,
-       MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-       MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-       MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-       MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-       /* SD1_CD */
-       MX53_PAD_EIM_DA13__GPIO3_13,
-       /* SD3 */
-       MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-       MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-       MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-       MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-       MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-       MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-       MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-       MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-       MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-       MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-       /* SD3_CD */
-       MX53_PAD_EIM_DA11__GPIO3_11,
-       /* SD3_WP */
-       MX53_PAD_EIM_DA12__GPIO3_12,
-       /* VGA */
-       MX53_PAD_EIM_OE__IPU_DI1_PIN7,
-       MX53_PAD_EIM_RW__IPU_DI1_PIN8,
-       /* DISPLB */
-       MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
-       MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
-       MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
-       MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
-       /* DISP0_POWER_EN */
-       MX53_PAD_EIM_D24__GPIO3_24,
-       /* DISP0 DET INT */
-       MX53_PAD_EIM_D31__GPIO3_31,
-       /* LVDS */
-       MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
-       MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
-       MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
-       MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
-       MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
-       MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
-       MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
-       MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
-       MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
-       MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
-       /* I2C1 */
-       MX53_PAD_CSI0_DAT8__I2C1_SDA,
-       MX53_PAD_CSI0_DAT9__I2C1_SCL,
-       /* UART1 */
-       MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-       MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-       /* CSI0 */
-       MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
-       MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
-       MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
-       MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
-       MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
-       MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
-       MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
-       MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
-       MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
-       MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
-       MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
-       /* DISPLAY */
-       MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
-       MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
-       MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
-       MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
-       MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
-       MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
-       MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
-       MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
-       MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
-       MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
-       MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
-       MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
-       MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
-       MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
-       MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
-       MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
-       MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
-       MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
-       MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
-       MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
-       MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
-       MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
-       MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
-       MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
-       MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
-       MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
-       MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
-       MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
-       /* Audio CLK*/
-       MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
-       /* PWM */
-       MX53_PAD_GPIO_1__PWM2_PWMO,
-       /* SPDIF */
-       MX53_PAD_GPIO_7__SPDIF_PLOCK,
-       MX53_PAD_GPIO_17__SPDIF_OUT1,
-       /* GPIO */
-       MX53_PAD_PATA_DA_1__GPIO7_7,            /* LED */
-       MX53_PAD_PATA_DA_2__GPIO7_8,
-       MX53_PAD_PATA_DATA5__GPIO2_5,
-       MX53_PAD_PATA_DATA6__GPIO2_6,
-       MX53_PAD_PATA_DATA14__GPIO2_14,
-       MX53_PAD_PATA_DATA15__GPIO2_15,
-       MX53_PAD_PATA_INTRQ__GPIO7_2,
-       MX53_PAD_EIM_WAIT__GPIO5_0,
-       MX53_PAD_NANDF_WP_B__GPIO6_9,
-       MX53_PAD_NANDF_RB0__GPIO6_10,
-       MX53_PAD_NANDF_CS1__GPIO6_14,
-       MX53_PAD_NANDF_CS2__GPIO6_15,
-       MX53_PAD_NANDF_CS3__GPIO6_16,
-       MX53_PAD_GPIO_5__GPIO1_5,
-       MX53_PAD_GPIO_16__GPIO7_11,
-       MX53_PAD_GPIO_8__GPIO1_8,
-};
-
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)   \
-{                                                              \
-       .gpio           = gpio_num,                             \
-       .type           = EV_KEY,                               \
-       .code           = ev_code,                              \
-       .active_low     = act_low,                              \
-       .desc           = "btn " descr,                         \
-       .wakeup         = wake,                                 \
-}
-
-static struct gpio_keys_button loco_buttons[] = {
-       GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
-       GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
-       GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-
-static const struct gpio_keys_platform_data loco_button_data __initconst = {
-       .buttons        = loco_buttons,
-       .nbuttons       = ARRAY_SIZE(loco_buttons),
-};
-
-static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
-       .cd_gpio = LOCO_SD1_CD,
-       .cd_type = ESDHC_CD_GPIO,
-       .wp_type = ESDHC_WP_NONE,
-};
-
-static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
-       .cd_gpio = LOCO_SD3_CD,
-       .wp_gpio = LOCO_SD3_WP,
-       .cd_type = ESDHC_CD_GPIO,
-       .wp_type = ESDHC_WP_GPIO,
-};
-
-static inline void mx53_loco_fec_reset(void)
-{
-       int ret;
-
-       /* reset FEC PHY */
-       ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
-       if (ret) {
-               printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-               return;
-       }
-       gpio_direction_output(LOCO_FEC_PHY_RST, 0);
-       msleep(1);
-       gpio_set_value(LOCO_FEC_PHY_RST, 1);
-}
-
-static struct fec_platform_data mx53_loco_fec_data = {
-       .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
-       .bitrate = 100000,
-};
-
-static const struct gpio_led mx53loco_leds[] __initconst = {
-       {
-               .name                   = "green",
-               .default_trigger        = "heartbeat",
-               .gpio                   = LOCO_LED,
-       },
-};
-
-static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
-       .leds           = mx53loco_leds,
-       .num_leds       = ARRAY_SIZE(mx53loco_leds),
-};
-
-void __init imx53_qsb_common_init(void)
-{
-       mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
-                                        ARRAY_SIZE(mx53_loco_pads));
-}
-
-static struct i2c_board_info mx53loco_i2c_devices[] = {
-       {
-               I2C_BOARD_INFO("mma8450", 0x1C),
-       },
-};
-
-static void __init mx53_loco_board_init(void)
-{
-       int ret;
-       imx53_soc_init();
-       imx53_qsb_common_init();
-
-       imx53_add_imx_uart(0, NULL);
-       mx53_loco_fec_reset();
-       imx53_add_fec(&mx53_loco_fec_data);
-       imx53_add_imx2_wdt(0, NULL);
-
-       ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
-       if (ret)
-               pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
-
-       i2c_register_board_info(0, mx53loco_i2c_devices,
-                               ARRAY_SIZE(mx53loco_i2c_devices));
-       imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
-       imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
-       imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
-       imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
-       imx_add_gpio_keys(&loco_button_data);
-       gpio_led_register_device(-1, &mx53loco_leds_data);
-       imx53_add_ahci_imx();
-}
-
-static void __init mx53_loco_timer_init(void)
-{
-       mx53_clocks_init(32768, 24000000, 0, 0);
-}
-
-static struct sys_timer mx53_loco_timer = {
-       .init   = mx53_loco_timer_init,
-};
-
-MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
-       .map_io = mx53_map_io,
-       .init_early = imx53_init_early,
-       .init_irq = mx53_init_irq,
-       .handle_irq = imx53_handle_irq,
-       .timer = &mx53_loco_timer,
-       .init_machine = mx53_loco_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
deleted file mode 100644 (file)
index d498573..0000000
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define SMD_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
-#define MX53_SMD_SATA_PWR_EN    IMX_GPIO_NR(3, 3)
-
-static iomux_v3_cfg_t mx53_smd_pads[] = {
-       MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-       MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-
-       MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-       MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-
-       MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-       MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-       MX53_PAD_PATA_DA_1__UART3_CTS,
-       MX53_PAD_PATA_DA_2__UART3_RTS,
-       /* I2C1 */
-       MX53_PAD_CSI0_DAT8__I2C1_SDA,
-       MX53_PAD_CSI0_DAT9__I2C1_SCL,
-       /* SD1 */
-       MX53_PAD_SD1_CMD__ESDHC1_CMD,
-       MX53_PAD_SD1_CLK__ESDHC1_CLK,
-       MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-       MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-       MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-       MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-       /* SD2 */
-       MX53_PAD_SD2_CMD__ESDHC2_CMD,
-       MX53_PAD_SD2_CLK__ESDHC2_CLK,
-       MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
-       MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
-       MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
-       MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
-       /* SD3 */
-       MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-       MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-       MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-       MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-       MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-       MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-       MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-       MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-       MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-       MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-};
-
-static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static inline void mx53_smd_init_uart(void)
-{
-       imx53_add_imx_uart(0, NULL);
-       imx53_add_imx_uart(1, NULL);
-       imx53_add_imx_uart(2, &mx53_smd_uart_data);
-}
-
-static inline void mx53_smd_fec_reset(void)
-{
-       int ret;
-
-       /* reset FEC PHY */
-       ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
-       if (ret) {
-               printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-               return;
-       }
-       gpio_direction_output(SMD_FEC_PHY_RST, 0);
-       msleep(1);
-       gpio_set_value(SMD_FEC_PHY_RST, 1);
-}
-
-static struct fec_platform_data mx53_smd_fec_data = {
-       .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
-       .bitrate = 100000,
-};
-
-static inline void mx53_smd_ahci_pwr_on(void)
-{
-       int ret;
-
-       /* Enable SATA PWR */
-       ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
-                       GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
-       if (ret) {
-               pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
-               return;
-       }
-}
-
-void __init imx53_smd_common_init(void)
-{
-       mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
-                                        ARRAY_SIZE(mx53_smd_pads));
-}
-
-static void __init mx53_smd_board_init(void)
-{
-       imx53_soc_init();
-       imx53_smd_common_init();
-
-       mx53_smd_init_uart();
-       mx53_smd_fec_reset();
-       imx53_add_fec(&mx53_smd_fec_data);
-       imx53_add_imx2_wdt(0, NULL);
-       imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
-       imx53_add_sdhci_esdhc_imx(0, NULL);
-       imx53_add_sdhci_esdhc_imx(1, NULL);
-       imx53_add_sdhci_esdhc_imx(2, NULL);
-       mx53_smd_ahci_pwr_on();
-       imx53_add_ahci_imx();
-}
-
-static void __init mx53_smd_timer_init(void)
-{
-       mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_smd_timer = {
-       .init   = mx53_smd_timer_init,
-};
-
-MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
-       .map_io = mx53_map_io,
-       .init_early = imx53_init_early,
-       .init_irq = mx53_init_irq,
-       .handle_irq = imx53_handle_irq,
-       .timer = &mx53_smd_timer,
-       .init_machine = mx53_smd_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
deleted file mode 100644 (file)
index 2aacf41..0000000
+++ /dev/null
@@ -1,1673 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-
-#include <asm/div64.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/clock.h>
-
-#include "crm_regs.h"
-
-/* External clock values passed-in by the board code */
-static unsigned long external_high_reference, external_low_reference;
-static unsigned long oscillator_reference, ckih2_reference;
-
-static struct clk osc_clk;
-static struct clk pll1_main_clk;
-static struct clk pll1_sw_clk;
-static struct clk pll2_sw_clk;
-static struct clk pll3_sw_clk;
-static struct clk mx53_pll4_sw_clk;
-static struct clk lp_apm_clk;
-static struct clk periph_apm_clk;
-static struct clk ahb_clk;
-static struct clk ipg_clk;
-static struct clk usboh3_clk;
-static struct clk emi_fast_clk;
-static struct clk ipu_clk;
-static struct clk mipi_hsc1_clk;
-static struct clk esdhc1_clk;
-static struct clk esdhc2_clk;
-static struct clk esdhc3_mx53_clk;
-
-#define MAX_DPLL_WAIT_TRIES    1000 /* 1000 * udelay(1) = 1ms */
-
-/* calculate best pre and post dividers to get the required divider */
-static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
-       u32 max_pre, u32 max_post)
-{
-       if (div >= max_pre * max_post) {
-               *pre = max_pre;
-               *post = max_post;
-       } else if (div >= max_pre) {
-               u32 min_pre, temp_pre, old_err, err;
-               min_pre = DIV_ROUND_UP(div, max_post);
-               old_err = max_pre;
-               for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
-                       err = div % temp_pre;
-                       if (err == 0) {
-                               *pre = temp_pre;
-                               break;
-                       }
-                       err = temp_pre - err;
-                       if (err < old_err) {
-                               old_err = err;
-                               *pre = temp_pre;
-                       }
-               }
-               *post = DIV_ROUND_UP(div, *pre);
-       } else {
-               *pre = div;
-               *post = 1;
-       }
-}
-
-static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
-{
-       u32 reg = __raw_readl(clk->enable_reg);
-
-       reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-       reg |= mode << clk->enable_shift;
-
-       __raw_writel(reg, clk->enable_reg);
-}
-
-static int _clk_ccgr_enable(struct clk *clk)
-{
-       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
-       return 0;
-}
-
-static void _clk_ccgr_disable(struct clk *clk)
-{
-       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
-}
-
-static int _clk_ccgr_enable_inrun(struct clk *clk)
-{
-       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
-       return 0;
-}
-
-static void _clk_ccgr_disable_inwait(struct clk *clk)
-{
-       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
-}
-
-/*
- * For the 4-to-1 muxed input clock
- */
-static inline u32 _get_mux(struct clk *parent, struct clk *m0,
-                          struct clk *m1, struct clk *m2, struct clk *m3)
-{
-       if (parent == m0)
-               return 0;
-       else if (parent == m1)
-               return 1;
-       else if (parent == m2)
-               return 2;
-       else if (parent == m3)
-               return 3;
-       else
-               BUG();
-
-       return -EINVAL;
-}
-
-static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
-{
-       if (pll == &pll1_main_clk)
-               return MX51_DPLL1_BASE;
-       else if (pll == &pll2_sw_clk)
-               return MX51_DPLL2_BASE;
-       else if (pll == &pll3_sw_clk)
-               return MX51_DPLL3_BASE;
-       else
-               BUG();
-
-       return NULL;
-}
-
-static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
-{
-       if (pll == &pll1_main_clk)
-               return MX53_DPLL1_BASE;
-       else if (pll == &pll2_sw_clk)
-               return MX53_DPLL2_BASE;
-       else if (pll == &pll3_sw_clk)
-               return MX53_DPLL3_BASE;
-       else if (pll == &mx53_pll4_sw_clk)
-               return MX53_DPLL4_BASE;
-       else
-               BUG();
-
-       return NULL;
-}
-
-static inline void __iomem *_get_pll_base(struct clk *pll)
-{
-       if (cpu_is_mx51())
-               return _mx51_get_pll_base(pll);
-       else
-               return _mx53_get_pll_base(pll);
-}
-
-static unsigned long clk_pll_get_rate(struct clk *clk)
-{
-       long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
-       unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
-       void __iomem *pllbase;
-       s64 temp;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       pllbase = _get_pll_base(clk);
-
-       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
-       dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
-
-       if (pll_hfsm == 0) {
-               dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
-               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
-               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
-       } else {
-               dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
-               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
-               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
-       }
-       pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
-       mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
-       mfi = (mfi <= 5) ? 5 : mfi;
-       mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
-       mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
-       /* Sign extend to 32-bits */
-       if (mfn >= 0x04000000) {
-               mfn |= 0xFC000000;
-               mfn_abs = -mfn;
-       }
-
-       ref_clk = 2 * parent_rate;
-       if (dbl != 0)
-               ref_clk *= 2;
-
-       ref_clk /= (pdf + 1);
-       temp = (u64) ref_clk * mfn_abs;
-       do_div(temp, mfd + 1);
-       if (mfn < 0)
-               temp = -temp;
-       temp = (ref_clk * mfi) + temp;
-
-       return temp;
-}
-
-static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg;
-       void __iomem *pllbase;
-
-       long mfi, pdf, mfn, mfd = 999999;
-       s64 temp64;
-       unsigned long quad_parent_rate;
-       unsigned long pll_hfsm, dp_ctl;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       pllbase = _get_pll_base(clk);
-
-       quad_parent_rate = 4 * parent_rate;
-       pdf = mfi = -1;
-       while (++pdf < 16 && mfi < 5)
-               mfi = rate * (pdf+1) / quad_parent_rate;
-       if (mfi > 15)
-               return -EINVAL;
-       pdf--;
-
-       temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
-       do_div(temp64, quad_parent_rate/1000000);
-       mfn = (long)temp64;
-
-       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-       /* use dpdck0_2 */
-       __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
-       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
-       if (pll_hfsm == 0) {
-               reg = mfi << 4 | pdf;
-               __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
-               __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
-               __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
-       } else {
-               reg = mfi << 4 | pdf;
-               __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
-               __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
-               __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
-       }
-
-       return 0;
-}
-
-static int _clk_pll_enable(struct clk *clk)
-{
-       u32 reg;
-       void __iomem *pllbase;
-       int i = 0;
-
-       pllbase = _get_pll_base(clk);
-       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-       if (reg & MXC_PLL_DP_CTL_UPEN)
-               return 0;
-
-       reg |= MXC_PLL_DP_CTL_UPEN;
-       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-
-       /* Wait for lock */
-       do {
-               reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-               if (reg & MXC_PLL_DP_CTL_LRF)
-                       break;
-
-               udelay(1);
-       } while (++i < MAX_DPLL_WAIT_TRIES);
-
-       if (i == MAX_DPLL_WAIT_TRIES) {
-               pr_err("MX5: pll locking failed\n");
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static void _clk_pll_disable(struct clk *clk)
-{
-       u32 reg;
-       void __iomem *pllbase;
-
-       pllbase = _get_pll_base(clk);
-       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
-       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-}
-
-static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg, step;
-
-       reg = __raw_readl(MXC_CCM_CCSR);
-
-       /* When switching from pll_main_clk to a bypass clock, first select a
-        * multiplexed clock in 'step_sel', then shift the glitchless mux
-        * 'pll1_sw_clk_sel'.
-        *
-        * When switching back, do it in reverse order
-        */
-       if (parent == &pll1_main_clk) {
-               /* Switch to pll1_main_clk */
-               reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-               __raw_writel(reg, MXC_CCM_CCSR);
-               /* step_clk mux switched to lp_apm, to save power. */
-               reg = __raw_readl(MXC_CCM_CCSR);
-               reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
-               reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
-                               MXC_CCM_CCSR_STEP_SEL_OFFSET);
-       } else {
-               if (parent == &lp_apm_clk) {
-                       step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
-               } else  if (parent == &pll2_sw_clk) {
-                       step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
-               } else  if (parent == &pll3_sw_clk) {
-                       step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
-               } else
-                       return -EINVAL;
-
-               reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
-               reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
-
-               __raw_writel(reg, MXC_CCM_CCSR);
-               /* Switch to step_clk */
-               reg = __raw_readl(MXC_CCM_CCSR);
-               reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-       }
-       __raw_writel(reg, MXC_CCM_CCSR);
-       return 0;
-}
-
-static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
-{
-       u32 reg, div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       reg = __raw_readl(MXC_CCM_CCSR);
-
-       if (clk->parent == &pll2_sw_clk) {
-               div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
-                      MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
-       } else if (clk->parent == &pll3_sw_clk) {
-               div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
-                      MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
-       } else
-               div = 1;
-       return parent_rate / div;
-}
-
-static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CCSR);
-
-       if (parent == &pll2_sw_clk)
-               reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
-       else
-               reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
-
-       __raw_writel(reg, MXC_CCM_CCSR);
-       return 0;
-}
-
-static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       if (parent == &osc_clk)
-               reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
-       else
-               return -EINVAL;
-
-       __raw_writel(reg, MXC_CCM_CCSR);
-
-       return 0;
-}
-
-static unsigned long clk_cpu_get_rate(struct clk *clk)
-{
-       u32 cacrr, div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-       cacrr = __raw_readl(MXC_CCM_CACRR);
-       div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
-
-       return parent_rate / div;
-}
-
-static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg, cpu_podf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-       cpu_podf = parent_rate / rate - 1;
-       /* use post divider to change freq */
-       reg = __raw_readl(MXC_CCM_CACRR);
-       reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
-       reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
-       __raw_writel(reg, MXC_CCM_CACRR);
-
-       return 0;
-}
-
-static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg, mux;
-       int i = 0;
-
-       mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
-
-       reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
-       reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
-       __raw_writel(reg, MXC_CCM_CBCMR);
-
-       /* Wait for lock */
-       do {
-               reg = __raw_readl(MXC_CCM_CDHIPR);
-               if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
-                       break;
-
-               udelay(1);
-       } while (++i < MAX_DPLL_WAIT_TRIES);
-
-       if (i == MAX_DPLL_WAIT_TRIES) {
-               pr_err("MX5: Set parent for periph_apm clock failed\n");
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-
-       if (parent == &pll2_sw_clk)
-               reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-       else if (parent == &periph_apm_clk)
-               reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-       else
-               return -EINVAL;
-
-       __raw_writel(reg, MXC_CCM_CBCDR);
-
-       return 0;
-}
-
-static struct clk main_bus_clk = {
-       .parent = &pll2_sw_clk,
-       .set_parent = _clk_main_bus_set_parent,
-};
-
-static unsigned long clk_ahb_get_rate(struct clk *clk)
-{
-       u32 reg, div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-              MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
-       return parent_rate / div;
-}
-
-
-static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg, div;
-       unsigned long parent_rate;
-       int i = 0;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-       if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
-       reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-       __raw_writel(reg, MXC_CCM_CBCDR);
-
-       /* Wait for lock */
-       do {
-               reg = __raw_readl(MXC_CCM_CDHIPR);
-               if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
-                       break;
-
-               udelay(1);
-       } while (++i < MAX_DPLL_WAIT_TRIES);
-
-       if (i == MAX_DPLL_WAIT_TRIES) {
-               pr_err("MX5: clk_ahb_set_rate failed\n");
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static unsigned long _clk_ahb_round_rate(struct clk *clk,
-                                               unsigned long rate)
-{
-       u32 div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-       if (div > 8)
-               div = 8;
-       else if (div == 0)
-               div++;
-       return parent_rate / div;
-}
-
-
-static int _clk_max_enable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_enable(clk);
-
-       /* Handshake with MAX when LPM is entered. */
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       if (cpu_is_mx51())
-               reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-       else if (cpu_is_mx53())
-               reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-
-       return 0;
-}
-
-static void _clk_max_disable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_disable_inwait(clk);
-
-       /* No Handshake with MAX when LPM is entered as its disabled. */
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       if (cpu_is_mx51())
-               reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-       else if (cpu_is_mx53())
-               reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static unsigned long clk_ipg_get_rate(struct clk *clk)
-{
-       u32 reg, div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-              MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
-
-       return parent_rate / div;
-}
-
-static unsigned long clk_ipg_per_get_rate(struct clk *clk)
-{
-       u32 reg, prediv1, prediv2, podf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
-               /* the main_bus_clk is the one before the DVFS engine */
-               reg = __raw_readl(MXC_CCM_CBCDR);
-               prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
-                          MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
-               prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
-                          MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
-               podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
-                       MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
-               return parent_rate / (prediv1 * prediv2 * podf);
-       } else if (clk->parent == &ipg_clk)
-               return parent_rate;
-       else
-               BUG();
-}
-
-static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CBCMR);
-
-       reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
-       reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
-
-       if (parent == &ipg_clk)
-               reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
-       else if (parent == &lp_apm_clk)
-               reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
-       else if (parent != &main_bus_clk)
-               return -EINVAL;
-
-       __raw_writel(reg, MXC_CCM_CBCMR);
-
-       return 0;
-}
-
-#define clk_nfc_set_parent     NULL
-
-static unsigned long clk_nfc_get_rate(struct clk *clk)
-{
-       unsigned long rate;
-       u32 reg, div;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
-              MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
-       rate = clk_get_rate(clk->parent) / div;
-       WARN_ON(rate == 0);
-       return rate;
-}
-
-static unsigned long clk_nfc_round_rate(struct clk *clk,
-                                               unsigned long rate)
-{
-       u32 div;
-       unsigned long parent_rate = clk_get_rate(clk->parent);
-
-       if (!rate)
-               return -EINVAL;
-
-       div = parent_rate / rate;
-
-       if (parent_rate % rate)
-               div++;
-
-       if (div > 8)
-               return -EINVAL;
-
-       return parent_rate / div;
-
-}
-
-static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg, div;
-
-       div = clk_get_rate(clk->parent) / rate;
-       if (div == 0)
-               div++;
-       if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
-               return -EINVAL;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
-       reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
-       __raw_writel(reg, MXC_CCM_CBCDR);
-
-       while (__raw_readl(MXC_CCM_CDHIPR) &
-                       MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
-       }
-
-       return 0;
-}
-
-static unsigned long get_high_reference_clock_rate(struct clk *clk)
-{
-       return external_high_reference;
-}
-
-static unsigned long get_low_reference_clock_rate(struct clk *clk)
-{
-       return external_low_reference;
-}
-
-static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
-{
-       return oscillator_reference;
-}
-
-static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
-{
-       return ckih2_reference;
-}
-
-static unsigned long clk_emi_slow_get_rate(struct clk *clk)
-{
-       u32 reg, div;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
-              MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
-
-       return clk_get_rate(clk->parent) / div;
-}
-
-static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
-{
-       unsigned long rate;
-       u32 reg, div;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
-               MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
-       rate = clk_get_rate(clk->parent) / div;
-
-       return rate;
-}
-
-/* External high frequency clock */
-static struct clk ckih_clk = {
-       .get_rate = get_high_reference_clock_rate,
-};
-
-static struct clk ckih2_clk = {
-       .get_rate = get_ckih2_reference_clock_rate,
-};
-
-static struct clk osc_clk = {
-       .get_rate = get_oscillator_reference_clock_rate,
-};
-
-/* External low frequency (32kHz) clock */
-static struct clk ckil_clk = {
-       .get_rate = get_low_reference_clock_rate,
-};
-
-static struct clk pll1_main_clk = {
-       .parent = &osc_clk,
-       .get_rate = clk_pll_get_rate,
-       .enable = _clk_pll_enable,
-       .disable = _clk_pll_disable,
-};
-
-/* Clock tree block diagram (WIP):
- *     CCM: Clock Controller Module
- *
- * PLL output -> |
- *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
- * PLL bypass -> |
- *
- */
-
-/* PLL1 SW supplies to ARM core */
-static struct clk pll1_sw_clk = {
-       .parent = &pll1_main_clk,
-       .set_parent = _clk_pll1_sw_set_parent,
-       .get_rate = clk_pll1_sw_get_rate,
-};
-
-/* PLL2 SW supplies to AXI/AHB/IP buses */
-static struct clk pll2_sw_clk = {
-       .parent = &osc_clk,
-       .get_rate = clk_pll_get_rate,
-       .set_rate = _clk_pll_set_rate,
-       .set_parent = _clk_pll2_sw_set_parent,
-       .enable = _clk_pll_enable,
-       .disable = _clk_pll_disable,
-};
-
-/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
-static struct clk pll3_sw_clk = {
-       .parent = &osc_clk,
-       .set_rate = _clk_pll_set_rate,
-       .get_rate = clk_pll_get_rate,
-       .enable = _clk_pll_enable,
-       .disable = _clk_pll_disable,
-};
-
-/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
-static struct clk mx53_pll4_sw_clk = {
-       .parent = &osc_clk,
-       .set_rate = _clk_pll_set_rate,
-       .enable = _clk_pll_enable,
-       .disable = _clk_pll_disable,
-};
-
-/* Low-power Audio Playback Mode clock */
-static struct clk lp_apm_clk = {
-       .parent = &osc_clk,
-       .set_parent = _clk_lp_apm_set_parent,
-};
-
-static struct clk periph_apm_clk = {
-       .parent = &pll1_sw_clk,
-       .set_parent = _clk_periph_apm_set_parent,
-};
-
-static struct clk cpu_clk = {
-       .parent = &pll1_sw_clk,
-       .get_rate = clk_cpu_get_rate,
-       .set_rate = clk_cpu_set_rate,
-};
-
-static struct clk ahb_clk = {
-       .parent = &main_bus_clk,
-       .get_rate = clk_ahb_get_rate,
-       .set_rate = _clk_ahb_set_rate,
-       .round_rate = _clk_ahb_round_rate,
-};
-
-static struct clk iim_clk = {
-       .parent = &ipg_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
-};
-
-/* Main IP interface clock for access to registers */
-static struct clk ipg_clk = {
-       .parent = &ahb_clk,
-       .get_rate = clk_ipg_get_rate,
-};
-
-static struct clk ipg_perclk = {
-       .parent = &lp_apm_clk,
-       .get_rate = clk_ipg_per_get_rate,
-       .set_parent = _clk_ipg_per_set_parent,
-};
-
-static struct clk ahb_max_clk = {
-       .parent = &ahb_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
-       .enable = _clk_max_enable,
-       .disable = _clk_max_disable,
-};
-
-static struct clk aips_tz1_clk = {
-       .parent = &ahb_clk,
-       .secondary = &ahb_max_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable_inwait,
-};
-
-static struct clk aips_tz2_clk = {
-       .parent = &ahb_clk,
-       .secondary = &ahb_max_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable_inwait,
-};
-
-static struct clk gpc_dvfs_clk = {
-       .enable_reg = MXC_CCM_CCGR5,
-       .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable,
-};
-
-static struct clk gpt_32k_clk = {
-       .id = 0,
-       .parent = &ckil_clk,
-};
-
-static struct clk dummy_clk = {
-       .id = 0,
-};
-
-static struct clk emi_slow_clk = {
-       .parent = &pll2_sw_clk,
-       .enable_reg = MXC_CCM_CCGR5,
-       .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable_inwait,
-       .get_rate = clk_emi_slow_get_rate,
-};
-
-static int clk_ipu_enable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_enable(clk);
-
-       /* Enable handshake with IPU when certain clock rates are changed */
-       reg = __raw_readl(MXC_CCM_CCDR);
-       reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
-       __raw_writel(reg, MXC_CCM_CCDR);
-
-       /* Enable handshake with IPU when LPM is entered */
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-
-       return 0;
-}
-
-static void clk_ipu_disable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_disable(clk);
-
-       /* Disable handshake with IPU whe dividers are changed */
-       reg = __raw_readl(MXC_CCM_CCDR);
-       reg |= MXC_CCM_CCDR_IPU_HS_MASK;
-       __raw_writel(reg, MXC_CCM_CCDR);
-
-       /* Disable handshake with IPU when LPM is entered */
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static struct clk ahbmux1_clk = {
-       .parent = &ahb_clk,
-       .secondary = &ahb_max_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable_inwait,
-};
-
-static struct clk ipu_sec_clk = {
-       .parent = &emi_fast_clk,
-       .secondary = &ahbmux1_clk,
-};
-
-static struct clk ddr_hf_clk = {
-       .parent = &pll1_sw_clk,
-       .get_rate = _clk_ddr_hf_get_rate,
-};
-
-static struct clk ddr_clk = {
-       .parent = &ddr_hf_clk,
-};
-
-/* clock definitions for MIPI HSC unit which has been removed
- * from documentation, but not from hardware
- */
-static int _clk_hsc_enable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_enable(clk);
-       /* Handshake with IPU when certain clock rates are changed. */
-       reg = __raw_readl(MXC_CCM_CCDR);
-       reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
-       __raw_writel(reg, MXC_CCM_CCDR);
-
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-
-       return 0;
-}
-
-static void _clk_hsc_disable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_disable(clk);
-       /* No handshake with HSC as its not enabled. */
-       reg = __raw_readl(MXC_CCM_CCDR);
-       reg |= MXC_CCM_CCDR_HSC_HS_MASK;
-       __raw_writel(reg, MXC_CCM_CCDR);
-
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static struct clk mipi_hsp_clk = {
-       .parent = &ipu_clk,
-       .enable_reg = MXC_CCM_CCGR4,
-       .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
-       .enable = _clk_hsc_enable,
-       .disable = _clk_hsc_disable,
-       .secondary = &mipi_hsc1_clk,
-};
-
-#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)  \
-       static struct clk name = {                      \
-               .id             = i,                    \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .get_rate       = pfx##_get_rate,       \
-               .set_rate       = pfx##_set_rate,       \
-               .round_rate     = pfx##_round_rate,     \
-               .set_parent     = pfx##_set_parent,     \
-               .enable         = _clk_ccgr_enable,     \
-               .disable        = _clk_ccgr_disable,    \
-               .parent         = p,                    \
-               .secondary      = s,                    \
-       }
-
-#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s)   \
-       static struct clk name = {                      \
-               .id             = i,                    \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .get_rate       = pfx##_get_rate,       \
-               .set_rate       = pfx##_set_rate,       \
-               .set_parent     = pfx##_set_parent,     \
-               .enable         = _clk_max_enable,      \
-               .disable        = _clk_max_disable,     \
-               .parent         = p,                    \
-               .secondary      = s,                    \
-       }
-
-#define CLK_GET_RATE(name, nr, bitsname)                               \
-static unsigned long clk_##name##_get_rate(struct clk *clk)            \
-{                                                                      \
-       u32 reg, pred, podf;                                            \
-                                                                       \
-       reg = __raw_readl(MXC_CCM_CSCDR##nr);                           \
-       pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK)   \
-               >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;    \
-       podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK)   \
-               >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;    \
-                                                                       \
-       return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),             \
-                       (pred + 1) * (podf + 1));                       \
-}
-
-#define CLK_SET_PARENT(name, nr, bitsname)                             \
-static int clk_##name##_set_parent(struct clk *clk, struct clk *parent)        \
-{                                                                      \
-       u32 reg, mux;                                                   \
-                                                                       \
-       mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,              \
-                       &pll3_sw_clk, &lp_apm_clk);                     \
-       reg = __raw_readl(MXC_CCM_CSCMR##nr) &                          \
-               ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK;         \
-       reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET;  \
-       __raw_writel(reg, MXC_CCM_CSCMR##nr);                           \
-                                                                       \
-       return 0;                                                       \
-}
-
-#define CLK_SET_RATE(name, nr, bitsname)                               \
-static int clk_##name##_set_rate(struct clk *clk, unsigned long rate)  \
-{                                                                      \
-       u32 reg, div, parent_rate;                                      \
-       u32 pre = 0, post = 0;                                          \
-                                                                       \
-       parent_rate = clk_get_rate(clk->parent);                        \
-       div = parent_rate / rate;                                       \
-                                                                       \
-       if ((parent_rate / div) != rate)                                \
-               return -EINVAL;                                         \
-                                                                       \
-       __calc_pre_post_dividers(div, &pre, &post,                      \
-               (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >>      \
-               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1,  \
-               (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >>      \
-               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
-                                                                       \
-       /* Set sdhc1 clock divider */                                   \
-       reg = __raw_readl(MXC_CCM_CSCDR##nr) &                          \
-               ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK        \
-               | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK);      \
-       reg |= (post - 1) <<                                            \
-               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;       \
-       reg |= (pre - 1) <<                                             \
-               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;       \
-       __raw_writel(reg, MXC_CCM_CSCDR##nr);                           \
-                                                                       \
-       return 0;                                                       \
-}
-
-/* UART */
-CLK_GET_RATE(uart, 1, UART)
-CLK_SET_PARENT(uart, 1, UART)
-
-static struct clk uart_root_clk = {
-       .parent = &pll2_sw_clk,
-       .get_rate = clk_uart_get_rate,
-       .set_parent = clk_uart_set_parent,
-};
-
-/* USBOH3 */
-CLK_GET_RATE(usboh3, 1, USBOH3)
-CLK_SET_PARENT(usboh3, 1, USBOH3)
-
-static struct clk usboh3_clk = {
-       .parent = &pll2_sw_clk,
-       .get_rate = clk_usboh3_get_rate,
-       .set_parent = clk_usboh3_set_parent,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable,
-       .enable_reg = MXC_CCM_CCGR2,
-       .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
-};
-
-static struct clk usb_ahb_clk = {
-       .parent = &ipg_clk,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable,
-       .enable_reg = MXC_CCM_CCGR2,
-       .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
-};
-
-static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-
-       if (parent == &pll3_sw_clk)
-               reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
-
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-static struct clk usb_phy1_clk = {
-       .parent = &pll3_sw_clk,
-       .set_parent = clk_usb_phy1_set_parent,
-       .enable = _clk_ccgr_enable,
-       .enable_reg = MXC_CCM_CCGR2,
-       .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
-       .disable = _clk_ccgr_disable,
-};
-
-/* eCSPI */
-CLK_GET_RATE(ecspi, 2, CSPI)
-CLK_SET_PARENT(ecspi, 1, CSPI)
-
-static struct clk ecspi_main_clk = {
-       .parent = &pll3_sw_clk,
-       .get_rate = clk_ecspi_get_rate,
-       .set_parent = clk_ecspi_set_parent,
-};
-
-/* eSDHC */
-CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
-CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
-CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
-
-/* mx51 specific */
-CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
-CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
-CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
-
-static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1);
-       if (parent == &esdhc1_clk)
-               reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
-       else if (parent == &esdhc2_clk)
-               reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
-       else
-               return -EINVAL;
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1);
-       if (parent == &esdhc1_clk)
-               reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-       else if (parent == &esdhc2_clk)
-               reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-       else
-               return -EINVAL;
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-/* mx53 specific */
-static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1);
-       if (parent == &esdhc1_clk)
-               reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
-       else if (parent == &esdhc3_mx53_clk)
-               reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
-       else
-               return -EINVAL;
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
-CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
-CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
-
-static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1);
-       if (parent == &esdhc1_clk)
-               reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-       else if (parent == &esdhc3_mx53_clk)
-               reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-       else
-               return -EINVAL;
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)         \
-       static struct clk name = {                                      \
-               .id             = i,                                    \
-               .enable_reg     = er,                                   \
-               .enable_shift   = es,                                   \
-               .get_rate       = gr,                                   \
-               .set_rate       = sr,                                   \
-               .enable         = e,                                    \
-               .disable        = d,                                    \
-               .parent         = p,                                    \
-               .secondary      = s,                                    \
-       }
-
-#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                    \
-       DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
-
-/* Shared peripheral bus arbiter */
-DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
-       NULL,  NULL, &ipg_clk, NULL);
-
-/* UART */
-DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
-       NULL,  NULL, &ipg_clk, &aips_tz1_clk);
-DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
-       NULL,  NULL, &ipg_clk, &aips_tz1_clk);
-DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
-       NULL,  NULL, &ipg_clk, &spba_clk);
-DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
-       NULL,  NULL, &ipg_clk, &spba_clk);
-DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
-       NULL,  NULL, &ipg_clk, &spba_clk);
-DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
-DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
-DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
-DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart4_ipg_clk);
-DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart5_ipg_clk);
-
-/* GPT */
-DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
-       NULL,  NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
-       NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
-
-DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-
-/* I2C */
-DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
-       NULL, NULL, &ipg_perclk, NULL);
-DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
-       NULL, NULL, &ipg_perclk, NULL);
-DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
-       NULL, NULL, &ipg_perclk, NULL);
-
-/* FEC */
-DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
-       NULL,  NULL, &ipg_clk, NULL);
-
-/* NFC */
-DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
-       clk_nfc, &emi_slow_clk, NULL);
-
-/* SSI */
-DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
-       NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
-DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
-       NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
-DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
-       NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
-
-/* eCSPI */
-DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
-               NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
-               &ipg_clk, &spba_clk);
-DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
-               NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
-DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
-               NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
-               &ipg_clk, &aips_tz2_clk);
-DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
-               NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
-
-/* CSPI */
-DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
-               NULL, NULL, &ipg_clk, &aips_tz2_clk);
-DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
-               NULL, NULL, &ipg_clk, &cspi_ipg_clk);
-
-/* SDMA */
-DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
-               NULL, NULL, &ahb_clk, NULL);
-
-/* eSDHC */
-DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
-       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
-       clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
-DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
-       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
-       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
-       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-
-/* mx51 specific */
-DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
-       clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
-
-static struct clk esdhc3_clk = {
-       .id = 2,
-       .parent = &esdhc1_clk,
-       .set_parent = clk_esdhc3_set_parent,
-       .enable_reg = MXC_CCM_CCGR3,
-       .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
-       .enable  = _clk_max_enable,
-       .disable = _clk_max_disable,
-       .secondary = &esdhc3_ipg_clk,
-};
-static struct clk esdhc4_clk = {
-       .id = 3,
-       .parent = &esdhc1_clk,
-       .set_parent = clk_esdhc4_set_parent,
-       .enable_reg = MXC_CCM_CCGR3,
-       .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
-       .enable  = _clk_max_enable,
-       .disable = _clk_max_disable,
-       .secondary = &esdhc4_ipg_clk,
-};
-
-/* mx53 specific */
-static struct clk esdhc2_mx53_clk = {
-       .id = 2,
-       .parent = &esdhc1_clk,
-       .set_parent = clk_esdhc2_mx53_set_parent,
-       .enable_reg = MXC_CCM_CCGR3,
-       .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
-       .enable  = _clk_max_enable,
-       .disable = _clk_max_disable,
-       .secondary = &esdhc3_ipg_clk,
-};
-
-DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
-       clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
-
-static struct clk esdhc4_mx53_clk = {
-       .id = 3,
-       .parent = &esdhc1_clk,
-       .set_parent = clk_esdhc4_mx53_set_parent,
-       .enable_reg = MXC_CCM_CCGR3,
-       .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
-       .enable  = _clk_max_enable,
-       .disable = _clk_max_disable,
-       .secondary = &esdhc4_ipg_clk,
-};
-
-static struct clk sata_clk = {
-       .parent = &ipg_clk,
-       .enable = _clk_max_enable,
-       .enable_reg = MXC_CCM_CCGR4,
-       .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
-       .disable = _clk_max_disable,
-};
-
-static struct clk ahci_phy_clk = {
-       .parent = &usb_phy1_clk,
-};
-
-static struct clk ahci_dma_clk = {
-       .parent = &ahb_clk,
-};
-
-DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
-DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
-DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
-
-/* IPU */
-DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
-       NULL,  NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
-
-DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
-               NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
-               &ddr_clk, NULL);
-
-DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
-               NULL, NULL, &pll3_sw_clk, NULL);
-DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
-               NULL, NULL, &pll3_sw_clk, NULL);
-
-/* PATA */
-DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
-               NULL, NULL, &ipg_clk, &spba_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-               .dev_id = d, \
-               .con_id = n, \
-               .clk = &c,   \
-       },
-
-static struct clk_lookup mx51_lookups[] = {
-       /* i.mx51 has the i.mx21 type uart */
-       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-       /* i.mx51 has the i.mx27 type fec */
-       _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
-       _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
-       _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-       _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
-       _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
-       _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
-       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-       _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
-       /* i.mx51 has the i.mx35 type sdma */
-       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-       _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
-       _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
-       _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
-       _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
-       _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
-       /* i.mx51 has the i.mx35 type cspi */
-       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk)
-       _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
-       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
-       _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
-       _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
-       _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
-       _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
-       _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
-       _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
-       _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
-       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-};
-
-static struct clk_lookup mx53_lookups[] = {
-       /* i.mx53 has the i.mx21 type uart */
-       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-       _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
-       _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
-       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-       /* i.mx53 has the i.mx25 type fec */
-       _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
-       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-       _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
-       /* i.mx53 has the i.mx51 type ecspi */
-       _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
-       _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
-       /* i.mx53 has the i.mx25 type cspi */
-       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk)
-       _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
-       _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
-       /* i.mx53 has the i.mx35 type sdma */
-       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-       _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
-       _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
-       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-       _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
-       _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
-       _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
-};
-
-static void clk_tree_init(void)
-{
-       u32 reg;
-
-       ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
-
-       /*
-        * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
-        * 8MHz, its derived from lp_apm.
-        *
-        * FIXME: Verify if true for all boards
-        */
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
-       reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
-       reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
-       reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
-       __raw_writel(reg, MXC_CCM_CBCDR);
-}
-
-int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
-                       unsigned long ckih1, unsigned long ckih2)
-{
-       int i;
-
-       external_low_reference = ckil;
-       external_high_reference = ckih1;
-       ckih2_reference = ckih2;
-       oscillator_reference = osc;
-
-       for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
-               clkdev_add(&mx51_lookups[i]);
-
-       clk_tree_init();
-
-       clk_enable(&cpu_clk);
-       clk_enable(&main_bus_clk);
-
-       clk_enable(&iim_clk);
-       imx_print_silicon_rev("i.MX51", mx51_revision());
-       clk_disable(&iim_clk);
-
-       /* move usb_phy_clk to 24MHz */
-       clk_set_parent(&usb_phy1_clk, &osc_clk);
-
-       /* set the usboh3_clk parent to pll2_sw_clk */
-       clk_set_parent(&usboh3_clk, &pll2_sw_clk);
-
-       /* Set SDHC parents to be PLL2 */
-       clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
-       clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
-
-       /* set SDHC root clock as 166.25MHZ*/
-       clk_set_rate(&esdhc1_clk, 166250000);
-       clk_set_rate(&esdhc2_clk, 166250000);
-
-       /* System timer */
-       mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-               MX51_INT_GPT);
-       return 0;
-}
-
-int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
-                       unsigned long ckih1, unsigned long ckih2)
-{
-       int i;
-
-       external_low_reference = ckil;
-       external_high_reference = ckih1;
-       ckih2_reference = ckih2;
-       oscillator_reference = osc;
-
-       for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
-               clkdev_add(&mx53_lookups[i]);
-
-       clk_tree_init();
-
-       clk_set_parent(&uart_root_clk, &pll3_sw_clk);
-       clk_enable(&cpu_clk);
-       clk_enable(&main_bus_clk);
-
-       clk_enable(&iim_clk);
-       imx_print_silicon_rev("i.MX53", mx53_revision());
-       clk_disable(&iim_clk);
-
-       /* Set SDHC parents to be PLL2 */
-       clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
-       clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
-
-       /* set SDHC root clock as 200MHZ*/
-       clk_set_rate(&esdhc1_clk, 200000000);
-       clk_set_rate(&esdhc3_mx53_clk, 200000000);
-
-       /* System timer */
-       mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
-               MX53_INT_GPT);
-       return 0;
-}
-
-static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
-                                  unsigned long *ckih1, unsigned long *ckih2)
-{
-       struct device_node *np;
-
-       /* retrieve the freqency of fixed clocks from device tree */
-       for_each_compatible_node(np, NULL, "fixed-clock") {
-               u32 rate;
-               if (of_property_read_u32(np, "clock-frequency", &rate))
-                       continue;
-
-               if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                       *ckil = rate;
-               else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                       *osc = rate;
-               else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                       *ckih1 = rate;
-               else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
-                       *ckih2 = rate;
-       }
-}
-
-int __init mx51_clocks_init_dt(void)
-{
-       unsigned long ckil, osc, ckih1, ckih2;
-
-       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-       return mx51_clocks_init(ckil, osc, ckih1, ckih2);
-}
-
-int __init mx53_clocks_init_dt(void)
-{
-       unsigned long ckil, osc, ckih1, ckih2;
-
-       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-       return mx53_clocks_init(ckil, osc, ckih1, ckih2);
-}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
deleted file mode 100644 (file)
index 5c53282..0000000
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * This file contains the CPU initialization code.
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <mach/hardware.h>
-#include <asm/io.h>
-
-static int mx5_cpu_rev = -1;
-
-#define IIM_SREV 0x24
-#define MX50_HW_ADADIG_DIGPROG 0xB0
-
-static int get_mx51_srev(void)
-{
-       void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
-       u32 rev = readl(iim_base + IIM_SREV) & 0xff;
-
-       switch (rev) {
-       case 0x0:
-               return IMX_CHIP_REVISION_2_0;
-       case 0x10:
-               return IMX_CHIP_REVISION_3_0;
-       default:
-               return IMX_CHIP_REVISION_UNKNOWN;
-       }
-}
-
-/*
- * Returns:
- *     the silicon revision of the cpu
- *     -EINVAL - not a mx51
- */
-int mx51_revision(void)
-{
-       if (!cpu_is_mx51())
-               return -EINVAL;
-
-       if (mx5_cpu_rev == -1)
-               mx5_cpu_rev = get_mx51_srev();
-
-       return mx5_cpu_rev;
-}
-EXPORT_SYMBOL(mx51_revision);
-
-#ifdef CONFIG_NEON
-
-/*
- * All versions of the silicon before Rev. 3 have broken NEON implementations.
- * Dependent on link order - so the assumption is that vfp_init is called
- * before us.
- */
-static int __init mx51_neon_fixup(void)
-{
-       if (!cpu_is_mx51())
-               return 0;
-
-       if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
-               elf_hwcap &= ~HWCAP_NEON;
-               pr_info("Turning off NEON support, detected broken NEON implementation\n");
-       }
-       return 0;
-}
-
-late_initcall(mx51_neon_fixup);
-#endif
-
-static int get_mx53_srev(void)
-{
-       void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
-       u32 rev = readl(iim_base + IIM_SREV) & 0xff;
-
-       switch (rev) {
-       case 0x0:
-               return IMX_CHIP_REVISION_1_0;
-       case 0x2:
-               return IMX_CHIP_REVISION_2_0;
-       case 0x3:
-               return IMX_CHIP_REVISION_2_1;
-       default:
-               return IMX_CHIP_REVISION_UNKNOWN;
-       }
-}
-
-/*
- * Returns:
- *     the silicon revision of the cpu
- *     -EINVAL - not a mx53
- */
-int mx53_revision(void)
-{
-       if (!cpu_is_mx53())
-               return -EINVAL;
-
-       if (mx5_cpu_rev == -1)
-               mx5_cpu_rev = get_mx53_srev();
-
-       return mx5_cpu_rev;
-}
-EXPORT_SYMBOL(mx53_revision);
-
-static int get_mx50_srev(void)
-{
-       void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
-       u32 rev;
-
-       if (!anatop) {
-               mx5_cpu_rev = -EINVAL;
-               return 0;
-       }
-
-       rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
-       rev &= 0xff;
-
-       iounmap(anatop);
-       if (rev == 0x0)
-               return IMX_CHIP_REVISION_1_0;
-       else if (rev == 0x1)
-               return IMX_CHIP_REVISION_1_1;
-       return 0;
-}
-
-/*
- * Returns:
- *     the silicon revision of the cpu
- *     -EINVAL - not a mx50
- */
-int mx50_revision(void)
-{
-       if (!cpu_is_mx50())
-               return -EINVAL;
-
-       if (mx5_cpu_rev == -1)
-               mx5_cpu_rev = get_mx50_srev();
-
-       return mx5_cpu_rev;
-}
-EXPORT_SYMBOL(mx50_revision);
-
-static int __init post_cpu_init(void)
-{
-       unsigned int reg;
-       void __iomem *base;
-
-       if (cpu_is_mx51() || cpu_is_mx53()) {
-               if (cpu_is_mx51())
-                       base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
-               else
-                       base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
-
-               __raw_writel(0x0, base + 0x40);
-               __raw_writel(0x0, base + 0x44);
-               __raw_writel(0x0, base + 0x48);
-               __raw_writel(0x0, base + 0x4C);
-               reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-               __raw_writel(reg, base + 0x50);
-
-               if (cpu_is_mx51())
-                       base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
-               else
-                       base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
-
-               __raw_writel(0x0, base + 0x40);
-               __raw_writel(0x0, base + 0x44);
-               __raw_writel(0x0, base + 0x48);
-               __raw_writel(0x0, base + 0x4C);
-               reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-               __raw_writel(reg, base + 0x50);
-       }
-
-       return 0;
-}
-
-postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-mx5/cpu_op-mx51.c
deleted file mode 100644 (file)
index 9d34c3d..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/types.h>
-#include <mach/hardware.h>
-#include <linux/kernel.h>
-
-static struct cpu_op mx51_cpu_op[] = {
-       {
-       .cpu_rate = 160000000,},
-       {
-       .cpu_rate = 800000000,},
-};
-
-struct cpu_op *mx51_get_cpu_op(int *op)
-{
-       *op = ARRAY_SIZE(mx51_cpu_op);
-       return mx51_cpu_op;
-}
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-mx5/cpu_op-mx51.h
deleted file mode 100644 (file)
index 97477fe..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
deleted file mode 100644 (file)
index 5e11ba7..0000000
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-#define MX51_CCM_BASE          MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
-#define MX51_DPLL1_BASE                MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
-#define MX51_DPLL2_BASE                MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
-#define MX51_DPLL3_BASE                MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
-#define MX51_CORTEXA8_BASE     MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
-#define MX51_GPC_BASE          MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
-
-/*MX53*/
-#define MX53_CCM_BASE          MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
-#define MX53_DPLL1_BASE                MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
-#define MX53_DPLL2_BASE                MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
-#define MX53_DPLL3_BASE                MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-#define MX53_DPLL4_BASE                MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL                 0x00
-#define MXC_PLL_DP_CONFIG              0x04
-#define MXC_PLL_DP_OP                  0x08
-#define MXC_PLL_DP_MFD                 0x0C
-#define MXC_PLL_DP_MFN                 0x10
-#define MXC_PLL_DP_MFNMINUS            0x14
-#define MXC_PLL_DP_MFNPLUS             0x18
-#define MXC_PLL_DP_HFS_OP              0x1C
-#define MXC_PLL_DP_HFS_MFD             0x20
-#define MXC_PLL_DP_HFS_MFN             0x24
-#define MXC_PLL_DP_MFN_TOGC            0x28
-#define MXC_PLL_DP_DESTAT              0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL                0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN     0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
-#define MXC_PLL_DP_CTL_ADE             0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV     0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK        (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET      8
-#define MXC_PLL_DP_CTL_HFSM            0x80
-#define MXC_PLL_DP_CTL_PRE             0x40
-#define MXC_PLL_DP_CTL_UPEN            0x20
-#define MXC_PLL_DP_CTL_RST             0x10
-#define MXC_PLL_DP_CTL_RCP             0x8
-#define MXC_PLL_DP_CTL_PLM             0x4
-#define MXC_PLL_DP_CTL_BRM0            0x2
-#define MXC_PLL_DP_CTL_LRF             0x1
-
-#define MXC_PLL_DP_CONFIG_BIST         0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE       0x4
-#define MXC_PLL_DP_CONFIG_AREN         0x2
-#define MXC_PLL_DP_CONFIG_LDREQ                0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET       4
-#define MXC_PLL_DP_OP_MFI_MASK         (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET       0
-#define MXC_PLL_DP_OP_PDF_MASK         0xF
-
-#define MXC_PLL_DP_MFD_OFFSET          0
-#define MXC_PLL_DP_MFD_MASK            0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET          0x0
-#define MXC_PLL_DP_MFN_MASK            0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS    (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN     (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK   0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL      (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN          0x07FFFFFF
-
-/* Register addresses of CCM*/
-#define MXC_CCM_CCR            (MX51_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR           (MX51_CCM_BASE + 0x04)
-#define MXC_CCM_CSR            (MX51_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR           (MX51_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR          (MX51_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR          (MX51_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR          (MX51_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1         (MX51_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2         (MX51_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1         (MX51_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR         (MX51_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR         (MX51_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR          (MX51_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR         (MX51_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2         (MX51_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3         (MX51_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4         (MX51_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR           (MX51_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR         (MX51_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR           (MX51_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR           (MX51_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR          (MX51_CCM_BASE + 0x54)
-#define MXC_CCM_CISR           (MX51_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR           (MX51_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR          (MX51_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR           (MX51_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0          (MX51_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1          (MX51_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2          (MX51_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3          (MX51_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4          (MX51_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5          (MX51_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6          (MX51_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7          (MX51_CCM_BASE + 0x84)
-
-#define MXC_CCM_CMEOR          (MX51_CCM_BASE + 0x84)
-
-/* Define the bits in register CCR */
-#define MXC_CCM_CCR_COSC_EN            (1 << 12)
-#define MXC_CCM_CCR_FPM_MULT_MASK      (1 << 11)
-#define MXC_CCM_CCR_CAMP2_EN           (1 << 10)
-#define MXC_CCM_CCR_CAMP1_EN           (1 << 9)
-#define MXC_CCM_CCR_FPM_EN             (1 << 8)
-#define MXC_CCM_CCR_OSCNT_OFFSET       (0)
-#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
-
-/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_HSC_HS_MASK       (0x1 << 18)
-#define MXC_CCM_CCDR_IPU_HS_MASK       (0x1 << 17)
-#define MXC_CCM_CCDR_EMI_HS_MASK       (0x1 << 16)
-
-/* Define the bits in register CSR */
-#define MXC_CCM_CSR_COSR_READY (1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE  (1 << 4)
-#define MXC_CCM_CSR_CAMP2_READY        (1 << 3)
-#define MXC_CCM_CSR_CAMP1_READY        (1 << 2)
-#define MXC_CCM_CSR_FPM_READY  (1 << 1)
-#define MXC_CCM_CSR_REF_EN_B   (1 << 0)
-
-/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL                (0x1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET   (7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK     (0x3 << 7)
-#define MXC_CCM_CCSR_STEP_SEL_LP_APM      0
-#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
-#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
-#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
-#define MXC_CCM_CCSR_PLL2_PODF_OFFSET  (5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK    (0x3 << 5)
-#define MXC_CCM_CCSR_PLL3_PODF_OFFSET  (3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK    (0x3 << 3)
-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL   (1 << 2) /* 0: pll1_main_clk,
-                                                   1: step_clk */
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL   (1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL   (1 << 0)
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET  (0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK    (0x7)
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL              (0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL           (0x1 << 25)
-#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET                (30)
-#define MXC_CCM_CBCDR_DDR_HF_SEL               (0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_OFFSET          (27)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK            (0x7 << 27)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET          (22)
-#define MXC_CCM_CBCDR_EMI_PODF_MASK            (0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET                (19)
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK          (0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET                (16)
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK          (0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET          (13)
-#define MXC_CCM_CBCDR_NFC_PODF_MASK            (0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET          (10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK            (0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET          (8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK            (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET      (6)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK                (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET      (3)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK                (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET       (0)
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK         (0x7)
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET   (14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK     (0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET    (12)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK      (0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET       (10)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK         (0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET   (8)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK     (0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET   (6)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK     (0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET       (4)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK         (0x3 << 4)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET     (14)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK       (0x3 << 14)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL    (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL       (0x1 << 0)
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET         (30)
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK           (0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET         (28)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK           (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET          (26)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL                 (0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET             (24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK               (0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET           (22)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK             (0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET     (20)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK       (0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL                  (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL       (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL                  (0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET     (16)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK       (0x3 << 16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET      (16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK                (0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             (14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK               (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             (12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK               (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL                    (0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL                    (0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET          (8)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK            (0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL                     (0x1 << 7)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL                 (0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET             (4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK               (0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET            (2)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK              (0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL            (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL            (0x1)
-
-/* Define the bits in register CSCMR2 */
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)            (26+n*3)
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n)              (0x7 << (26+n*3))
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET                (24)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK          (0x3 << 24)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET                (22)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK          (0x3 << 22)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET              (20)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK                        (0x3 << 20)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET             (18)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK               (0x3 << 18)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET             (16)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK               (0x3 << 16)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET            (14)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK              (0x3 << 14)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET             (12)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK               (0x3 << 12)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET              (10)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK                        (0x3 << 10)
-#define MXC_CCM_CSCMR2_SLIMBUS_COM                     (0x1 << 9)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET          (6)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK            (0x7 << 6)
-#define MXC_CCM_CSCMR2_SPDIF1_COM                      (1 << 5)
-#define MXC_CCM_CSCMR2_SPDIF0_COM                      (1 << 4)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET           (2)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK             (0x3 << 2)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET           (0)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK             (0x3)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET    (22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK      (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET    (19)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK      (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET     (22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK       (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET     (19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK       (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET    (16)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK      (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET             (14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK               (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET    (11)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK      (0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET          (8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK            (0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          (6)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET            (3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK              (0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET            (0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET                (22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK          (0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET                (16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK          (0x3F << 16)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET            (6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK              (0x7 << 6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET            (0)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK              (0x3F)
-
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET                (22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK          (0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET                (16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK          (0x3F << 16)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET            (6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK              (0x7 << 6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET            (0)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK              (0x3F)
-
-/* Define the bits in register CDCDR */
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET              (28)
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK                        (0x7 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET           (25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK             (0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET           (19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK             (0x3F << 19)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET           (16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK             (0x7 << 16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET           (9)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK             (0x3F << 9)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET               (6)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK                 (0x7 << 6)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET              (3)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK                        (0x7 << 3)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET              (0)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK                        (0x7)
-
-/* Define the bits in register CHSCCDR */
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET            (12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK              (0x7 << 12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET            (6)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK              (0x3F << 6)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET           (3)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK             (0x7 << 3)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET           (0)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK             (0x7)
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET            (25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK              (0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET            (19)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK              (0x3F << 19)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET             (16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK               (0x7 << 16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET             (9)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK               (0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET         (6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK               (0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET             (0)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK               (0x3F)
-
-/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET           (16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK             (0x7 << 16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET           (9)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK             (0x3F << 9)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET            (6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK              (0x7 << 6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET            (0)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK              (0x3F)
-
-/* Define the bits in register CSCDR4 */
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET       (16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK         (0x7 << 16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET       (9)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK         (0x3F << 9)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET       (6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK         (0x7 << 6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET       (0)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK         (0x3F)
-
-/* Define the bits in register CDHIPR */
-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY                   (1 << 16)
-#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY             (1 << 8)
-#define MXC_CCM_CDHIPR_DDR_PODF_BUSY                   (1 << 7)
-#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY                        (1 << 6)
-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY             (1 << 5)
-#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY       (1 << 4)
-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY                   (1 << 3)
-#define MXC_CCM_CDHIPR_EMI_PODF_BUSY                   (1 << 2)
-#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY                 (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY                 (1 << 0)
-
-/* Define the bits in register CDCR */
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER            (0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET       (0)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK         (0x3)
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS                (0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS                (0x1 << 22)
-#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS               (0x1 << 21)
-#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS               (0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS       (0x1 << 20)
-#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS                (0x1 << 19)
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                (0x1 << 18)
-#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS       (0x1 << 17)
-#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS       (0x1 << 16)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN             (0x1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                (9)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK          (0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY                    (0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC              (0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS                    (0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM       (0x1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET      (3)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                (0x3 << 3)
-#define MXC_CCM_CLPCR_LPM_OFFSET               (0)
-#define MXC_CCM_CLPCR_LPM_MASK                 (0x3)
-
-/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED                   (0x1 << 25)
-#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED       (0x1 << 21)
-#define MXC_CCM_CISR_AHB_PODF_LOADED                   (0x1 << 20)
-#define MXC_CCM_CISR_EMI_PODF_LOADED                   (0x1 << 19)
-#define MXC_CCM_CISR_AXI_B_PODF_LOADED                 (0x1 << 18)
-#define MXC_CCM_CISR_AXI_A_PODF_LOADED                 (0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED                    (0x1 << 16)
-#define MXC_CCM_CISR_COSC_READY                                (0x1 << 6)
-#define MXC_CCM_CISR_CKIH2_READY                       (0x1 << 5)
-#define MXC_CCM_CISR_CKIH_READY                                (0x1 << 4)
-#define MXC_CCM_CISR_FPM_READY                         (0x1 << 3)
-#define MXC_CCM_CISR_LRF_PLL3                          (0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2                          (0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1                          (0x1)
-
-/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED              (0x1 << 25)
-#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED  (0x1 << 21)
-#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED              (0x1 << 20)
-#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED            (0x1 << 19)
-#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED            (0x1 << 18)
-#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED            (0x1 << 17)
-#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED               (0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY                   (0x1 << 5)
-#define MXC_CCM_CIMR_MASK_CKIH_READY                   (0x1 << 4)
-#define MXC_CCM_CIMR_MASK_FPM_READY                    (0x1 << 3)
-#define MXC_CCM_CIMR_MASK_LRF_PLL3                     (0x1 << 2)
-#define MXC_CCM_CIMR_MASK_LRF_PLL2                     (0x1 << 1)
-#define MXC_CCM_CIMR_MASK_LRF_PLL1                     (0x1)
-
-/* Define the bits in register CCOSR */
-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET                   (0x1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET                  (21)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK                    (0x7 << 21)
-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET                  (16)
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK                    (0x1F << 16)
-#define MXC_CCM_CCOSR_CKOL_EN                          (0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET                  (4)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK                    (0x7 << 4)
-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET                  (0)
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK                    (0xF)
-
-/* Define the bits in registers CGPR */
-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE            (0x1 << 4)
-#define MXC_CCM_CGPR_FPM_SEL                           (0x1 << 3)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET           (0)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK             (0x7)
-
-/* Define the bits in registers CCGRx */
-#define MXC_CCM_CCGRx_CG_MASK                          0x3
-#define MXC_CCM_CCGRx_MOD_OFF                          0x0
-#define MXC_CCM_CCGRx_MOD_ON                           0x3
-#define MXC_CCM_CCGRx_MOD_IDLE                         0x1
-
-#define MXC_CCM_CCGRx_CG15_MASK                                (0x3 << 30)
-#define MXC_CCM_CCGRx_CG14_MASK                                (0x3 << 28)
-#define MXC_CCM_CCGRx_CG13_MASK                                (0x3 << 26)
-#define MXC_CCM_CCGRx_CG12_MASK                                (0x3 << 24)
-#define MXC_CCM_CCGRx_CG11_MASK                                (0x3 << 22)
-#define MXC_CCM_CCGRx_CG10_MASK                                (0x3 << 20)
-#define MXC_CCM_CCGRx_CG9_MASK                         (0x3 << 18)
-#define MXC_CCM_CCGRx_CG8_MASK                         (0x3 << 16)
-#define MXC_CCM_CCGRx_CG5_MASK                         (0x3 << 10)
-#define MXC_CCM_CCGRx_CG4_MASK                         (0x3 << 8)
-#define MXC_CCM_CCGRx_CG3_MASK                         (0x3 << 6)
-#define MXC_CCM_CCGRx_CG2_MASK                         (0x3 << 4)
-#define MXC_CCM_CCGRx_CG1_MASK                         (0x3 << 2)
-#define MXC_CCM_CCGRx_CG0_MASK                         (0x3 << 0)
-
-#define MXC_CCM_CCGRx_CG15_OFFSET                      30
-#define MXC_CCM_CCGRx_CG14_OFFSET                      28
-#define MXC_CCM_CCGRx_CG13_OFFSET                      26
-#define MXC_CCM_CCGRx_CG12_OFFSET                      24
-#define MXC_CCM_CCGRx_CG11_OFFSET                      22
-#define MXC_CCM_CCGRx_CG10_OFFSET                      20
-#define MXC_CCM_CCGRx_CG9_OFFSET                       18
-#define MXC_CCM_CCGRx_CG8_OFFSET                       16
-#define MXC_CCM_CCGRx_CG7_OFFSET                       14
-#define MXC_CCM_CCGRx_CG6_OFFSET                       12
-#define MXC_CCM_CCGRx_CG5_OFFSET                       10
-#define MXC_CCM_CCGRx_CG4_OFFSET                       8
-#define MXC_CCM_CCGRx_CG3_OFFSET                       6
-#define MXC_CCM_CCGRx_CG2_OFFSET                       4
-#define MXC_CCM_CCGRx_CG1_OFFSET                       2
-#define MXC_CCM_CCGRx_CG0_OFFSET                       0
-
-#define MXC_DPTC_LP_BASE       (MX51_GPC_BASE + 0x80)
-#define MXC_DPTC_GP_BASE       (MX51_GPC_BASE + 0x100)
-#define MXC_DVFS_CORE_BASE     (MX51_GPC_BASE + 0x180)
-#define MXC_DPTC_PER_BASE      (MX51_GPC_BASE + 0x1C0)
-#define MXC_PGC_IPU_BASE       (MX51_GPC_BASE + 0x220)
-#define MXC_PGC_VPU_BASE       (MX51_GPC_BASE + 0x240)
-#define MXC_PGC_GPU_BASE       (MX51_GPC_BASE + 0x260)
-#define MXC_SRPG_NEON_BASE     (MX51_GPC_BASE + 0x280)
-#define MXC_SRPG_ARM_BASE      (MX51_GPC_BASE + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE   (MX51_GPC_BASE + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE   (MX51_GPC_BASE + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE  (MX51_GPC_BASE + 0x2E0)
-#define MXC_SRPG_EMI_BASE      (MX51_GPC_BASE + 0x300)
-
-/* CORTEXA8 platform */
-#define MXC_CORTEXA8_PLAT_PVID         (MX51_CORTEXA8_BASE + 0x0)
-#define MXC_CORTEXA8_PLAT_GPC          (MX51_CORTEXA8_BASE + 0x4)
-#define MXC_CORTEXA8_PLAT_PIC          (MX51_CORTEXA8_BASE + 0x8)
-#define MXC_CORTEXA8_PLAT_LPC          (MX51_CORTEXA8_BASE + 0xC)
-#define MXC_CORTEXA8_PLAT_NEON_LPC     (MX51_CORTEXA8_BASE + 0x10)
-#define MXC_CORTEXA8_PLAT_ICGC         (MX51_CORTEXA8_BASE + 0x14)
-#define MXC_CORTEXA8_PLAT_AMC          (MX51_CORTEXA8_BASE + 0x18)
-#define MXC_CORTEXA8_PLAT_NMC          (MX51_CORTEXA8_BASE + 0x20)
-#define MXC_CORTEXA8_PLAT_NMS          (MX51_CORTEXA8_BASE + 0x24)
-
-/* DVFS CORE */
-#define MXC_DVFSTHRS           (MXC_DVFS_CORE_BASE + 0x00)
-#define MXC_DVFSCOUN           (MXC_DVFS_CORE_BASE + 0x04)
-#define MXC_DVFSSIG1           (MXC_DVFS_CORE_BASE + 0x08)
-#define MXC_DVFSSIG0           (MXC_DVFS_CORE_BASE + 0x0C)
-#define MXC_DVFSGPC0           (MXC_DVFS_CORE_BASE + 0x10)
-#define MXC_DVFSGPC1           (MXC_DVFS_CORE_BASE + 0x14)
-#define MXC_DVFSGPBT           (MXC_DVFS_CORE_BASE + 0x18)
-#define MXC_DVFSEMAC           (MXC_DVFS_CORE_BASE + 0x1C)
-#define MXC_DVFSCNTR           (MXC_DVFS_CORE_BASE + 0x20)
-#define MXC_DVFSLTR0_0         (MXC_DVFS_CORE_BASE + 0x24)
-#define MXC_DVFSLTR0_1         (MXC_DVFS_CORE_BASE + 0x28)
-#define MXC_DVFSLTR1_0         (MXC_DVFS_CORE_BASE + 0x2C)
-#define MXC_DVFSLTR1_1         (MXC_DVFS_CORE_BASE + 0x30)
-#define MXC_DVFSPT0            (MXC_DVFS_CORE_BASE + 0x34)
-#define MXC_DVFSPT1            (MXC_DVFS_CORE_BASE + 0x38)
-#define MXC_DVFSPT2            (MXC_DVFS_CORE_BASE + 0x3C)
-#define MXC_DVFSPT3            (MXC_DVFS_CORE_BASE + 0x40)
-
-/* GPC */
-#define MXC_GPC_CNTR           (MX51_GPC_BASE + 0x0)
-#define MXC_GPC_PGR            (MX51_GPC_BASE + 0x4)
-#define MXC_GPC_VCR            (MX51_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU         (MX51_GPC_BASE + 0xC)
-#define MXC_GPC_NEON           (MX51_GPC_BASE + 0x10)
-#define MXC_GPC_PGR_ARMPG_OFFSET       8
-#define MXC_GPC_PGR_ARMPG_MASK         (3 << 8)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR       (MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR       (MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR       (MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR       (MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR       (MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR       (MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR           1
-#define MXC_SRPGCR_PCR         1
-#define MXC_EMPGCR_PCR         1
-#define MXC_PGSR_PSR           1
-
-
-#define MXC_CORTEXA8_PLAT_LPC_DSM      (1 << 0)
-#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM  (1 << 1)
-
-/* SRPG */
-#define MXC_SRPG_NEON_SRPGCR   (MXC_SRPG_NEON_BASE + 0x0)
-#define MXC_SRPG_NEON_PUPSCR   (MXC_SRPG_NEON_BASE + 0x4)
-#define MXC_SRPG_NEON_PDNSCR   (MXC_SRPG_NEON_BASE + 0x8)
-
-#define MXC_SRPG_ARM_SRPGCR    (MXC_SRPG_ARM_BASE + 0x0)
-#define MXC_SRPG_ARM_PUPSCR    (MXC_SRPG_ARM_BASE + 0x4)
-#define MXC_SRPG_ARM_PDNSCR    (MXC_SRPG_ARM_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
-#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
-#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
-#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
-#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
-
-#define MXC_SRPG_MEGAMIX_SRPGCR                (MXC_SRPG_MEGAMIX_BASE + 0x0)
-#define MXC_SRPG_MEGAMIX_PUPSCR                (MXC_SRPG_MEGAMIX_BASE + 0x4)
-#define MXC_SRPG_MEGAMIX_PDNSCR                (MXC_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MXC_SRPGC_EMI_SRPGCR   (MXC_SRPGC_EMI_BASE + 0x0)
-#define MXC_SRPGC_EMI_PUPSCR   (MXC_SRPGC_EMI_BASE + 0x4)
-#define MXC_SRPGC_EMI_PDNSCR   (MXC_SRPGC_EMI_BASE + 0x8)
-
-#endif                         /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h
deleted file mode 100644 (file)
index 7216667..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <mach/mx50.h>
-#include <mach/devices-common.h>
-
-extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
-#define imx50_add_imx_uart(id, pdata)  \
-       imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
-
-extern const struct imx_fec_data imx50_fec_data;
-#define imx50_add_fec(pdata)   \
-       imx_add_fec(&imx50_fec_data, pdata)
-
-extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
-#define imx50_add_imx_i2c(id, pdata)   \
-       imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
deleted file mode 100644 (file)
index af488bc..0000000
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx51.h>
-#include <mach/devices-common.h>
-
-extern const struct imx_fec_data imx51_fec_data;
-#define imx51_add_fec(pdata)   \
-       imx_add_fec(&imx51_fec_data, pdata)
-
-extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
-#define imx51_add_fsl_usb2_udc(pdata)  \
-       imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
-
-extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
-#define imx51_add_imx_i2c(id, pdata)   \
-       imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
-#define imx51_add_hsi2c(pdata) \
-       imx51_add_imx_i2c(2, pdata)
-
-extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
-#define imx51_add_imx_ssi(id, pdata)   \
-       imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
-#define imx51_add_imx_uart(id, pdata)  \
-       imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
-
-extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
-#define imx51_add_mxc_ehci_otg(pdata)  \
-       imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
-#define imx51_add_mxc_ehci_hs(id, pdata)       \
-       imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
-
-extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
-#define imx51_add_mxc_nand(pdata)      \
-       imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
-
-extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
-#define imx51_add_sdhci_esdhc_imx(id, pdata)   \
-       imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx51_cspi_data;
-#define imx51_add_cspi(pdata)  \
-       imx_add_spi_imx(&imx51_cspi_data, pdata)
-
-extern const struct imx_spi_imx_data imx51_ecspi_data[];
-#define imx51_add_ecspi(id, pdata)     \
-       imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
-
-extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
-#define imx51_add_imx2_wdt(id, pdata)  \
-       imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
-
-extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
-#define imx51_add_mxc_pwm(id)  \
-       imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
-
-extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
-#define imx51_add_imx_keypad(pdata)    \
-       imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
-
-extern const struct imx_pata_imx_data imx51_pata_imx_data;
-#define imx51_add_pata_imx() \
-       imx_add_pata_imx(&imx51_pata_imx_data)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
deleted file mode 100644 (file)
index 6e1e5d1..0000000
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx53.h>
-#include <mach/devices-common.h>
-
-extern const struct imx_fec_data imx53_fec_data;
-#define imx53_add_fec(pdata)   \
-       imx_add_fec(&imx53_fec_data, pdata)
-
-extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
-#define imx53_add_imx_uart(id, pdata)  \
-       imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
-
-
-extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
-#define imx53_add_imx_i2c(id, pdata)   \
-       imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
-
-extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
-#define imx53_add_sdhci_esdhc_imx(id, pdata)   \
-       imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx53_ecspi_data[];
-#define imx53_add_ecspi(id, pdata)     \
-       imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
-
-extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
-#define imx53_add_imx2_wdt(id, pdata)  \
-       imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
-
-extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
-#define imx53_add_imx_ssi(id, pdata)   \
-       imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
-#define imx53_add_imx_keypad(pdata)    \
-       imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
-
-extern const struct imx_pata_imx_data imx53_pata_imx_data;
-#define imx53_add_pata_imx() \
-       imx_add_pata_imx(&imx53_pata_imx_data)
-
-extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h
deleted file mode 100644 (file)
index 014aa98..0000000
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _EFIKA_H
-#define _EFIKA_H
-
-#define EFIKA_WLAN_EN          IMX_GPIO_NR(2, 16)
-#define EFIKA_WLAN_RESET       IMX_GPIO_NR(2, 10)
-#define EFIKA_USB_PHY_RESET    IMX_GPIO_NR(2, 9)
-
-void __init efika_board_common_init(void);
-
-#endif
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
deleted file mode 100644 (file)
index c17fa13..0000000
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
-
-#define MXC_OTG_OFFSET                 0
-#define MXC_H1_OFFSET                  0x200
-#define MXC_H2_OFFSET                  0x400
-
-/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT         (1 << 27)       /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT          (1 << 24)       /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT         (1 << 12)       /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT         (1 << 11)       /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT          (1 <<  8)               /* HOST1 power mask */
-
-/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT     (1 << 8)        /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT              (1 << 5)        /* UH1 Disable Overcurrent Event */
-
-/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT         (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT         (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT          (1 << 4)
-
-#define MXC_USBCMD_OFFSET              0x140
-
-/* USBCMD */
-#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
-
-int mx51_initialize_usb_hw(int port, unsigned int flags)
-{
-       unsigned int v;
-       void __iomem *usb_base;
-       void __iomem *usbotg_base;
-       void __iomem *usbother_base;
-       int ret = 0;
-
-       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-       if (!usb_base) {
-               printk(KERN_ERR "%s(): ioremap failed\n", __func__);
-               return -ENOMEM;
-       }
-
-       switch (port) {
-       case 0: /* OTG port */
-               usbotg_base = usb_base + MXC_OTG_OFFSET;
-               break;
-       case 1: /* Host 1 port */
-               usbotg_base = usb_base + MXC_H1_OFFSET;
-               break;
-       case 2: /* Host 2 port */
-               usbotg_base = usb_base + MXC_H2_OFFSET;
-               break;
-       default:
-               printk(KERN_ERR"%s no such port %d\n", __func__, port);
-               ret = -ENOENT;
-               goto error;
-       }
-       usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-
-       switch (port) {
-       case 0: /*OTG port */
-               if (flags & MXC_EHCI_INTERNAL_PHY) {
-                       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                       if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
-                               /* OC/USBPWR is not used */
-                               v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                       } else {
-                               /* OC/USBPWR is used */
-                               v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                       }
-                       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-                       v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                       if (flags & MXC_EHCI_WAKEUP_ENABLED)
-                               v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
-                       else
-                               v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
-                       if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                               v |= MXC_OTG_UCTRL_OPM_BIT;
-                       else
-                               v &= ~MXC_OTG_UCTRL_OPM_BIT;
-                       __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-               }
-               break;
-       case 1: /* Host 1 */
-               /*Host ULPI */
-               v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-               if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                       /* HOST1 wakeup/ULPI intr enable */
-                       v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-               } else {
-                       /* HOST1 wakeup/ULPI intr disable */
-                       v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
-               }
-
-               if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                       v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-               else
-                       v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-               __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-
-               v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-               if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                       v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
-               else
-                       v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
-               __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
-
-               v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
-               if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
-                       /* Interrupt Threshold Control:Immediate (no threshold) */
-                       v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
-               __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
-               break;
-       case 2: /* Host 2 ULPI */
-               v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
-               if (flags & MXC_EHCI_WAKEUP_ENABLED) {
-                       /* HOST1 wakeup/ULPI intr enable */
-                       v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-               } else {
-                       /* HOST1 wakeup/ULPI intr disable */
-                       v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
-               }
-
-               if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                       v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
-               else
-                       v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
-               __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
-               break;
-       }
-
-error:
-       iounmap(usb_base);
-       return ret;
-}
-
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
deleted file mode 100644 (file)
index a6a3ab8..0000000
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- *
- * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/i2c/tsc2007.h>
-#include <linux/leds.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/mach/arch.h>
-
-#include "devices-imx51.h"
-
-#define MBIMX51_TSC2007_GPIO   IMX_GPIO_NR(3, 30)
-#define MBIMX51_LED0           IMX_GPIO_NR(3, 5)
-#define MBIMX51_LED1           IMX_GPIO_NR(3, 6)
-#define MBIMX51_LED2           IMX_GPIO_NR(3, 7)
-#define MBIMX51_LED3           IMX_GPIO_NR(3, 8)
-
-static const struct gpio_led mbimx51_leds[] __initconst = {
-       {
-               .name                   = "led0",
-               .default_trigger        = "heartbeat",
-               .active_low             = 1,
-               .gpio                   = MBIMX51_LED0,
-       },
-       {
-               .name                   = "led1",
-               .default_trigger        = "nand-disk",
-               .active_low             = 1,
-               .gpio                   = MBIMX51_LED1,
-       },
-       {
-               .name                   = "led2",
-               .default_trigger        = "mmc0",
-               .active_low             = 1,
-               .gpio                   = MBIMX51_LED2,
-       },
-       {
-               .name                   = "led3",
-               .default_trigger        = "default-on",
-               .active_low             = 1,
-               .gpio                   = MBIMX51_LED3,
-       },
-};
-
-static const struct gpio_led_platform_data mbimx51_leds_info __initconst = {
-       .leds           = mbimx51_leds,
-       .num_leds       = ARRAY_SIZE(mbimx51_leds),
-};
-
-static iomux_v3_cfg_t mbimx51_pads[] = {
-       /* UART2 */
-       MX51_PAD_UART2_RXD__UART2_RXD,
-       MX51_PAD_UART2_TXD__UART2_TXD,
-
-       /* UART3 */
-       MX51_PAD_UART3_RXD__UART3_RXD,
-       MX51_PAD_UART3_TXD__UART3_TXD,
-       MX51_PAD_KEY_COL4__UART3_RTS,
-       MX51_PAD_KEY_COL5__UART3_CTS,
-
-       /* TSC2007 IRQ */
-       MX51_PAD_NANDF_D10__GPIO3_30,
-
-       /* LEDS */
-       MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
-       MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
-       MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
-       MX51_PAD_DISPB2_SER_RS__GPIO3_8,
-
-       /* KPP */
-       MX51_PAD_KEY_ROW0__KEY_ROW0,
-       MX51_PAD_KEY_ROW1__KEY_ROW1,
-       MX51_PAD_KEY_ROW2__KEY_ROW2,
-       MX51_PAD_KEY_ROW3__KEY_ROW3,
-       MX51_PAD_KEY_COL0__KEY_COL0,
-       MX51_PAD_KEY_COL1__KEY_COL1,
-       MX51_PAD_KEY_COL2__KEY_COL2,
-       MX51_PAD_KEY_COL3__KEY_COL3,
-
-       /* SD 1 */
-       MX51_PAD_SD1_CMD__SD1_CMD,
-       MX51_PAD_SD1_CLK__SD1_CLK,
-       MX51_PAD_SD1_DATA0__SD1_DATA0,
-       MX51_PAD_SD1_DATA1__SD1_DATA1,
-       MX51_PAD_SD1_DATA2__SD1_DATA2,
-       MX51_PAD_SD1_DATA3__SD1_DATA3,
-
-       /* SD 2 */
-       MX51_PAD_SD2_CMD__SD2_CMD,
-       MX51_PAD_SD2_CLK__SD2_CLK,
-       MX51_PAD_SD2_DATA0__SD2_DATA0,
-       MX51_PAD_SD2_DATA1__SD2_DATA1,
-       MX51_PAD_SD2_DATA2__SD2_DATA2,
-       MX51_PAD_SD2_DATA3__SD2_DATA3,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static int mbimx51_keymap[] = {
-       KEY(0, 0, KEY_1),
-       KEY(0, 1, KEY_2),
-       KEY(0, 2, KEY_3),
-       KEY(0, 3, KEY_UP),
-
-       KEY(1, 0, KEY_4),
-       KEY(1, 1, KEY_5),
-       KEY(1, 2, KEY_6),
-       KEY(1, 3, KEY_LEFT),
-
-       KEY(2, 0, KEY_7),
-       KEY(2, 1, KEY_8),
-       KEY(2, 2, KEY_9),
-       KEY(2, 3, KEY_RIGHT),
-
-       KEY(3, 0, KEY_0),
-       KEY(3, 1, KEY_DOWN),
-       KEY(3, 2, KEY_ESC),
-       KEY(3, 3, KEY_ENTER),
-};
-
-static const struct matrix_keymap_data mbimx51_map_data __initconst = {
-       .keymap         = mbimx51_keymap,
-       .keymap_size    = ARRAY_SIZE(mbimx51_keymap),
-};
-
-static int tsc2007_get_pendown_state(void)
-{
-       return !gpio_get_value(MBIMX51_TSC2007_GPIO);
-}
-
-struct tsc2007_platform_data tsc2007_data = {
-       .model = 2007,
-       .x_plate_ohms = 180,
-       .get_pendown_state = tsc2007_get_pendown_state,
-};
-
-static struct i2c_board_info mbimx51_i2c_devices[] = {
-       {
-               I2C_BOARD_INFO("tsc2007", 0x49),
-               .irq  = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO),
-               .platform_data = &tsc2007_data,
-       }, {
-               I2C_BOARD_INFO("tlv320aic23", 0x1a),
-       },
-};
-
-/*
- * baseboard initialization.
- */
-void __init eukrea_mbimx51_baseboard_init(void)
-{
-       mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
-                                       ARRAY_SIZE(mbimx51_pads));
-
-       imx51_add_imx_uart(1, NULL);
-       imx51_add_imx_uart(2, &uart_pdata);
-
-       gpio_request(MBIMX51_LED0, "LED0");
-       gpio_direction_output(MBIMX51_LED0, 1);
-       gpio_free(MBIMX51_LED0);
-       gpio_request(MBIMX51_LED1, "LED1");
-       gpio_direction_output(MBIMX51_LED1, 1);
-       gpio_free(MBIMX51_LED1);
-       gpio_request(MBIMX51_LED2, "LED2");
-       gpio_direction_output(MBIMX51_LED2, 1);
-       gpio_free(MBIMX51_LED2);
-       gpio_request(MBIMX51_LED3, "LED3");
-       gpio_direction_output(MBIMX51_LED3, 1);
-       gpio_free(MBIMX51_LED3);
-
-       gpio_led_register_device(-1, &mbimx51_leds_info);
-
-       imx51_add_imx_keypad(&mbimx51_map_data);
-
-       gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
-       gpio_direction_input(MBIMX51_TSC2007_GPIO);
-       irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO),
-                                       IRQF_TRIGGER_FALLING);
-       i2c_register_board_info(1, mbimx51_i2c_devices,
-                               ARRAY_SIZE(mbimx51_i2c_devices));
-
-       imx51_add_sdhci_esdhc_imx(0, NULL);
-       imx51_add_sdhci_esdhc_imx(1, NULL);
-}
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
deleted file mode 100644 (file)
index d817fc8..0000000
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric@eukrea.com
- *
- * Based on pcm970-baseboard.c which is :
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx51.h>
-#include <mach/audmux.h>
-
-#include "devices-imx51.h"
-
-static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
-       /* LED */
-       MX51_PAD_NANDF_D10__GPIO3_30,
-       /* SWITCH */
-       NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
-                       PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                       PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-       /* UART2 */
-       MX51_PAD_UART2_RXD__UART2_RXD,
-       MX51_PAD_UART2_TXD__UART2_TXD,
-       /* UART 3 */
-       MX51_PAD_UART3_RXD__UART3_RXD,
-       MX51_PAD_UART3_TXD__UART3_TXD,
-       MX51_PAD_KEY_COL4__UART3_RTS,
-       MX51_PAD_KEY_COL5__UART3_CTS,
-       /* SD */
-       MX51_PAD_SD1_CMD__SD1_CMD,
-       MX51_PAD_SD1_CLK__SD1_CLK,
-       MX51_PAD_SD1_DATA0__SD1_DATA0,
-       MX51_PAD_SD1_DATA1__SD1_DATA1,
-       MX51_PAD_SD1_DATA2__SD1_DATA2,
-       MX51_PAD_SD1_DATA3__SD1_DATA3,
-       /* SD1 CD */
-       NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
-                       PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                       PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-};
-
-#define GPIO_LED1      IMX_GPIO_NR(3, 30)
-#define GPIO_SWITCH1   IMX_GPIO_NR(3, 31)
-
-static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
-       {
-               .name                   = "led1",
-               .default_trigger        = "heartbeat",
-               .active_low             = 1,
-               .gpio                   = GPIO_LED1,
-       },
-};
-
-static const struct gpio_led_platform_data
-               eukrea_mbimxsd_led_info __initconst = {
-       .leds           = eukrea_mbimxsd_leds,
-       .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
-};
-
-static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
-       {
-               .gpio           = GPIO_SWITCH1,
-               .code           = BTN_0,
-               .desc           = "BP1",
-               .active_low     = 1,
-               .wakeup         = 1,
-       },
-};
-
-static const struct gpio_keys_platform_data
-               eukrea_mbimxsd_button_data __initconst = {
-       .buttons        = eukrea_mbimxsd_gpio_buttons,
-       .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
-       {
-               I2C_BOARD_INFO("tlv320aic23", 0x1a),
-       },
-};
-
-/*
- * system init for baseboard usage. Will be called by cpuimx51sd init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init eukrea_mbimxsd51_baseboard_init(void)
-{
-       if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
-                       ARRAY_SIZE(eukrea_mbimxsd_pads)))
-               printk(KERN_ERR "error setting mbimxsd pads !\n");
-
-       imx51_add_imx_uart(1, NULL);
-       imx51_add_imx_uart(2, &uart_pdata);
-
-       imx51_add_sdhci_esdhc_imx(0, NULL);
-
-       gpio_request(GPIO_LED1, "LED1");
-       gpio_direction_output(GPIO_LED1, 1);
-       gpio_free(GPIO_LED1);
-
-       gpio_request(GPIO_SWITCH1, "SWITCH1");
-       gpio_direction_input(GPIO_SWITCH1);
-       gpio_free(GPIO_SWITCH1);
-
-       i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
-                               ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
-
-       gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
-       imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
-}
diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-mx5/imx51-dt.c
deleted file mode 100644 (file)
index ccc6158..0000000
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/mx51.h>
-
-/*
- * Lookup table for attaching a specific name and platform_data pointer to
- * devices as they get created by of_platform_populate().  Ideally this table
- * would not exist, but the current clock implementation depends on some devices
- * having a specific name.
- */
-static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
-       OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
-       OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
-       { /* sentinel */ }
-};
-
-static void __init imx51_tzic_add_irq_domain(struct device_node *np,
-                               struct device_node *interrupt_parent)
-{
-       irq_domain_add_simple(np, 0);
-}
-
-static void __init imx51_gpio_add_irq_domain(struct device_node *np,
-                               struct device_node *interrupt_parent)
-{
-       static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
-                                  32 * 4; /* imx51 gets 4 gpio ports */
-
-       irq_domain_add_simple(np, gpio_irq_base);
-       gpio_irq_base += 32;
-}
-
-static const struct of_device_id imx51_irq_match[] __initconst = {
-       { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
-       { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
-       { /* sentinel */ }
-};
-
-static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
-       { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
-       { /* sentinel */ }
-};
-
-static void __init imx51_dt_init(void)
-{
-       struct device_node *node;
-       const struct of_device_id *of_id;
-       void (*func)(void);
-
-       of_irq_init(imx51_irq_match);
-
-       node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
-       if (node) {
-               of_id = of_match_node(imx51_iomuxc_of_match, node);
-               func = of_id->data;
-               func();
-               of_node_put(node);
-       }
-
-       of_platform_populate(NULL, of_default_bus_match_table,
-                            imx51_auxdata_lookup, NULL);
-}
-
-static void __init imx51_timer_init(void)
-{
-       mx51_clocks_init_dt();
-}
-
-static struct sys_timer imx51_timer = {
-       .init = imx51_timer_init,
-};
-
-static const char *imx51_dt_board_compat[] __initdata = {
-       "fsl,imx51-babbage",
-       NULL
-};
-
-DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
-       .map_io         = mx51_map_io,
-       .init_early     = imx51_init_early,
-       .init_irq       = mx51_init_irq,
-       .handle_irq     = imx51_handle_irq,
-       .timer          = &imx51_timer,
-       .init_machine   = imx51_dt_init,
-       .dt_compat      = imx51_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-mx5/imx53-dt.c
deleted file mode 100644 (file)
index ccaa0b8..0000000
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/mx53.h>
-
-/*
- * Lookup table for attaching a specific name and platform_data pointer to
- * devices as they get created by of_platform_populate().  Ideally this table
- * would not exist, but the current clock implementation depends on some devices
- * having a specific name.
- */
-static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
-       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
-       OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
-       { /* sentinel */ }
-};
-
-static void __init imx53_tzic_add_irq_domain(struct device_node *np,
-                               struct device_node *interrupt_parent)
-{
-       irq_domain_add_simple(np, 0);
-}
-
-static void __init imx53_gpio_add_irq_domain(struct device_node *np,
-                               struct device_node *interrupt_parent)
-{
-       static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
-                                  32 * 7; /* imx53 gets 7 gpio ports */
-
-       irq_domain_add_simple(np, gpio_irq_base);
-       gpio_irq_base += 32;
-}
-
-static const struct of_device_id imx53_irq_match[] __initconst = {
-       { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
-       { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
-       { /* sentinel */ }
-};
-
-static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
-       { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
-       { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
-       { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
-       { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
-       { /* sentinel */ }
-};
-
-static void __init imx53_dt_init(void)
-{
-       struct device_node *node;
-       const struct of_device_id *of_id;
-       void (*func)(void);
-
-       of_irq_init(imx53_irq_match);
-
-       node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
-       if (node) {
-               of_id = of_match_node(imx53_iomuxc_of_match, node);
-               func = of_id->data;
-               func();
-               of_node_put(node);
-       }
-
-       of_platform_populate(NULL, of_default_bus_match_table,
-                            imx53_auxdata_lookup, NULL);
-}
-
-static void __init imx53_timer_init(void)
-{
-       mx53_clocks_init_dt();
-}
-
-static struct sys_timer imx53_timer = {
-       .init = imx53_timer_init,
-};
-
-static const char *imx53_dt_board_compat[] __initdata = {
-       "fsl,imx53-ard",
-       "fsl,imx53-evk",
-       "fsl,imx53-qsb",
-       "fsl,imx53-smd",
-       NULL
-};
-
-DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
-       .map_io         = mx53_map_io,
-       .init_early     = imx53_init_early,
-       .init_irq       = mx53_init_irq,
-       .handle_irq     = imx53_handle_irq,
-       .timer          = &imx53_timer,
-       .init_machine   = imx53_dt_init,
-       .dt_compat      = imx53_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
deleted file mode 100644 (file)
index 26eacc9..0000000
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License.  You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * Create static mapping between physical to virtual memory.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/devices-common.h>
-#include <mach/iomux-v3.h>
-
-static void imx5_idle(void)
-{
-       mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-}
-
-/*
- * Define the MX50 memory map.
- */
-static struct map_desc mx50_io_desc[] __initdata = {
-       imx_map_entry(MX50, TZIC, MT_DEVICE),
-       imx_map_entry(MX50, SPBA0, MT_DEVICE),
-       imx_map_entry(MX50, AIPS1, MT_DEVICE),
-       imx_map_entry(MX50, AIPS2, MT_DEVICE),
-};
-
-/*
- * Define the MX51 memory map.
- */
-static struct map_desc mx51_io_desc[] __initdata = {
-       imx_map_entry(MX51, TZIC, MT_DEVICE),
-       imx_map_entry(MX51, IRAM, MT_DEVICE),
-       imx_map_entry(MX51, AIPS1, MT_DEVICE),
-       imx_map_entry(MX51, SPBA0, MT_DEVICE),
-       imx_map_entry(MX51, AIPS2, MT_DEVICE),
-};
-
-/*
- * Define the MX53 memory map.
- */
-static struct map_desc mx53_io_desc[] __initdata = {
-       imx_map_entry(MX53, TZIC, MT_DEVICE),
-       imx_map_entry(MX53, AIPS1, MT_DEVICE),
-       imx_map_entry(MX53, SPBA0, MT_DEVICE),
-       imx_map_entry(MX53, AIPS2, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx50_map_io(void)
-{
-       iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
-}
-
-void __init mx51_map_io(void)
-{
-       iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
-}
-
-void __init mx53_map_io(void)
-{
-       iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
-}
-
-void __init imx50_init_early(void)
-{
-       mxc_set_cpu_type(MXC_CPU_MX50);
-       mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
-       mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
-}
-
-void __init imx51_init_early(void)
-{
-       mxc_set_cpu_type(MXC_CPU_MX51);
-       mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
-       mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-       imx_idle = imx5_idle;
-}
-
-void __init imx53_init_early(void)
-{
-       mxc_set_cpu_type(MXC_CPU_MX53);
-       mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
-       mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
-}
-
-void __init mx50_init_irq(void)
-{
-       tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-}
-
-void __init mx51_init_irq(void)
-{
-       tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
-}
-
-void __init mx53_init_irq(void)
-{
-       tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
-}
-
-static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
-       .ap_2_ap_addr = 642,
-       .uart_2_mcu_addr = 817,
-       .mcu_2_app_addr = 747,
-       .mcu_2_shp_addr = 961,
-       .ata_2_mcu_addr = 1473,
-       .mcu_2_ata_addr = 1392,
-       .app_2_per_addr = 1033,
-       .app_2_mcu_addr = 683,
-       .shp_2_per_addr = 1251,
-       .shp_2_mcu_addr = 892,
-};
-
-static struct sdma_platform_data imx51_sdma_pdata __initdata = {
-       .fw_name = "sdma-imx51.bin",
-       .script_addrs = &imx51_sdma_script,
-};
-
-static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
-       .ap_2_ap_addr = 642,
-       .app_2_mcu_addr = 683,
-       .mcu_2_app_addr = 747,
-       .uart_2_mcu_addr = 817,
-       .shp_2_mcu_addr = 891,
-       .mcu_2_shp_addr = 960,
-       .uartsh_2_mcu_addr = 1032,
-       .spdif_2_mcu_addr = 1100,
-       .mcu_2_spdif_addr = 1134,
-       .firi_2_mcu_addr = 1193,
-       .mcu_2_firi_addr = 1290,
-};
-
-static struct sdma_platform_data imx53_sdma_pdata __initdata = {
-       .fw_name = "sdma-imx53.bin",
-       .script_addrs = &imx53_sdma_script,
-};
-
-void __init imx50_soc_init(void)
-{
-       /* i.mx50 has the i.mx31 type gpio */
-       mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
-       mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
-       mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
-       mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
-       mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
-       mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
-}
-
-void __init imx51_soc_init(void)
-{
-       /* i.mx51 has the i.mx31 type gpio */
-       mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
-       mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
-       mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
-       mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
-
-       /* i.mx51 has the i.mx35 type sdma */
-       imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
-}
-
-void __init imx53_soc_init(void)
-{
-       /* i.mx53 has the i.mx31 type gpio */
-       mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
-       mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
-       mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
-       mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
-       mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
-       mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
-       mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
-
-       /* i.mx53 has the i.mx35 type sdma */
-       imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
-}
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
deleted file mode 100644 (file)
index ec6ca91..0000000
+++ /dev/null
@@ -1,632 +0,0 @@
-/*
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-#include "cpu_op-mx51.h"
-
-#define MX51_USB_CTRL_1_OFFSET          0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
-#define        MX51_USB_PLL_DIV_19_2_MHZ       0x01
-
-#define EFIKAMX_USB_HUB_RESET  IMX_GPIO_NR(1, 5)
-#define EFIKAMX_USBH1_STP      IMX_GPIO_NR(1, 27)
-
-#define EFIKAMX_SPI_CS0                IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_CS1                IMX_GPIO_NR(4, 25)
-
-#define EFIKAMX_PMIC           IMX_GPIO_NR(1, 6)
-
-static iomux_v3_cfg_t mx51efika_pads[] = {
-       /* UART1 */
-       MX51_PAD_UART1_RXD__UART1_RXD,
-       MX51_PAD_UART1_TXD__UART1_TXD,
-       MX51_PAD_UART1_RTS__UART1_RTS,
-       MX51_PAD_UART1_CTS__UART1_CTS,
-
-       /* SD 1 */
-       MX51_PAD_SD1_CMD__SD1_CMD,
-       MX51_PAD_SD1_CLK__SD1_CLK,
-       MX51_PAD_SD1_DATA0__SD1_DATA0,
-       MX51_PAD_SD1_DATA1__SD1_DATA1,
-       MX51_PAD_SD1_DATA2__SD1_DATA2,
-       MX51_PAD_SD1_DATA3__SD1_DATA3,
-
-       /* SD 2 */
-       MX51_PAD_SD2_CMD__SD2_CMD,
-       MX51_PAD_SD2_CLK__SD2_CLK,
-       MX51_PAD_SD2_DATA0__SD2_DATA0,
-       MX51_PAD_SD2_DATA1__SD2_DATA1,
-       MX51_PAD_SD2_DATA2__SD2_DATA2,
-       MX51_PAD_SD2_DATA3__SD2_DATA3,
-
-       /* SD/MMC WP/CD */
-       MX51_PAD_GPIO1_0__SD1_CD,
-       MX51_PAD_GPIO1_1__SD1_WP,
-       MX51_PAD_GPIO1_7__SD2_WP,
-       MX51_PAD_GPIO1_8__SD2_CD,
-
-       /* spi */
-       MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-       MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-       MX51_PAD_CSPI1_SS0__GPIO4_24,
-       MX51_PAD_CSPI1_SS1__GPIO4_25,
-       MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
-       MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-       MX51_PAD_GPIO1_6__GPIO1_6,
-
-       /* USB HOST1 */
-       MX51_PAD_USBH1_CLK__USBH1_CLK,
-       MX51_PAD_USBH1_DIR__USBH1_DIR,
-       MX51_PAD_USBH1_NXT__USBH1_NXT,
-       MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-       MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-       MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-       MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-       MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-       MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-       MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-       MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-
-       /* USB HUB RESET */
-       MX51_PAD_GPIO1_5__GPIO1_5,
-
-       /* WLAN */
-       MX51_PAD_EIM_A22__GPIO2_16,
-       MX51_PAD_EIM_A16__GPIO2_10,
-
-       /* USB PHY RESET */
-       MX51_PAD_EIM_D27__GPIO2_9,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata = {
-       .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/* This function is board specific as the bit mask for the plldiv will also
- * be different for other Freescale SoCs, thus a common bitmask is not
- * possible and cannot get place in /plat-mxc/ehci.c.
- */
-static int initialize_otg_port(struct platform_device *pdev)
-{
-       u32 v;
-       void __iomem *usb_base;
-       void __iomem *usbother_base;
-       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-       if (!usb_base)
-               return -ENOMEM;
-       usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-       /* Set the PHY clock to 19.2MHz */
-       v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-       v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-       v |= MX51_USB_PLL_DIV_19_2_MHZ;
-       __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-       iounmap(usb_base);
-
-       mdelay(10);
-
-       return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
-}
-
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-       .init   = initialize_otg_port,
-       .portsc = MXC_EHCI_UTMI_16BIT,
-};
-
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-       iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-       iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
-       u32 v;
-       void __iomem *usb_base;
-       void __iomem *socregs_base;
-
-       mxc_iomux_v3_setup_pad(usbh1gpio);
-       gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
-       gpio_direction_output(EFIKAMX_USBH1_STP, 0);
-       msleep(1);
-       gpio_set_value(EFIKAMX_USBH1_STP, 1);
-       msleep(1);
-
-       usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-       socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-       /* The clock for the USBH1 ULPI port will come externally */
-       /* from the PHY. */
-       v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
-       __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
-                       socregs_base + MX51_USB_CTRL_1_OFFSET);
-
-       iounmap(usb_base);
-
-       gpio_free(EFIKAMX_USBH1_STP);
-       mxc_iomux_v3_setup_pad(usbh1stp);
-
-       mdelay(10);
-
-       return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static struct mxc_usbh_platform_data usbh1_config __initdata = {
-       .init   = initialize_usbh1_port,
-       .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static void mx51_efika_hubreset(void)
-{
-       gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
-       gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
-       msleep(1);
-       gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
-       msleep(1);
-       gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
-}
-
-static void __init mx51_efika_usb(void)
-{
-       mx51_efika_hubreset();
-
-       /* pulling it low, means no USB at all... */
-       gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
-       gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
-       msleep(1);
-       gpio_set_value(EFIKA_USB_PHY_RESET, 1);
-
-       usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                       ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-
-       imx51_add_mxc_ehci_otg(&dr_utmi_config);
-       if (usbh1_config.otg)
-               imx51_add_mxc_ehci_hs(1, &usbh1_config);
-}
-
-static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
-       {
-        .name = "u-boot",
-        .offset = 0,
-        .size = SZ_256K,
-       },
-       {
-         .name = "config",
-         .offset = MTDPART_OFS_APPEND,
-         .size = SZ_64K,
-       },
-};
-
-static struct flash_platform_data mx51_efika_spi_flash_data = {
-       .name           = "spi_flash",
-       .parts          = mx51_efika_spi_nor_partitions,
-       .nr_parts       = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
-       .type           = "sst25vf032b",
-};
-
-static struct regulator_consumer_supply sw1_consumers[] = {
-       {
-               .supply = "cpu_vcc",
-       }
-};
-
-static struct regulator_consumer_supply vdig_consumers[] = {
-       /* sgtl5000 */
-       REGULATOR_SUPPLY("VDDA", "1-000a"),
-       REGULATOR_SUPPLY("VDDD", "1-000a"),
-};
-
-static struct regulator_consumer_supply vvideo_consumers[] = {
-       /* sgtl5000 */
-       REGULATOR_SUPPLY("VDDIO", "1-000a"),
-};
-
-static struct regulator_consumer_supply vsd_consumers[] = {
-       REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
-       REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
-};
-
-static struct regulator_consumer_supply pwgt1_consumer[] = {
-       {
-               .supply = "pwgt1",
-       }
-};
-
-static struct regulator_consumer_supply pwgt2_consumer[] = {
-       {
-               .supply = "pwgt2",
-       }
-};
-
-static struct regulator_consumer_supply coincell_consumer[] = {
-       {
-               .supply = "coincell",
-       }
-};
-
-static struct regulator_init_data sw1_init = {
-       .constraints = {
-               .name = "SW1",
-               .min_uV = 600000,
-               .max_uV = 1375000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .valid_modes_mask = 0,
-               .always_on = 1,
-               .boot_on = 1,
-               .state_mem = {
-                       .uV = 850000,
-                       .mode = REGULATOR_MODE_NORMAL,
-                       .enabled = 1,
-               },
-       },
-       .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
-       .consumer_supplies = sw1_consumers,
-};
-
-static struct regulator_init_data sw2_init = {
-       .constraints = {
-               .name = "SW2",
-               .min_uV = 900000,
-               .max_uV = 1850000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .always_on = 1,
-               .boot_on = 1,
-               .state_mem = {
-                       .uV = 950000,
-                       .mode = REGULATOR_MODE_NORMAL,
-                       .enabled = 1,
-               },
-       }
-};
-
-static struct regulator_init_data sw3_init = {
-       .constraints = {
-               .name = "SW3",
-               .min_uV = 1100000,
-               .max_uV = 1850000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .always_on = 1,
-               .boot_on = 1,
-       }
-};
-
-static struct regulator_init_data sw4_init = {
-       .constraints = {
-               .name = "SW4",
-               .min_uV = 1100000,
-               .max_uV = 1850000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .always_on = 1,
-               .boot_on = 1,
-       }
-};
-
-static struct regulator_init_data viohi_init = {
-       .constraints = {
-               .name = "VIOHI",
-               .boot_on = 1,
-               .always_on = 1,
-       }
-};
-
-static struct regulator_init_data vusb_init = {
-       .constraints = {
-               .name = "VUSB",
-               .boot_on = 1,
-               .always_on = 1,
-       }
-};
-
-static struct regulator_init_data swbst_init = {
-       .constraints = {
-               .name = "SWBST",
-       }
-};
-
-static struct regulator_init_data vdig_init = {
-       .constraints = {
-               .name = "VDIG",
-               .min_uV = 1050000,
-               .max_uV = 1800000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-               .boot_on = 1,
-               .always_on = 1,
-       },
-       .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
-       .consumer_supplies = vdig_consumers,
-};
-
-static struct regulator_init_data vpll_init = {
-       .constraints = {
-               .name = "VPLL",
-               .min_uV = 1050000,
-               .max_uV = 1800000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-               .boot_on = 1,
-               .always_on = 1,
-       }
-};
-
-static struct regulator_init_data vusb2_init = {
-       .constraints = {
-               .name = "VUSB2",
-               .min_uV = 2400000,
-               .max_uV = 2775000,
-               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-               .boot_on = 1,
-               .always_on = 1,
-       }
-};
-
-static struct regulator_init_data vvideo_init = {
-       .constraints = {
-               .name = "VVIDEO",
-               .min_uV = 2775000,
-               .max_uV = 2775000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-               .boot_on = 1,
-               .apply_uV = 1,
-       },
-       .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
-       .consumer_supplies = vvideo_consumers,
-};
-
-static struct regulator_init_data vaudio_init = {
-       .constraints = {
-               .name = "VAUDIO",
-               .min_uV = 2300000,
-               .max_uV = 3000000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-               .boot_on = 1,
-       }
-};
-
-static struct regulator_init_data vsd_init = {
-       .constraints = {
-               .name = "VSD",
-               .min_uV = 1800000,
-               .max_uV = 3150000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE,
-               .boot_on = 1,
-       },
-       .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
-       .consumer_supplies = vsd_consumers,
-};
-
-static struct regulator_init_data vcam_init = {
-       .constraints = {
-               .name = "VCAM",
-               .min_uV = 2500000,
-               .max_uV = 3000000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE |
-                       REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
-               .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-               .boot_on = 1,
-       }
-};
-
-static struct regulator_init_data vgen1_init = {
-       .constraints = {
-               .name = "VGEN1",
-               .min_uV = 1200000,
-               .max_uV = 3150000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-               .boot_on = 1,
-               .always_on = 1,
-       }
-};
-
-static struct regulator_init_data vgen2_init = {
-       .constraints = {
-               .name = "VGEN2",
-               .min_uV = 1200000,
-               .max_uV = 3150000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-               .boot_on = 1,
-               .always_on = 1,
-       }
-};
-
-static struct regulator_init_data vgen3_init = {
-       .constraints = {
-               .name = "VGEN3",
-               .min_uV = 1800000,
-               .max_uV = 2900000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-               .boot_on = 1,
-               .always_on = 1,
-       }
-};
-
-static struct regulator_init_data gpo1_init = {
-       .constraints = {
-               .name = "GPO1",
-       }
-};
-
-static struct regulator_init_data gpo2_init = {
-       .constraints = {
-               .name = "GPO2",
-       }
-};
-
-static struct regulator_init_data gpo3_init = {
-       .constraints = {
-               .name = "GPO3",
-       }
-};
-
-static struct regulator_init_data gpo4_init = {
-       .constraints = {
-               .name = "GPO4",
-       }
-};
-
-static struct regulator_init_data pwgt1_init = {
-       .constraints = {
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .boot_on        = 1,
-       },
-       .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
-       .consumer_supplies = pwgt1_consumer,
-};
-
-static struct regulator_init_data pwgt2_init = {
-       .constraints = {
-               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-               .boot_on        = 1,
-       },
-       .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
-       .consumer_supplies = pwgt2_consumer,
-};
-
-static struct regulator_init_data vcoincell_init = {
-       .constraints = {
-               .name = "COINCELL",
-               .min_uV = 3000000,
-               .max_uV = 3000000,
-               .valid_ops_mask =
-                       REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-       },
-       .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
-       .consumer_supplies = coincell_consumer,
-};
-
-static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
-       { .id = MC13892_SW1,            .init_data =  &sw1_init },
-       { .id = MC13892_SW2,            .init_data =  &sw2_init },
-       { .id = MC13892_SW3,            .init_data =  &sw3_init },
-       { .id = MC13892_SW4,            .init_data =  &sw4_init },
-       { .id = MC13892_SWBST,          .init_data =  &swbst_init },
-       { .id = MC13892_VIOHI,          .init_data =  &viohi_init },
-       { .id = MC13892_VPLL,           .init_data =  &vpll_init },
-       { .id = MC13892_VDIG,           .init_data =  &vdig_init },
-       { .id = MC13892_VSD,            .init_data =  &vsd_init },
-       { .id = MC13892_VUSB2,          .init_data =  &vusb2_init },
-       { .id = MC13892_VVIDEO,         .init_data =  &vvideo_init },
-       { .id = MC13892_VAUDIO,         .init_data =  &vaudio_init },
-       { .id = MC13892_VCAM,           .init_data =  &vcam_init },
-       { .id = MC13892_VGEN1,          .init_data =  &vgen1_init },
-       { .id = MC13892_VGEN2,          .init_data =  &vgen2_init },
-       { .id = MC13892_VGEN3,          .init_data =  &vgen3_init },
-       { .id = MC13892_VUSB,           .init_data =  &vusb_init },
-       { .id = MC13892_GPO1,           .init_data =  &gpo1_init },
-       { .id = MC13892_GPO2,           .init_data =  &gpo2_init },
-       { .id = MC13892_GPO3,           .init_data =  &gpo3_init },
-       { .id = MC13892_GPO4,           .init_data =  &gpo4_init },
-       { .id = MC13892_PWGT1SPI,       .init_data = &pwgt1_init },
-       { .id = MC13892_PWGT2SPI,       .init_data = &pwgt2_init },
-       { .id = MC13892_VCOINCELL,      .init_data = &vcoincell_init },
-};
-
-static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
-       .flags = MC13XXX_USE_RTC,
-       .regulators = {
-               .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
-               .regulators = mx51_efika_regulators,
-       },
-};
-
-static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
-       {
-               .modalias = "m25p80",
-               .max_speed_hz = 25000000,
-               .bus_num = 0,
-               .chip_select = 1,
-               .platform_data = &mx51_efika_spi_flash_data,
-               .irq = -1,
-       },
-       {
-               .modalias = "mc13892",
-               .max_speed_hz = 1000000,
-               .bus_num = 0,
-               .chip_select = 0,
-               .platform_data = &mx51_efika_mc13892_data,
-               .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
-       },
-};
-
-static int mx51_efika_spi_cs[] = {
-       EFIKAMX_SPI_CS0,
-       EFIKAMX_SPI_CS1,
-};
-
-static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
-       .chipselect     = mx51_efika_spi_cs,
-       .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
-};
-
-void __init efika_board_common_init(void)
-{
-       mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
-                                       ARRAY_SIZE(mx51efika_pads));
-       imx51_add_imx_uart(0, &uart_pdata);
-       mx51_efika_usb();
-
-       /* FIXME: comes from original code. check this. */
-       if (mx51_revision() < IMX_CHIP_REVISION_2_0)
-               sw2_init.constraints.state_mem.uV = 1100000;
-       else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
-               sw2_init.constraints.state_mem.uV = 1250000;
-               sw1_init.constraints.state_mem.uV = 1000000;
-       }
-       if (machine_is_mx51_efikasb())
-               vgen1_init.constraints.max_uV = 1200000;
-
-       gpio_request(EFIKAMX_PMIC, "pmic irq");
-       gpio_direction_input(EFIKAMX_PMIC);
-       spi_register_board_info(mx51_efika_spi_board_info,
-               ARRAY_SIZE(mx51_efika_spi_board_info));
-       imx51_add_ecspi(0, &mx51_efika_spi_pdata);
-
-       imx51_add_pata_imx();
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-       get_cpu_op = mx51_get_cpu_op;
-#endif
-}
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
deleted file mode 100644 (file)
index 98052fc..0000000
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- *  Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/suspend.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include "crm_regs.h"
-
-static struct clk *gpc_dvfs_clk;
-
-static int mx5_suspend_prepare(void)
-{
-       return clk_enable(gpc_dvfs_clk);
-}
-
-static int mx5_suspend_enter(suspend_state_t state)
-{
-       switch (state) {
-       case PM_SUSPEND_MEM:
-               mx5_cpu_lp_set(STOP_POWER_OFF);
-               break;
-       case PM_SUSPEND_STANDBY:
-               mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       if (state == PM_SUSPEND_MEM) {
-               local_flush_tlb_all();
-               flush_cache_all();
-
-               /*clear the EMPGC0/1 bits */
-               __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
-               __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
-       }
-       cpu_do_idle();
-       return 0;
-}
-
-static void mx5_suspend_finish(void)
-{
-       clk_disable(gpc_dvfs_clk);
-}
-
-static int mx5_pm_valid(suspend_state_t state)
-{
-       return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
-}
-
-static const struct platform_suspend_ops mx5_suspend_ops = {
-       .valid = mx5_pm_valid,
-       .prepare = mx5_suspend_prepare,
-       .enter = mx5_suspend_enter,
-       .finish = mx5_suspend_finish,
-};
-
-static int __init mx5_pm_init(void)
-{
-       if (gpc_dvfs_clk == NULL)
-               gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
-
-       if (!IS_ERR(gpc_dvfs_clk)) {
-               if (cpu_is_mx51())
-                       suspend_set_ops(&mx5_suspend_ops);
-       } else
-               return -EPERM;
-
-       return 0;
-}
-device_initcall(mx5_pm_init);
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
deleted file mode 100644 (file)
index 144ebeb..0000000
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include "crm_regs.h"
-
-/* set cpu low power mode before WFI instruction. This function is called
-  * mx5 because it can be used for mx50, mx51, and mx53.*/
-void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
-{
-       u32 plat_lpc, arm_srpgcr, ccm_clpcr;
-       u32 empgc0, empgc1;
-       int stop_mode = 0;
-
-       /* always allow platform to issue a deep sleep mode request */
-       plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
-           ~(MXC_CORTEXA8_PLAT_LPC_DSM);
-       ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
-       arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
-       empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
-       empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
-
-       switch (mode) {
-       case WAIT_CLOCKED:
-               break;
-       case WAIT_UNCLOCKED:
-               ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
-               break;
-       case WAIT_UNCLOCKED_POWER_OFF:
-       case STOP_POWER_OFF:
-               plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
-                           | MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
-               if (mode == WAIT_UNCLOCKED_POWER_OFF) {
-                       ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
-                       ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
-                       ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
-                       stop_mode = 0;
-               } else {
-                       ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
-                       ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
-                       ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
-                       ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
-                       stop_mode = 1;
-               }
-               arm_srpgcr |= MXC_SRPGCR_PCR;
-
-               if (tzic_enable_wake(1) != 0)
-                       return;
-               break;
-       case STOP_POWER_ON:
-               ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
-               break;
-       default:
-               printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
-               return;
-       }
-
-       __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
-       __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
-       __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
-
-       /* Enable NEON SRPG for all but MX50TO1.0. */
-       if (mx50_revision() != IMX_CHIP_REVISION_1_0)
-               __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
-
-       if (stop_mode) {
-               empgc0 |= MXC_SRPGCR_PCR;
-               empgc1 |= MXC_SRPGCR_PCR;
-
-               __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
-               __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
-       }
-}
index a08a95107a632f9b1c178c29a55388494d7286bd..fdde4d13d2e8bc7c520fdb1f7c62fd5d451ac891 100644 (file)
@@ -17,25 +17,16 @@ config ARCH_IMX_V4_V5
          and ARMv5 SoCs
 
 config ARCH_IMX_V6_V7
-       bool "i.MX3, i.MX6"
+       bool "i.MX3, i.MX5, i.MX6"
        select AUTO_ZRELADDR if !ZBOOT_ROM
        select ARM_PATCH_PHYS_VIRT
        help
-         This enables support for systems based on the Freescale i.MX3 and i.MX6
-         family.
-
-config ARCH_MX5
-       bool "i.MX50, i.MX51, i.MX53"
-       select AUTO_ZRELADDR
-       select ARM_PATCH_PHYS_VIRT
-       help
-         This enables support for machines using Freescale's i.MX50 and i.MX53
-         processors.
+         This enables support for systems based on the Freescale i.MX3, i.MX5
+         and i.MX6 family.
 
 endchoice
 
 source "arch/arm/mach-imx/Kconfig"
-source "arch/arm/mach-mx5/Kconfig"
 
 endmenu