drm/nouveau/gr/nv3x: fix instobj write offsets in gr setup

commit d0e62ef6ed257715a88d0e5d7cd850a1695429e2 upstream.

This should fix some unaligned access warnings. This is also likely to
fix non-descript issues on nv30/nv34 as a result of incorrect channel
setup.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96836
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
index 69de8c6259febb8dab996b66eee38b6a9e21a868..f1e15a4d4f64fe95a2fe38a1fa2566ba376e2698 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
@@ -76,8 +76,8 @@ nv30_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
                nvkm_wo32(chan->inst, i, 0x00040004);
        for (i = 0x1f18; i <= 0x3088 ; i += 16) {
                nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
-               nvkm_wo32(chan->inst, i + 1, 0x0436086c);
-               nvkm_wo32(chan->inst, i + 2, 0x000c001b);
+               nvkm_wo32(chan->inst, i + 4, 0x0436086c);
+               nvkm_wo32(chan->inst, i + 8, 0x000c001b);
        }
        for (i = 0x30b8; i < 0x30c8; i += 4)
                nvkm_wo32(chan->inst, i, 0x0000ffff);

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
index 2207dac23981a10f4b01dde77ea47f1df84f9723..300f5ed5de0b0fe618e1707aa0d78b12b62b370f 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
@@ -75,8 +75,8 @@ nv34_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
                nvkm_wo32(chan->inst, i, 0x00040004);
        for (i = 0x15ac; i <= 0x271c ; i += 16) {
                nvkm_wo32(chan->inst, i + 0, 0x10700ff9);
-               nvkm_wo32(chan->inst, i + 1, 0x0436086c);
-               nvkm_wo32(chan->inst, i + 2, 0x000c001b);
+               nvkm_wo32(chan->inst, i + 4, 0x0436086c);
+               nvkm_wo32(chan->inst, i + 8, 0x000c001b);
        }
        for (i = 0x274c; i < 0x275c; i += 4)
                nvkm_wo32(chan->inst, i, 0x0000ffff);