ARM: dts: apq8064: add missing i2c2 pinctrl info

This patch adds missing i2c2 pinctrl information in i2c2 node.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index 0b7b10e8ba5cce2dc9aa991fee65bf2f65457bf3..0a342d31c0a2d1e73be5af48a9103b88a94c9b2b 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -39,6 +39,32 @@
                };
        };
 
+       i2c2_pins: i2c2 {
+               mux {
+                       pins = "gpio24", "gpio25";
+                       function = "gsbi2";
+               };
+
+               pinconf {
+                       pins = "gpio24", "gpio25";
+                       drive-strength = <16>;
+                       bias-disable;
+               };
+       };
+
+       i2c2_pins_sleep: i2c2_pins_sleep {
+               mux {
+                       pins = "gpio24", "gpio25";
+                       function = "gpio";
+               };
+
+               pinconf {
+                       pins = "gpio24", "gpio25";
+                       drive-strength = <2>;
+                       bias-disable = <0>;
+               };
+       };
+
        i2c3_pins: i2c3 {
                mux {
                        pins = "gpio8", "gpio9";

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index d46d460d621e4a459731fcd90efcfee358c4805c..20da87306bb3f78fa9e5276163202342de47f04b 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -255,6 +255,8 @@
                        gsbi2_i2c: i2c@124a0000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x124a0000 0x1000>;
+                               pinctrl-0 = <&i2c2_pins &i2c2_pins_sleep>;
+                               pinctrl-names = "default", "sleep";
                                interrupts = <0 196 IRQ_TYPE_NONE>;
                                clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
                                clock-names = "core", "iface";