PMUCAL_SEQ_DESC(PMUCAL_WRITE, "ctrl_ovr", 0x12200000, 0x0000, (0x1 << 3), (0x0 << 3), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CG_CONTROL", 0x10440000, 0x001c, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CG_CONTROL", 0x10540000, 0x001c, (0xffffffff << 0), (0xFFFFFFFF << 0), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_SOC_DOWN_IRQ_OPTION1__DOWN_STATE", 0x11860000, 0x8204, (0x1 << 15), (0x1 << 15), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_SOC_DOWN_IRQ_OPTION0__UP_STATE", 0x11860000, 0x8210, (0x1 << 2), (0x1 << 2), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_DOWN_IRQ_OPTION1__DOWN_STATE", 0x11860000, 0x8224, (0x1 << 15), (0x1 << 15), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_DOWN_IRQ_OPTION0__UP_STATE", 0x11860000, 0x8230, (0x1 << 2), (0x1 << 2), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WDTRESET_LPI", 0x11860000, 0x0418, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DIS_IRQ_AUD_CA7_LOCAL", 0x11860000, 0x10A8, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GNSS_CTRL_NS", 0x11860000, 0x0040, (0x1 << 20), (0x0 << 20), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WLBT_CTRL_NS", 0x11860000, 0x0050, (0x1 << 20), (0x0 << 20), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "OSC_CON0_OSC", 0x11860000, 0x0c00, (0x1 << 31), (0x1 << 31), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_RAW_WAIT, "OSC_CON0_OSC", 0x11860000, 0x0c00, (0x1 << 29), (0x1 << 29), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "OSC_CON0_OSC", 0x11860000, 0x0c00, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CTRL_REFCLK_PMU", 0x11860000, 0x0c1c, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CTRL_REFCLK_OSC__MUX_SEL", 0x11860000, 0x0c18, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PPC_CPUCL0__USE_PPC_BY_SW", 0x11860000, 0x0740, (0x1 << 21), (0x0 << 21), 0, 0, 0xffffffff, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PPC_CPUCL0__MANUAL_CONTROL_USE_PPC ", 0x11860000, 0x0740, (0x1 << 20), (0x1 << 20), 0, 0, 0xffffffff, 0),
};
-unsigned int pmucal_lpm_init_size = 128;
+unsigned int pmucal_lpm_init_size = 139;
/* individual sequence descriptor for each power mode - enter, exit, early_wakeup */
struct pmucal_seq enter_sicd[] = {
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0", 0x11860000, 0x1000, (0xf << 0), (0xF << 0), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_SOC_UP_IRQ_OPTION2__UP_STATE ", 0x11860000, 0x8210, (0x1 << 4), (0x0 << 4), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "USB_OPTION", 0x11860000, 0x40C8, (0x1 << 30), (0x0 << 30), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TOP_BUS_MIF_OPTION", 0x11860000, 0x2C28, (0x1 << 5), (0x0 << 5), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x0 << 0), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_CONFIGURATION", 0x11860000, 0x0200, (0x1 << 16), (0x0 << 16), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_CONFIGURATION", 0x11860000, 0x0240, (0x1 << 16), (0x0 << 16), 0, 0, 0xffffffff, 0),
};
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G2D_OPTION[31] (EMULATION)", 0x11860000, 0x40C8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "VIPX_OPTION[31] (EMULATION)", 0x11860000, 0x40E8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_OPTION", 0x11860000, 0x0248, (0x1 << 0), (0x0 << 0), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x0 << 0), 0, 0, 0, 0),
};
struct pmucal_seq earlywkup_sicd[] = {
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_SOC_UP_IRQ_OPTION2__UP_STATE ", 0x11860000, 0x8210, (0x1 << 4), (0x1 << 4), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "USB_OPTION", 0x11860000, 0x40C8, (0x1 << 30), (0x0 << 30), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TOP_BUS_MIF_OPTION", 0x11860000, 0x2C28, (0x1 << 5), (0x0 << 5), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x0 << 0), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_CONFIGURATION", 0x11860000, 0x0200, (0x1 << 16), (0x0 << 16), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_CONFIGURATION", 0x11860000, 0x0240, (0x1 << 16), (0x0 << 16), 0, 0, 0xffffffff, 0),
};
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G2D_OPTION[31] (EMULATION)", 0x11860000, 0x40C8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "VIPX_OPTION[31] (EMULATION)", 0x11860000, 0x40E8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_OPTION", 0x11860000, 0x0248, (0x1 << 0), (0x0 << 0), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x0 << 0), 0, 0, 0, 0),
};
struct pmucal_seq earlywkup_stop[] = {
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_SOC_UP_IRQ_OPTION2__UP_STATE ", 0x11860000, 0x8210, (0x1 << 4), (0x1 << 4), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "USB_OPTION", 0x11860000, 0x40C8, (0x1 << 30), (0x0 << 30), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TOP_BUS_MIF_OPTION", 0x11860000, 0x2C28, (0x1 << 5), (0x1 << 5), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x3 << 0), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_CONFIGURATION", 0x11860000, 0x0200, (0x1 << 16), (0x0 << 16), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_CONFIGURATION", 0x11860000, 0x0240, (0x1 << 16), (0x0 << 16), 0, 0, 0xffffffff, 0),
};
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G2D_OPTION[31] (EMULATION)", 0x11860000, 0x40C8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "VIPX_OPTION[31] (EMULATION)", 0x11860000, 0x40E8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_OPTION", 0x11860000, 0x0248, (0x1 << 0), (0x0 << 0), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x0 << 0), 0, 0, 0, 0),
};
struct pmucal_seq earlywkup_sleep[] = {
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_SOC_UP_IRQ_OPTION2__UP_STATE ", 0x11860000, 0x8210, (0x1 << 4), (0x1 << 4), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "USB_OPTION", 0x11860000, 0x40C8, (0x1 << 30), (0x1 << 30), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TOP_BUS_MIF_OPTION", 0x11860000, 0x2C28, (0x1 << 5), (0x1 << 5), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x3 << 0), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_CONFIGURATION", 0x11860000, 0x0200, (0x1 << 16), (0x0 << 16), 0, 0, 0xffffffff, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_CONFIGURATION", 0x11860000, 0x0240, (0x1 << 16), (0x0 << 16), 0, 0, 0xffffffff, 0),
};
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G2D_OPTION[31] (EMULATION)", 0x11860000, 0x40C8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "VIPX_OPTION[31] (EMULATION)", 0x11860000, 0x40E8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_OPTION", 0x11860000, 0x0248, (0x1 << 0), (0x0 << 0), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x0 << 0), 0, 0, 0, 0),
};
struct pmucal_seq earlywkup_sleep_usb_on[] = {
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_SOC_UP_IRQ_OPTION2__UP_STATE ", 0x11860000, 0x8210, (0x1 << 4), (0x1 << 4), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "USB_OPTION", 0x11860000, 0x40C8, (0x1 << 30), (0x0 << 30), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TOP_BUS_MIF_OPTION", 0x11860000, 0x2C28, (0x1 << 5), (0x1 << 5), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x3 << 0), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_CONFIGURATION", 0x11860000, 0x0200, (0x1 << 16), (0x0 << 16), 0, 0, 0xffffffff, 0),
};
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G2D_OPTION[31] (EMULATION)", 0x11860000, 0x40C8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "VIPX_OPTION[31] (EMULATION)", 0x11860000, 0x40E8, (0x1 << 31), (0x0 << 31), 0, 0, 0, 0),
PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CENTRAL_SEQ_MIF_OPTION", 0x11860000, 0x0248, (0x1 << 0), (0x0 << 0), 0, 0, 0, 0),
+ PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP7_INTR_BID_ENABL", 0x11870000, 0x0700, (0x3 << 0), (0x0 << 0), 0, 0, 0, 0),
};
struct pmucal_seq earlywkup_sleep_aud_on[] = {