config MACH_NSLU2
bool
prompt "Linksys NSLU2"
+ select PCI
help
Say 'Y' here if you want your kernel to support Linksys's
NSLU2 NAS device. For more information on this platform,
config ARCH_AVILA
bool "Avila"
+ select PCI
help
Say 'Y' here if you want your kernel to support the Gateworks
Avila Network Platform. For more information on this platform,
config ARCH_ADI_COYOTE
bool "Coyote"
+ select PCI
help
Say 'Y' here if you want your kernel to support the ADI
Engineering Coyote Gateway Reference Platform. For more
config ARCH_IXDP425
bool "IXDP425"
+ select PCI
help
Say 'Y' here if you want your kernel to support Intel's
IXDP425 Development Platform (Also known as Richfield).
config MACH_IXDPG425
bool "IXDPG425"
+ select PCI
help
Say 'Y' here if you want your kernel to support Intel's
IXDPG425 Development Platform (Also known as Montajade).
config MACH_IXDP465
bool "IXDP465"
+ select PCI
help
Say 'Y' here if you want your kernel to support Intel's
IXDP465 Development Platform (Also known as BMP).
config MACH_NAS100D
bool
prompt "NAS100D"
+ select PCI
help
Say 'Y' here if you want your kernel to support Iomega's
NAS 100d device. For more information on this platform,
config MACH_GTWX5715
bool "Gemtek WX5715 (Linksys WRV54G)"
depends on ARCH_IXP4XX
+ select PCI
help
This board is currently inside the Linksys WRV54G Gateways.
"High Speed" UART is n/c (as far as I can tell)
20 Pin ARM/Xscale JTAG interface on J2
-
comment "IXP4xx Options"
+config DMABOUNCE
+ bool
+ default y
+ depends on PCI
+
config IXP4XX_INDIRECT_PCI
bool "Use indirect PCI memory access"
+ depends on PCI
help
IXP4xx provides two methods of accessing PCI memory space:
# Makefile for the linux kernel.
#
-obj-y += common.o common-pci.o
+obj-y += common.o
+obj-$(CONFIG_PCI) += common-pci.o
obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o ixdp425-setup.o
obj-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o coyote-setup.o
obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o coyote-setup.o
#endif
+#ifndef CONFIG_PCI
+
+#define __io(v) v
+
+#else
+
/*
* IXP4xx does not have a transparent cpu -> PCI I/O translation
* window. Instead, it has a set of registers that must be tweaked
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
#define ioport_unmap(addr)
+#endif // !CONFIG_PCI
#endif // __ASM_ARM_ARCH_IO_H