drm/i915: Kill most of the FBC register save/restore

We will anyway re-enable FBC normally after resume, so trying to save
and restore the register makes little sense.

We do need to preserve the FBC1 interval bits in FBC_CONTROL since
we only initialize them during driver load, and try to preserve them
after that.

v2: s/I915_HAS_FBC/HAS_FBC/ and fix the check for gen4

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 20f0e780584bf2d9e284b5668c4162be72f5f48a..7693f96023f69bd2e4dbdfe4965cfa40c1e160c1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -859,11 +859,7 @@ struct i915_suspend_saved_registers {
        u32 savePFIT_CONTROL;
        u32 save_palette_a[256];
        u32 save_palette_b[256];
-       u32 saveDPFC_CB_BASE;
-       u32 saveFBC_CFB_BASE;
-       u32 saveFBC_LL_BASE;
        u32 saveFBC_CONTROL;
-       u32 saveFBC_CONTROL2;
        u32 saveIER;
        u32 saveIIR;
        u32 saveIMR;

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index e6c90d1382b3499e282384099ef2fc1e1c3a6d35..56785e8fb2eb5f7e209b8713f3815b4c5ecbcf22 100644 (file)
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -236,19 +236,9 @@ static void i915_save_display(struct drm_device *dev)
                dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
        }
 
-       /* Only regfile.save FBC state on the platform that supports FBC */
-       if (HAS_FBC(dev)) {
-               if (HAS_PCH_SPLIT(dev)) {
-                       dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
-               } else if (IS_GM45(dev)) {
-                       dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
-               } else {
-                       dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
-                       dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
-                       dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
-                       dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
-               }
-       }
+       /* save FBC interval */
+       if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
+               dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 
        if (!drm_core_check_feature(dev, DRIVER_MODESET))
                i915_save_vga(dev);
@@ -300,18 +290,10 @@ static void i915_restore_display(struct drm_device *dev)
 
        /* only restore FBC info on the platform that supports FBC*/
        intel_disable_fbc(dev);
-       if (HAS_FBC(dev)) {
-               if (HAS_PCH_SPLIT(dev)) {
-                       I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
-               } else if (IS_GM45(dev)) {
-                       I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
-               } else {
-                       I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
-                       I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
-                       I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
-                       I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
-               }
-       }
+
+       /* restore FBC interval */
+       if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
+               I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
 
        if (!drm_core_check_feature(dev, DRIVER_MODESET))
                i915_restore_vga(dev);