#define SH_CACHE_VALID (1LL<<0)
#define SH_CACHE_UPDATED (1LL<<57)
+/* Unimplemented compat bits.. */
+#define SH_CACHE_COMBINED 0
+#define SH_CACHE_ASSOC 0
+
/* Cache flags */
#define SH_CACHE_MODE_WT (1LL<<0)
#define SH_CACHE_MODE_WB (1LL<<1)
#ifndef __ASM_SH_PROCESSOR_H
#define __ASM_SH_PROCESSOR_H
+#include <asm/cpu-features.h>
+
/*
* CPU type and hardware bug flags. Kept separately for each CPU.
*
#include <asm/types.h>
#include <asm/cache.h>
#include <asm/ptrace.h>
-#include <asm/cpu-features.h>
/*
* Default implementation of macro that returns current
/* TLB info */
struct tlb_info itlb;
struct tlb_info dtlb;
-};
-extern struct sh_cpuinfo boot_cpu_data;
+ unsigned long flags;
+};
-#define cpu_data (&boot_cpu_data)
-#define current_cpu_data boot_cpu_data
+extern struct sh_cpuinfo cpu_data[];
+#define boot_cpu_data cpu_data[0]
+#define current_cpu_data cpu_data[smp_processor_id()]
+#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
#endif