/*
* Driver for the Renesas RCar I2C unit
*
- * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
- * Copyright (C) 2011-2015 Renesas Electronics Corporation
+ * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
*
* Copyright (C) 2012-14 Renesas Solutions Corp.
* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
* This file is based on the drivers/i2c/busses/i2c-sh7760.c
* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
*
+ * This file used out-of-tree driver i2c-rcar.c
+ * Copyright (C) 2011-2012 Renesas Electronics Corporation
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
+#include <linux/spinlock.h>
/* register offsets */
#define ICSCR 0x00 /* slave ctrl */
#define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
#define RCAR_BUS_PHASE_DATA (MDBS | MIE)
-#define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
#define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
#define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
#define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF)
#define ID_LAST_MSG (1 << 0)
+#define ID_IOERROR (1 << 1)
#define ID_DONE (1 << 2)
#define ID_ARBLOST (1 << 3)
#define ID_NACK (1 << 4)
struct rcar_i2c_priv {
void __iomem *io;
struct i2c_adapter adap;
- struct i2c_msg *msg;
- int msgs_left;
+ struct i2c_msg *msg;
struct clk *clk;
+ spinlock_t lock;
wait_queue_head_t wait;
int pos;
{
/* reset master mode */
rcar_i2c_write(priv, ICMIER, 0);
- rcar_i2c_write(priv, ICMCR, MDBS);
+ rcar_i2c_write(priv, ICMCR, 0);
rcar_i2c_write(priv, ICMSR, 0);
- /* start clock */
- rcar_i2c_write(priv, ICCCR, priv->icccr);
+ rcar_i2c_write(priv, ICMAR, 0);
}
static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
- /* keep icccr value */
+ /*
+ * keep icccr value
+ */
priv->icccr = scgd << cdf_width | cdf;
return 0;
{
int read = !!rcar_i2c_is_recv(priv);
- priv->pos = 0;
- priv->flags = 0;
- if (priv->msgs_left == 1)
- rcar_i2c_flags_set(priv, ID_LAST_MSG);
-
rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
rcar_i2c_write(priv, ICMSR, 0);
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
}
-static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
-{
- priv->msg++;
- priv->msgs_left--;
- rcar_i2c_prepare_msg(priv);
-}
-
/*
* interrupt functions
*/
{
struct i2c_msg *msg = priv->msg;
- /* FIXME: sometimes, unknown interrupt happened. Do nothing */
+ /*
+ * FIXME
+ * sometimes, unknown interrupt happened.
+ * Do nothing
+ */
if (!(msr & MDE))
return 0;
+ /*
+ * If address transfer phase finished,
+ * goto data phase.
+ */
+ if (msr & MAT)
+ rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
+
if (priv->pos < msg->len) {
/*
* Prepare next data to ICRXTX register.
* [ICRXTX] -> [SHIFT] -> [I2C bus]
*/
- if (priv->flags & ID_LAST_MSG) {
+ if (priv->flags & ID_LAST_MSG)
/*
* If current msg is the _LAST_ msg,
* prepare stop condition here.
* ID_DONE will be set on STOP irq.
*/
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
- } else {
- rcar_i2c_next_msg(priv);
- return 0;
- }
+ else
+ /*
+ * If current msg is _NOT_ last msg,
+ * it doesn't call stop phase.
+ * thus, there is no STOP irq.
+ * return ID_DONE here.
+ */
+ return ID_DONE;
}
rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
{
struct i2c_msg *msg = priv->msg;
- /* FIXME: sometimes, unknown interrupt happened. Do nothing */
+ /*
+ * FIXME
+ * sometimes, unknown interrupt happened.
+ * Do nothing
+ */
if (!(msr & MDR))
return 0;
if (msr & MAT) {
- /* Address transfer phase finished, but no data at this point. */
+ /*
+ * Address transfer phase finished,
+ * but, there is no data at this point.
+ * Do nothing.
+ */
} else if (priv->pos < msg->len) {
- /* get received data */
+ /*
+ * get received data
+ */
msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
priv->pos++;
}
/*
- * If next received data is the _LAST_, go to STOP phase. Might be
- * overwritten by REP START when setting up a new msg. Not elegant
- * but the only stable sequence for REP START I have found so far.
+ * If next received data is the _LAST_,
+ * go to STOP phase,
+ * otherwise, go to DATA phase.
*/
if (priv->pos + 1 >= msg->len)
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
-
- if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
- rcar_i2c_next_msg(priv);
else
- rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
+ rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
+
+ rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
return 0;
}
static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
{
struct rcar_i2c_priv *priv = ptr;
- u32 msr, val;
+ irqreturn_t result = IRQ_HANDLED;
+ u32 msr;
- /* Clear START or STOP as soon as we can */
- val = rcar_i2c_read(priv, ICMCR);
- rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
+ /*-------------- spin lock -----------------*/
+ spin_lock(&priv->lock);
+
+ if (rcar_i2c_slave_irq(priv))
+ goto exit;
msr = rcar_i2c_read(priv, ICMSR);
/* Only handle interrupts that are currently enabled */
msr &= rcar_i2c_read(priv, ICMIER);
if (!msr) {
- if (rcar_i2c_slave_irq(priv))
- return IRQ_HANDLED;
-
- return IRQ_NONE;
+ result = IRQ_NONE;
+ goto exit;
}
/* Arbitration lost */
/* Nack */
if (msr & MNR) {
- /* HW automatically sends STOP after received NACK */
+ /* go to stop phase */
+ rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
rcar_i2c_flags_set(priv, ID_NACK);
goto out;
/* Stop */
if (msr & MST) {
- priv->msgs_left--; /* The last message also made it */
rcar_i2c_flags_set(priv, ID_DONE);
goto out;
}
wake_up(&priv->wait);
}
- return IRQ_HANDLED;
+exit:
+ spin_unlock(&priv->lock);
+ /*-------------- spin unlock -----------------*/
+
+ return result;
}
static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
{
struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
struct device *dev = rcar_i2c_priv_to_dev(priv);
+ unsigned long flags;
int i, ret;
- long time_left;
+ long timeout;
pm_runtime_get_sync(dev);
+ /*-------------- spin lock -----------------*/
+ spin_lock_irqsave(&priv->lock, flags);
+
+ rcar_i2c_init(priv);
+ /* start clock */
+ rcar_i2c_write(priv, ICCCR, priv->icccr);
+
+ spin_unlock_irqrestore(&priv->lock, flags);
+ /*-------------- spin unlock -----------------*/
+
ret = rcar_i2c_bus_barrier(priv);
if (ret < 0)
goto out;
/* This HW can't send STOP after address phase */
if (msgs[i].len == 0) {
ret = -EOPNOTSUPP;
- goto out;
+ break;
}
- }
- /* init data */
- priv->msg = msgs;
- priv->msgs_left = num;
-
- rcar_i2c_prepare_msg(priv);
-
- time_left = wait_event_timeout(priv->wait,
- rcar_i2c_flags_has(priv, ID_DONE),
- num * adap->timeout);
- if (!time_left) {
- rcar_i2c_init(priv);
- ret = -ETIMEDOUT;
- } else if (rcar_i2c_flags_has(priv, ID_NACK)) {
- ret = -ENXIO;
- } else if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
- ret = -EAGAIN;
- } else {
- ret = num - priv->msgs_left; /* The number of transfer */
+ /*-------------- spin lock -----------------*/
+ spin_lock_irqsave(&priv->lock, flags);
+
+ /* init each data */
+ priv->msg = &msgs[i];
+ priv->pos = 0;
+ priv->flags = 0;
+ if (i == num - 1)
+ rcar_i2c_flags_set(priv, ID_LAST_MSG);
+
+ rcar_i2c_prepare_msg(priv);
+
+ spin_unlock_irqrestore(&priv->lock, flags);
+ /*-------------- spin unlock -----------------*/
+
+ timeout = wait_event_timeout(priv->wait,
+ rcar_i2c_flags_has(priv, ID_DONE),
+ adap->timeout);
+ if (!timeout) {
+ ret = -ETIMEDOUT;
+ break;
+ }
+
+ if (rcar_i2c_flags_has(priv, ID_NACK)) {
+ ret = -ENXIO;
+ break;
+ }
+
+ if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
+ ret = -EAGAIN;
+ break;
+ }
+
+ if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
+ ret = -EIO;
+ break;
+ }
+
+ ret = i + 1; /* The number of transfer */
}
out:
pm_runtime_put(dev);
if (IS_ERR(priv->io))
return PTR_ERR(priv->io);
- rcar_i2c_init(priv);
-
irq = platform_get_irq(pdev, 0);
init_waitqueue_head(&priv->wait);
+ spin_lock_init(&priv->lock);
adap = &priv->adap;
adap->nr = pdev->id;
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff