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ath9k_hw: Fix PLL initialization for AR9485.
authorVivek Natarajan <vnatarajan@atheros.com>
Thu, 10 Mar 2011 05:35:42 +0000 (11:05 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 11 Mar 2011 19:15:36 +0000 (14:15 -0500)
Increase the delay to make sure the initialization of pll
passes.

Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/hw.c patch | blob | blame | history

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 9a3438174f862d0bcfbffa44db6046c0d6169434..338b07502f1adc5621c60815a8f5ce8c0e0345e6 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -701,7 +701,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
                              AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
 
                REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
-               udelay(100);
+               udelay(1000);
 
                REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
 
@@ -713,7 +713,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
                REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
                              AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
                REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
-               udelay(110);
+               udelay(1000);
        }
 
        pll = ath9k_hw_compute_pll_control(ah, chan);