clk: rockchip: fix typo in rk3188 spdif_frac parent
authorJohan Jonker <jbx9999@hotmail.com>
Sat, 3 Nov 2018 22:54:13 +0000 (23:54 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 9 Jan 2019 15:16:44 +0000 (16:16 +0100)
commit 8b19faf6fae2867e2c177212c541e8ae36aa4d32 upstream.

Fix typo in common_clk_branches.
Make spdif_pre parent of spdif_frac.

Fixes: 667464208989 ("clk: rockchip: include downstream muxes into fractional dividers")
Cc: stable@vger.kernel.org
Signed-off-by: Johan Jonker <jbx9999@hotmail.com>
Acked-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/rockchip/clk-rk3188.c

index d0e722a0e8cff9afb79f7c22535042fe2332ce61..523378d1396e87289c7afc80fd29b5e73895096b 100644 (file)
@@ -381,7 +381,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
        COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
                        RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
                        RK2928_CLKGATE_CON(0), 13, GFLAGS),
-       COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pll", CLK_SET_RATE_PARENT,
+       COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
                        RK2928_CLKSEL_CON(9), 0,
                        RK2928_CLKGATE_CON(0), 14, GFLAGS,
                        &common_spdif_fracmux),