drm/i915: Parametrize AUX registers

v2: Keep some MISSING_CASE() stuff (Jani)
    s/-1/-PIPE_B/ in the register macro
    Fix typo in patch subject
v3: Use PORT_B registers for invalid ports in g4x_aux_ctl_reg() (Jani)
v4: Reorder patches (Chris)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com> (v3)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v3)
Link: http://patchwork.freedesktop.org/patch/msgid/1447266856-30249-4-git-send-email-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b24993319dd482ea9af95227449c15bc7f02bd3..81dd27a601f9075e6171ed6b0540b77c873a68e2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3100,11 +3100,7 @@ enum skl_disp_power_wells {
 #define   EDP_PSR_IDLE_FRAME_SHIFT             0
 
 #define EDP_PSR_AUX_CTL(dev)                   (EDP_PSR_BASE(dev) + 0x10)
-#define EDP_PSR_AUX_DATA1(dev)                 (EDP_PSR_BASE(dev) + 0x14)
-#define EDP_PSR_AUX_DATA2(dev)                 (EDP_PSR_BASE(dev) + 0x18)
-#define EDP_PSR_AUX_DATA3(dev)                 (EDP_PSR_BASE(dev) + 0x1c)
-#define EDP_PSR_AUX_DATA4(dev)                 (EDP_PSR_BASE(dev) + 0x20)
-#define EDP_PSR_AUX_DATA5(dev)                 (EDP_PSR_BASE(dev) + 0x24)
+#define EDP_PSR_AUX_DATA(dev, i)               (EDP_PSR_BASE(dev) + 0x14 + (i) * 4) /* 5 registers */
 
 #define EDP_PSR_STATUS_CTL(dev)                        (EDP_PSR_BASE(dev) + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK            (7<<29)
@@ -4232,33 +4228,36 @@ enum skl_disp_power_wells {
  * is 20 bytes in each direction, hence the 5 fixed
  * data registers
  */
-#define DPA_AUX_CH_CTL                 0x64010
-#define DPA_AUX_CH_DATA1               0x64014
-#define DPA_AUX_CH_DATA2               0x64018
-#define DPA_AUX_CH_DATA3               0x6401c
-#define DPA_AUX_CH_DATA4               0x64020
-#define DPA_AUX_CH_DATA5               0x64024
-
-#define DPB_AUX_CH_CTL                 0x64110
-#define DPB_AUX_CH_DATA1               0x64114
-#define DPB_AUX_CH_DATA2               0x64118
-#define DPB_AUX_CH_DATA3               0x6411c
-#define DPB_AUX_CH_DATA4               0x64120
-#define DPB_AUX_CH_DATA5               0x64124
-
-#define DPC_AUX_CH_CTL                 0x64210
-#define DPC_AUX_CH_DATA1               0x64214
-#define DPC_AUX_CH_DATA2               0x64218
-#define DPC_AUX_CH_DATA3               0x6421c
-#define DPC_AUX_CH_DATA4               0x64220
-#define DPC_AUX_CH_DATA5               0x64224
-
-#define DPD_AUX_CH_CTL                 0x64310
-#define DPD_AUX_CH_DATA1               0x64314
-#define DPD_AUX_CH_DATA2               0x64318
-#define DPD_AUX_CH_DATA3               0x6431c
-#define DPD_AUX_CH_DATA4               0x64320
-#define DPD_AUX_CH_DATA5               0x64324
+#define _DPA_AUX_CH_CTL                        0x64010
+#define _DPA_AUX_CH_DATA1              0x64014
+#define _DPA_AUX_CH_DATA2              0x64018
+#define _DPA_AUX_CH_DATA3              0x6401c
+#define _DPA_AUX_CH_DATA4              0x64020
+#define _DPA_AUX_CH_DATA5              0x64024
+
+#define _DPB_AUX_CH_CTL                        0x64110
+#define _DPB_AUX_CH_DATA1              0x64114
+#define _DPB_AUX_CH_DATA2              0x64118
+#define _DPB_AUX_CH_DATA3              0x6411c
+#define _DPB_AUX_CH_DATA4              0x64120
+#define _DPB_AUX_CH_DATA5              0x64124
+
+#define _DPC_AUX_CH_CTL                        0x64210
+#define _DPC_AUX_CH_DATA1              0x64214
+#define _DPC_AUX_CH_DATA2              0x64218
+#define _DPC_AUX_CH_DATA3              0x6421c
+#define _DPC_AUX_CH_DATA4              0x64220
+#define _DPC_AUX_CH_DATA5              0x64224
+
+#define _DPD_AUX_CH_CTL                        0x64310
+#define _DPD_AUX_CH_DATA1              0x64314
+#define _DPD_AUX_CH_DATA2              0x64318
+#define _DPD_AUX_CH_DATA3              0x6431c
+#define _DPD_AUX_CH_DATA4              0x64320
+#define _DPD_AUX_CH_DATA5              0x64324
+
+#define DP_AUX_CH_CTL(port)    _PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
+#define DP_AUX_CH_DATA(port, i)        (_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 #define   DP_AUX_CH_CTL_SEND_BUSY          (1 << 31)
 #define   DP_AUX_CH_CTL_DONE               (1 << 30)
@@ -6609,28 +6608,31 @@ enum skl_disp_power_wells {
 #define BXT_PP_OFF_DELAYS(n)   _PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
 
 #define PCH_DP_B               0xe4100
-#define PCH_DPB_AUX_CH_CTL     0xe4110
-#define PCH_DPB_AUX_CH_DATA1   0xe4114
-#define PCH_DPB_AUX_CH_DATA2   0xe4118
-#define PCH_DPB_AUX_CH_DATA3   0xe411c
-#define PCH_DPB_AUX_CH_DATA4   0xe4120
-#define PCH_DPB_AUX_CH_DATA5   0xe4124
+#define _PCH_DPB_AUX_CH_CTL    0xe4110
+#define _PCH_DPB_AUX_CH_DATA1  0xe4114
+#define _PCH_DPB_AUX_CH_DATA2  0xe4118
+#define _PCH_DPB_AUX_CH_DATA3  0xe411c
+#define _PCH_DPB_AUX_CH_DATA4  0xe4120
+#define _PCH_DPB_AUX_CH_DATA5  0xe4124
 
 #define PCH_DP_C               0xe4200
-#define PCH_DPC_AUX_CH_CTL     0xe4210
-#define PCH_DPC_AUX_CH_DATA1   0xe4214
-#define PCH_DPC_AUX_CH_DATA2   0xe4218
-#define PCH_DPC_AUX_CH_DATA3   0xe421c
-#define PCH_DPC_AUX_CH_DATA4   0xe4220
-#define PCH_DPC_AUX_CH_DATA5   0xe4224
+#define _PCH_DPC_AUX_CH_CTL    0xe4210
+#define _PCH_DPC_AUX_CH_DATA1  0xe4214
+#define _PCH_DPC_AUX_CH_DATA2  0xe4218
+#define _PCH_DPC_AUX_CH_DATA3  0xe421c
+#define _PCH_DPC_AUX_CH_DATA4  0xe4220
+#define _PCH_DPC_AUX_CH_DATA5  0xe4224
 
 #define PCH_DP_D               0xe4300
-#define PCH_DPD_AUX_CH_CTL     0xe4310
-#define PCH_DPD_AUX_CH_DATA1   0xe4314
-#define PCH_DPD_AUX_CH_DATA2   0xe4318
-#define PCH_DPD_AUX_CH_DATA3   0xe431c
-#define PCH_DPD_AUX_CH_DATA4   0xe4320
-#define PCH_DPD_AUX_CH_DATA5   0xe4324
+#define _PCH_DPD_AUX_CH_CTL    0xe4310
+#define _PCH_DPD_AUX_CH_DATA1  0xe4314
+#define _PCH_DPD_AUX_CH_DATA2  0xe4318
+#define _PCH_DPD_AUX_CH_DATA3  0xe431c
+#define _PCH_DPD_AUX_CH_DATA4  0xe4320
+#define _PCH_DPD_AUX_CH_DATA5  0xe4324
+
+#define PCH_DP_AUX_CH_CTL(port)                _PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
+#define PCH_DP_AUX_CH_DATA(port, i)    (_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
 
 /* CPT */
 #define  PORT_TRANS_A_SEL_CPT  0

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index df2a2d21933cc8c054f17a6940da1e923c08d5e5..b07660cbbeff7f8bb85203e178c0b7c50338d6f2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1023,7 +1023,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        enum port port = intel_dig_port->port;
        struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
-       uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
+       uint32_t porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_A);
        int ret;
 
        /* On SKL we don't have Aux for port E so we rely on VBT to set
@@ -1032,32 +1032,28 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
        if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) {
                switch (info->alternate_aux_channel) {
                case DP_AUX_B:
-                       porte_aux_ctl_reg = DPB_AUX_CH_CTL;
+                       porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_B);
                        break;
                case DP_AUX_C:
-                       porte_aux_ctl_reg = DPC_AUX_CH_CTL;
+                       porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_C);
                        break;
                case DP_AUX_D:
-                       porte_aux_ctl_reg = DPD_AUX_CH_CTL;
+                       porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_D);
                        break;
                case DP_AUX_A:
                default:
-                       porte_aux_ctl_reg = DPA_AUX_CH_CTL;
+                       porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_A);
                }
        }
 
        switch (port) {
        case PORT_A:
-               intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
+               intel_dp->aux_ch_ctl_reg = DP_AUX_CH_CTL(port);
                break;
        case PORT_B:
-               intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
-               break;
        case PORT_C:
-               intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
-               break;
        case PORT_D:
-               intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
+               intel_dp->aux_ch_ctl_reg = PCH_DP_AUX_CH_CTL(port);
                break;
        case PORT_E:
                intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 213581c215b300c6bd3e5cb43cf890d7a917f4bb..ff667189bf90ab3f892fda0c14336b0d69b9ac6a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -166,6 +166,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
                [3] = 1 - 1,
                [4] = DP_SET_POWER_D0,
        };
+       enum port port = dig_port->port;
        int i;
 
        BUILD_BUG_ON(sizeof(aux_msg) > 20);
@@ -182,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
                                DP_AUX_FRAME_SYNC_ENABLE);
 
        aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
-                               DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
+               DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
        aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
-                               DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
+               DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
 
        /* Setup AUX registers */
        for (i = 0; i < sizeof(aux_msg); i += 4)